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Differential D149481

[TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT.
ClosedPublic

Authored by craig.topper on Apr 28 2023, 1:32 PM.

Details

Reviewers
efriedma
dmgreen
RKSimon
SjoerdMeijer
Commits
rGdf017ba9d33f: [TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT.
Summary

This function gets called for vectors and ISD::SELECT_CC was never
intended to support vectors. Some updates were made to support
it when this function started getting used for vectors.

Overall, using separate ISD::SETCC and ISD::SELECT looks like an
improvement even for scalar.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 28 2023, 1:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2023, 1:32 PM
Herald added subscribers: luke, frasercrmck, luismarques and 21 others. · View Herald Transcript
craig.topper requested review of this revision.Apr 28 2023, 1:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2023, 1:32 PM
Herald added subscribers: • pcwang-thead, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B228911: Diff 518038.Apr 28 2023, 2:25 PM
craig.topper added inline comments.Apr 28 2023, 3:59 PM
llvm/test/CodeGen/RISCV/float-convert.ll
537

The xori+addi here are equivalent to neg. I'll fix this in a follow up patch.

craig.topper updated this revision to Diff 518097.Apr 28 2023, 5:04 PM

Rebase after fixing (addi (xor (setcc X, Y), 1) -1) on RISC-V

Harbormaster completed remote builds in B228959: Diff 518097.Apr 28 2023, 6:32 PM
RKSimon accepted this revision.Apr 29 2023, 9:57 AM

LGTM

This revision is now accepted and ready to land.Apr 29 2023, 9:57 AM
nikic added a subscriber: nikic.Apr 29 2023, 10:05 AM

Why is SELECT_CC a thing at all?

Closed by commit rGdf017ba9d33f: [TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT. (authored by craig.topper). · Explain WhyApr 29 2023, 10:23 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGdf017ba9d33f: [TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT..
efriedma added a comment.May 1 2023, 3:28 PM

Why is SELECT_CC a thing at all?

On targets where compare instructions modify a flag register, "SELECT" and "BRCOND" aren't really the natural representation; it effectively makes x != 0 a special case. SELECT_CC and BR_CC represent the combination of a comparison followed by a branch.

That said, a lot of of targets with a flag register prefer to to custom-lower SETCC anyway, so maybe it's not as useful today.

barannikov88 added a subscriber: barannikov88.May 1 2023, 4:09 PM
In D149481#4311028, @efriedma wrote:

Why is SELECT_CC a thing at all?

On targets where compare instructions modify a flag register, "SELECT" and "BRCOND" aren't really the natural representation; it effectively makes x != 0 a special case. SELECT_CC and BR_CC represent the combination of a comparison followed by a branch.

FWIW on such targets neither of these are natural. CC versions are just slightly
easier to lower (saves a couple lines of code).
I wish these nodes were not there when I started bringing up a new backend
and that I didn't read the comments saying "CC" versions are more natural.
This would save me quite a lot of time.

That said, a lot of of targets with a flag register prefer to to custom-lower SETCC anyway, so maybe it's not as useful today.

These nodes are just a redundancy (like a "not x" compared to "xor x, ~0").
I'm glad RISC-V doesn't use them, even though BR_CC is pertty much natural.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
20 lines
test/
CodeGen/
ARM/
1387 lines
1093 lines
RISCV/
152 lines
175 lines
132 lines
315 lines
284 lines
630 lines
rvv/
40 lines
Thumb2/
1587 lines
1172 lines
X86/
72 lines

Diff 518038

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 10,302 Lines • ▼ Show 20 Lines if (AreExactFloatBounds && MinMaxLegal) {
// In the unsigned case we're done, because we mapped NaN to MinFloat, // In the unsigned case we're done, because we mapped NaN to MinFloat,
// which will cast to zero. // which will cast to zero.
if (!IsSigned) if (!IsSigned)
return FpToInt; return FpToInt;
// Otherwise, select 0 if Src is NaN. // Otherwise, select 0 if Src is NaN.
SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); SDValue ZeroInt = DAG.getConstant(0, dl, DstVT);
return DAG.getSelectCC(dl, Src, Src, ZeroInt, FpToInt, EVT SetCCVT =
ISD::CondCode::SETUO); getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
SDValue IsNan = DAG.getSetCC(dl, SetCCVT, Src, Src, ISD::CondCode::SETUO);
return DAG.getSelect(dl, DstVT, IsNan, ZeroInt, FpToInt);
} }
SDValue MinIntNode = DAG.getConstant(MinInt, dl, DstVT); SDValue MinIntNode = DAG.getConstant(MinInt, dl, DstVT);
SDValue MaxIntNode = DAG.getConstant(MaxInt, dl, DstVT); SDValue MaxIntNode = DAG.getConstant(MaxInt, dl, DstVT);
// Result of direct conversion. The assumption here is that the operation is // Result of direct conversion. The assumption here is that the operation is
// non-trapping and it's fine to apply it to an out-of-range value if we // non-trapping and it's fine to apply it to an out-of-range value if we
// select it away later. // select it away later.
SDValue FpToInt = SDValue FpToInt =
DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src); DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src);
SDValue Select = FpToInt; SDValue Select = FpToInt;
EVT SetCCVT =
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
// If Src ULT MinFloat, select MinInt. In particular, this also selects // If Src ULT MinFloat, select MinInt. In particular, this also selects
// MinInt if Src is NaN. // MinInt if Src is NaN.
Select = DAG.getSelectCC(dl, Src, MinFloatNode, MinIntNode, Select, SDValue ULT = DAG.getSetCC(dl, SetCCVT, Src, MinFloatNode, ISD::SETULT);
ISD::CondCode::SETULT); Select = DAG.getSelect(dl, DstVT, ULT, MinIntNode, Select);
// If Src OGT MaxFloat, select MaxInt. // If Src OGT MaxFloat, select MaxInt.
Select = DAG.getSelectCC(dl, Src, MaxFloatNode, MaxIntNode, Select, SDValue OGT = DAG.getSetCC(dl, SetCCVT, Src, MaxFloatNode, ISD::SETOGT);
ISD::CondCode::SETOGT); Select = DAG.getSelect(dl, DstVT, OGT, MaxIntNode, Select);
// In the unsigned case we are done, because we mapped NaN to MinInt, which // In the unsigned case we are done, because we mapped NaN to MinInt, which
// is already zero. // is already zero.
if (!IsSigned) if (!IsSigned)
return Select; return Select;
// Otherwise, select 0 if Src is NaN. // Otherwise, select 0 if Src is NaN.
SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); SDValue ZeroInt = DAG.getConstant(0, dl, DstVT);
return DAG.getSelectCC(dl, Src, Src, ZeroInt, Select, ISD::CondCode::SETUO); SDValue IsNan = DAG.getSetCC(dl, SetCCVT, Src, Src, ISD::CondCode::SETUO);
return DAG.getSelect(dl, DstVT, IsNan, ZeroInt, Select);
} }
SDValue TargetLowering::expandVectorSplice(SDNode *Node, SDValue TargetLowering::expandVectorSplice(SDNode *Node,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!"); assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!");
assert(Node->getValueType(0).isScalableVector() && assert(Node->getValueType(0).isScalableVector() &&
"Fixed length vector types expected to use SHUFFLE_VECTOR!"); "Fixed length vector types expected to use SHUFFLE_VECTOR!");
▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll

Show First 20 Lines • Show All 565 Lines • ▼ Show 20 Lines
define i50 @test_signed_i50_f32(float %f) nounwind { define i50 @test_signed_i50_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i50_f32: ; SOFT-LABEL: test_signed_i50_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI6_0 ; SOFT-NEXT: ldr r1, .LCPI6_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: movs r0, #27 ; SOFT-NEXT: movs r0, #27
; SOFT-NEXT: lsls r5, r0, #27 ; SOFT-NEXT: lsls r1, r0, #27
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2lz ; SOFT-NEXT: bl __aeabi_f2lz
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB6_2 ; SOFT-NEXT: bne .LBB6_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r6, r7 ; SOFT-NEXT: mov r4, r5
; SOFT-NEXT: .LBB6_2: ; SOFT-NEXT: .LBB6_2:
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB6_4 ; SOFT-NEXT: beq .LBB6_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r6, r7 ; SOFT-NEXT: mvns r4, r6
; SOFT-NEXT: .LBB6_4: ; SOFT-NEXT: .LBB6_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB6_6 ; SOFT-NEXT: bne .LBB6_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: .LBB6_6:
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: .LBB6_6:
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB6_8 ; SOFT-NEXT: beq .LBB6_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r5, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: b .LBB6_9 ; SOFT-NEXT: b .LBB6_9
; SOFT-NEXT: .LBB6_8: ; SOFT-NEXT: .LBB6_8:
; SOFT-NEXT: ldr r5, .LCPI6_1 ; SOFT-NEXT: ldr r3, .LCPI6_1
; SOFT-NEXT: .LBB6_9: ; SOFT-NEXT: .LBB6_9:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, .LCPI6_0 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB6_11 ; SOFT-NEXT: beq .LBB6_11
; SOFT-NEXT: @ %bb.10: ; SOFT-NEXT: @ %bb.10:
; SOFT-NEXT: ldr r5, .LCPI6_2 ; SOFT-NEXT: ldr r3, .LCPI6_2
; SOFT-NEXT: .LBB6_11: ; SOFT-NEXT: .LBB6_11:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB6_13 ; SOFT-NEXT: bne .LBB6_13
; SOFT-NEXT: @ %bb.12: ; SOFT-NEXT: @ %bb.12:
; SOFT-NEXT: mov r7, r5 ; SOFT-NEXT: mov r6, r3
; SOFT-NEXT: .LBB6_13: ; SOFT-NEXT: .LBB6_13:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.14: ; SOFT-NEXT: @ %bb.14:
; SOFT-NEXT: .LCPI6_0: ; SOFT-NEXT: .LCPI6_0:
; SOFT-NEXT: .long 1476395007 @ 0x57ffffff ; SOFT-NEXT: .long 1476395007 @ 0x57ffffff
; SOFT-NEXT: .LCPI6_1: ; SOFT-NEXT: .LCPI6_1:
; SOFT-NEXT: .long 4294836224 @ 0xfffe0000 ; SOFT-NEXT: .long 4294836224 @ 0xfffe0000
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define i64 @test_signed_i64_f32(float %f) nounwind { define i64 @test_signed_i64_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i64_f32: ; SOFT-LABEL: test_signed_i64_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI7_0 ; SOFT-NEXT: ldr r1, .LCPI7_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: movs r0, #223 ; SOFT-NEXT: movs r0, #223
; SOFT-NEXT: lsls r5, r0, #24 ; SOFT-NEXT: lsls r1, r0, #24
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2lz ; SOFT-NEXT: bl __aeabi_f2lz
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB7_2 ; SOFT-NEXT: bne .LBB7_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r6, r7 ; SOFT-NEXT: mov r4, r5
; SOFT-NEXT: .LBB7_2: ; SOFT-NEXT: .LBB7_2:
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB7_4 ; SOFT-NEXT: beq .LBB7_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r6, r7 ; SOFT-NEXT: mvns r4, r6
; SOFT-NEXT: .LBB7_4: ; SOFT-NEXT: .LBB7_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB7_6 ; SOFT-NEXT: bne .LBB7_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: .LBB7_6:
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: .LBB7_6:
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB7_8 ; SOFT-NEXT: beq .LBB7_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r5, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: b .LBB7_9 ; SOFT-NEXT: b .LBB7_9
; SOFT-NEXT: .LBB7_8: ; SOFT-NEXT: .LBB7_8:
; SOFT-NEXT: movs r0, #1 ; SOFT-NEXT: movs r2, #1
; SOFT-NEXT: lsls r5, r0, #31 ; SOFT-NEXT: lsls r3, r2, #31
; SOFT-NEXT: .LBB7_9: ; SOFT-NEXT: .LBB7_9:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, .LCPI7_0 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB7_11 ; SOFT-NEXT: beq .LBB7_11
; SOFT-NEXT: @ %bb.10: ; SOFT-NEXT: @ %bb.10:
; SOFT-NEXT: ldr r5, .LCPI7_1 ; SOFT-NEXT: ldr r3, .LCPI7_1
; SOFT-NEXT: .LBB7_11: ; SOFT-NEXT: .LBB7_11:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB7_13 ; SOFT-NEXT: bne .LBB7_13
; SOFT-NEXT: @ %bb.12: ; SOFT-NEXT: @ %bb.12:
; SOFT-NEXT: mov r7, r5 ; SOFT-NEXT: mov r6, r3
; SOFT-NEXT: .LBB7_13: ; SOFT-NEXT: .LBB7_13:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.14: ; SOFT-NEXT: @ %bb.14:
; SOFT-NEXT: .LCPI7_0: ; SOFT-NEXT: .LCPI7_0:
; SOFT-NEXT: .long 1593835519 @ 0x5effffff ; SOFT-NEXT: .long 1593835519 @ 0x5effffff
; SOFT-NEXT: .LCPI7_1: ; SOFT-NEXT: .LCPI7_1:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define i100 @test_signed_i100_f32(float %f) nounwind { define i100 @test_signed_i100_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i100_f32: ; SOFT-LABEL: test_signed_i100_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #20
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #20
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: ldr r1, .LCPI8_0 ; SOFT-NEXT: ldr r1, .LCPI8_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r0, #241 ; SOFT-NEXT: movs r0, #241
; SOFT-NEXT: lsls r5, r0, #24 ; SOFT-NEXT: lsls r1, r0, #24
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bl __fixsfti ; SOFT-NEXT: bl __fixsfti
; SOFT-NEXT: str r1, [sp] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB8_2 ; SOFT-NEXT: bne .LBB8_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB8_2: ; SOFT-NEXT: .LBB8_2:
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mvns r1, r6 ; SOFT-NEXT: mvns r1, r5
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: str r4, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r7, r1 ; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: bne .LBB8_4 ; SOFT-NEXT: bne .LBB8_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: .LBB8_4: ; SOFT-NEXT: .LBB8_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: bne .LBB8_6 ; SOFT-NEXT: bne .LBB8_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB8_6:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI8_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: .LBB8_6:
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: bne .LBB8_8 ; SOFT-NEXT: bne .LBB8_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: str r7, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: .LBB8_8: ; SOFT-NEXT: .LBB8_8:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: bne .LBB8_10 ; SOFT-NEXT: bne .LBB8_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB8_10: ; SOFT-NEXT: .LBB8_10:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: beq .LBB8_18
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB8_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB8_19
; SOFT-NEXT: .LBB8_12: ; SOFT-NEXT: .LBB8_12:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI8_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB8_14 ; SOFT-NEXT: bne .LBB8_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB8_13:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB8_14: ; SOFT-NEXT: .LBB8_14:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: bne .LBB8_16 ; SOFT-NEXT: bne .LBB8_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: .LBB8_16: ; SOFT-NEXT: .LBB8_16:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: movs r4, #7
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: beq .LBB8_20
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: bne .LBB8_18
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload
; SOFT-NEXT: b .LBB8_21
; SOFT-NEXT: .LBB8_18: ; SOFT-NEXT: .LBB8_18:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bne .LBB8_12
; SOFT-NEXT: movs r5, #7 ; SOFT-NEXT: .LBB8_19:
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: str r7, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: bne .LBB8_20 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: @ %bb.19: ; SOFT-NEXT: beq .LBB8_13
; SOFT-NEXT: mvns r0, r5 ; SOFT-NEXT: b .LBB8_14
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: .LBB8_20: ; SOFT-NEXT: .LBB8_20:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mvns r7, r4
; SOFT-NEXT: ldr r1, .LCPI8_0 ; SOFT-NEXT: .LBB8_21:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB8_22 ; SOFT-NEXT: bne .LBB8_23
; SOFT-NEXT: @ %bb.21: ; SOFT-NEXT: @ %bb.22:
; SOFT-NEXT: ldr r5, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: .LBB8_22: ; SOFT-NEXT: .LBB8_23:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: bne .LBB8_25
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: @ %bb.24:
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: mov r5, r4
; SOFT-NEXT: bne .LBB8_24 ; SOFT-NEXT: .LBB8_25:
; SOFT-NEXT: @ %bb.23: ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: mov r6, r5
; SOFT-NEXT: .LBB8_24:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp] @ 4-byte Reload
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #20
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.25: ; SOFT-NEXT: @ %bb.26:
; SOFT-NEXT: .LCPI8_0: ; SOFT-NEXT: .LCPI8_0:
; SOFT-NEXT: .long 1895825407 @ 0x70ffffff ; SOFT-NEXT: .long 1895825407 @ 0x70ffffff
; ;
; VFP-LABEL: test_signed_i100_f32: ; VFP-LABEL: test_signed_i100_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: .save {r4, lr} ; VFP-NEXT: .save {r4, lr}
; VFP-NEXT: push {r4, lr} ; VFP-NEXT: push {r4, lr}
; VFP-NEXT: mov r4, r0 ; VFP-NEXT: mov r4, r0
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
define i128 @test_signed_i128_f32(float %f) nounwind { define i128 @test_signed_i128_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i128_f32: ; SOFT-LABEL: test_signed_i128_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #20
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #20
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: ldr r1, .LCPI9_0 ; SOFT-NEXT: ldr r1, .LCPI9_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r0, #255 ; SOFT-NEXT: movs r0, #255
; SOFT-NEXT: lsls r7, r0, #24 ; SOFT-NEXT: lsls r1, r0, #24
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bl __fixsfti ; SOFT-NEXT: bl __fixsfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB9_2 ; SOFT-NEXT: bne .LBB9_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB9_2: ; SOFT-NEXT: .LBB9_2:
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mvns r1, r6 ; SOFT-NEXT: mvns r1, r5
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: str r4, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: bne .LBB9_4 ; SOFT-NEXT: bne .LBB9_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: .LBB9_4: ; SOFT-NEXT: .LBB9_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: bne .LBB9_6 ; SOFT-NEXT: bne .LBB9_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB9_6:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI9_0 ; SOFT-NEXT: .LBB9_6:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB9_8 ; SOFT-NEXT: bne .LBB9_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r7, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: .LBB9_8: ; SOFT-NEXT: .LBB9_8:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r5, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: bne .LBB9_10 ; SOFT-NEXT: bne .LBB9_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: ldr r5, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB9_10: ; SOFT-NEXT: .LBB9_10:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: beq .LBB9_18
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB9_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB9_19
; SOFT-NEXT: .LBB9_12: ; SOFT-NEXT: .LBB9_12:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI9_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB9_14 ; SOFT-NEXT: bne .LBB9_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB9_13:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB9_14: ; SOFT-NEXT: .LBB9_14:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: bne .LBB9_16 ; SOFT-NEXT: bne .LBB9_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: .LBB9_16: ; SOFT-NEXT: .LBB9_16:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: beq .LBB9_20
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: bne .LBB9_18
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: ldr r5, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r6, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB9_21
; SOFT-NEXT: b .LBB9_22
; SOFT-NEXT: .LBB9_18: ; SOFT-NEXT: .LBB9_18:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bne .LBB9_12
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: .LBB9_19:
; SOFT-NEXT: beq .LBB9_20 ; SOFT-NEXT: str r7, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: @ %bb.19: ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload ; SOFT-NEXT: beq .LBB9_13
; SOFT-NEXT: b .LBB9_21 ; SOFT-NEXT: b .LBB9_14
; SOFT-NEXT: .LBB9_20: ; SOFT-NEXT: .LBB9_20:
; SOFT-NEXT: movs r0, #1 ; SOFT-NEXT: movs r4, #1
; SOFT-NEXT: lsls r7, r0, #31 ; SOFT-NEXT: lsls r6, r4, #31
; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB9_22
; SOFT-NEXT: .LBB9_21: ; SOFT-NEXT: .LBB9_21:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: ldr r6, .LCPI9_1
; SOFT-NEXT: ldr r1, .LCPI9_0 ; SOFT-NEXT: .LBB9_22:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: bne .LBB9_24
; SOFT-NEXT: beq .LBB9_23 ; SOFT-NEXT: @ %bb.23:
; SOFT-NEXT: @ %bb.22: ; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: ldr r7, .LCPI9_1 ; SOFT-NEXT: .LBB9_24:
; SOFT-NEXT: .LBB9_23: ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB9_25
; SOFT-NEXT: @ %bb.24:
; SOFT-NEXT: mov r6, r7
; SOFT-NEXT: .LBB9_25:
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #20
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.26: ; SOFT-NEXT: @ %bb.25:
; SOFT-NEXT: .LCPI9_0: ; SOFT-NEXT: .LCPI9_0:
; SOFT-NEXT: .long 2130706431 @ 0x7effffff ; SOFT-NEXT: .long 2130706431 @ 0x7effffff
; SOFT-NEXT: .LCPI9_1: ; SOFT-NEXT: .LCPI9_1:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP-LABEL: test_signed_i128_f32: ; VFP-LABEL: test_signed_i128_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: .save {r4, lr} ; VFP-NEXT: .save {r4, lr}
▲ Show 20 Lines • Show All 714 Lines • ▼ Show 20 Lines; FP16-NEXT: bx lr
ret i32 %x ret i32 %x
} }
define i50 @test_signed_i50_f64(double %f) nounwind { define i50 @test_signed_i50_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i50_f64: ; SOFT-LABEL: test_signed_i50_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r4, r1 ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: movs r0, #15 ; SOFT-NEXT: movs r0, #15
; SOFT-NEXT: mvns r2, r0 ; SOFT-NEXT: mvns r2, r0
; SOFT-NEXT: ldr r3, .LCPI16_0 ; SOFT-NEXT: ldr r3, .LCPI16_0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: movs r0, #195 ; SOFT-NEXT: movs r0, #195
; SOFT-NEXT: lsls r3, r0, #24 ; SOFT-NEXT: lsls r3, r0, #24
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r4, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: str r3, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_d2lz ; SOFT-NEXT: bl __aeabi_d2lz
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: mov r2, r0
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB16_2 ; SOFT-NEXT: bne .LBB16_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: .LBB16_2: ; SOFT-NEXT: .LBB16_2:
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB16_4 ; SOFT-NEXT: bne .LBB16_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: str r2, [sp] @ 4-byte Spill
; SOFT-NEXT: b .LBB16_5 ; SOFT-NEXT: b .LBB16_5
; SOFT-NEXT: .LBB16_4: ; SOFT-NEXT: .LBB16_4:
; SOFT-NEXT: mvns r7, r6 ; SOFT-NEXT: mvns r0, r4
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: .LBB16_5: ; SOFT-NEXT: .LBB16_5:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r2, r5 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r4 ; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpun ; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB16_7 ; SOFT-NEXT: bne .LBB16_7
; SOFT-NEXT: @ %bb.6: ; SOFT-NEXT: @ %bb.6:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: .LBB16_7: ; SOFT-NEXT: .LBB16_7:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: beq .LBB16_9
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI16_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: ldr r3, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB16_9
; SOFT-NEXT: @ %bb.8: ; SOFT-NEXT: @ %bb.8:
; SOFT-NEXT: ldr r0, .LCPI16_1 ; SOFT-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: b .LBB16_10
; SOFT-NEXT: .LBB16_9: ; SOFT-NEXT: .LBB16_9:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: ldr r3, .LCPI16_1
; SOFT-NEXT: bne .LBB16_11 ; SOFT-NEXT: .LBB16_10:
; SOFT-NEXT: @ %bb.10: ; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: b .LBB16_12 ; SOFT-NEXT: beq .LBB16_12
; SOFT-NEXT: .LBB16_11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: ldr r7, .LCPI16_2 ; SOFT-NEXT: ldr r3, .LCPI16_2
; SOFT-NEXT: .LBB16_12: ; SOFT-NEXT: .LBB16_12:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB16_14 ; SOFT-NEXT: bne .LBB16_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: @ %bb.13:
; SOFT-NEXT: mov r6, r7 ; SOFT-NEXT: mov r4, r3
; SOFT-NEXT: .LBB16_14: ; SOFT-NEXT: .LBB16_14:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: add sp, #12
; SOFT-NEXT: add sp, #20
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: .LCPI16_0: ; SOFT-NEXT: .LCPI16_0:
; SOFT-NEXT: .long 1124073471 @ 0x42ffffff ; SOFT-NEXT: .long 1124073471 @ 0x42ffffff
; SOFT-NEXT: .LCPI16_1: ; SOFT-NEXT: .LCPI16_1:
; SOFT-NEXT: .long 4294836224 @ 0xfffe0000 ; SOFT-NEXT: .long 4294836224 @ 0xfffe0000
; SOFT-NEXT: .LCPI16_2: ; SOFT-NEXT: .LCPI16_2:
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
define i64 @test_signed_i64_f64(double %f) nounwind { define i64 @test_signed_i64_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i64_f64: ; SOFT-LABEL: test_signed_i64_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: mov r6, r1
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: movs r4, #0 ; SOFT-NEXT: movs r4, #0
; SOFT-NEXT: mvns r2, r4 ; SOFT-NEXT: mvns r2, r4
; SOFT-NEXT: ldr r3, .LCPI17_0 ; SOFT-NEXT: ldr r3, .LCPI17_0
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: ldr r3, .LCPI17_1 ; SOFT-NEXT: ldr r3, .LCPI17_1
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r2, r4 ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_d2lz ; SOFT-NEXT: bl __aeabi_d2lz
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB17_2 ; SOFT-NEXT: bne .LBB17_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB17_2: ; SOFT-NEXT: .LBB17_2:
; SOFT-NEXT: ldr r1, [sp] @ 4-byte Reload ; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: bne .LBB17_4 ; SOFT-NEXT: bne .LBB17_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: .LBB17_4: ; SOFT-NEXT: .LBB17_4:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r5 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpun ; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB17_6 ; SOFT-NEXT: bne .LBB17_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB17_6: ; SOFT-NEXT: .LBB17_6:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: beq .LBB17_8
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI17_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI17_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB17_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: movs r0, #1 ; SOFT-NEXT: ldr r3, [sp] @ 4-byte Reload
; SOFT-NEXT: lsls r0, r0, #31 ; SOFT-NEXT: b .LBB17_9
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: .LBB17_8: ; SOFT-NEXT: .LBB17_8:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: movs r2, #1
; SOFT-NEXT: bne .LBB17_10 ; SOFT-NEXT: lsls r3, r2, #31
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: .LBB17_9:
; SOFT-NEXT: ldr r7, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: b .LBB17_11 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: .LBB17_10: ; SOFT-NEXT: beq .LBB17_11
; SOFT-NEXT: ldr r7, .LCPI17_2 ; SOFT-NEXT: @ %bb.10:
; SOFT-NEXT: ldr r3, .LCPI17_2
; SOFT-NEXT: .LBB17_11: ; SOFT-NEXT: .LBB17_11:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB17_13 ; SOFT-NEXT: bne .LBB17_13
; SOFT-NEXT: @ %bb.12: ; SOFT-NEXT: @ %bb.12:
; SOFT-NEXT: mov r4, r7 ; SOFT-NEXT: mov r4, r3
; SOFT-NEXT: .LBB17_13: ; SOFT-NEXT: .LBB17_13:
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.14: ; SOFT-NEXT: @ %bb.14:
; SOFT-NEXT: .LCPI17_0: ; SOFT-NEXT: .LCPI17_0:
; SOFT-NEXT: .long 1138753535 @ 0x43dfffff ; SOFT-NEXT: .long 1138753535 @ 0x43dfffff
; SOFT-NEXT: .LCPI17_1: ; SOFT-NEXT: .LCPI17_1:
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 1138753535
ret i64 %x ret i64 %x
} }
define i100 @test_signed_i100_f64(double %f) nounwind { define i100 @test_signed_i100_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i100_f64: ; SOFT-LABEL: test_signed_i100_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #28
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #28
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: mov r5, r1
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: movs r4, #0 ; SOFT-NEXT: movs r4, #0
; SOFT-NEXT: mvns r2, r4 ; SOFT-NEXT: mvns r2, r4
; SOFT-NEXT: ldr r3, .LCPI18_0 ; SOFT-NEXT: ldr r3, .LCPI18_0
; SOFT-NEXT: str r2, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #24] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #20] @ 4-byte Spill
; SOFT-NEXT: ldr r3, .LCPI18_1 ; SOFT-NEXT: ldr r3, .LCPI18_1
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4 ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __fixdfti ; SOFT-NEXT: bl __fixdfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB18_2 ; SOFT-NEXT: bne .LBB18_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB18_2: ; SOFT-NEXT: .LBB18_2:
; SOFT-NEXT: str r3, [sp] @ 4-byte Spill ; SOFT-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: bne .LBB18_4 ; SOFT-NEXT: bne .LBB18_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: .LBB18_4: ; SOFT-NEXT: .LBB18_4:
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5 ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun ; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB18_6 ; SOFT-NEXT: bne .LBB18_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB18_6: ; SOFT-NEXT: .LBB18_6:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: ldr r6, [sp, #20] @ 4-byte Reload
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI18_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI18_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB18_8 ; SOFT-NEXT: bne .LBB18_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r7, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: .LBB18_8: ; SOFT-NEXT: .LBB18_8:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: bne .LBB18_10 ; SOFT-NEXT: bne .LBB18_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: ldr r7, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB18_10: ; SOFT-NEXT: .LBB18_10:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: beq .LBB18_18
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB18_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB18_19
; SOFT-NEXT: .LBB18_12: ; SOFT-NEXT: .LBB18_12:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI18_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI18_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB18_14 ; SOFT-NEXT: bne .LBB18_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB18_13:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: str r2, [sp, #24] @ 4-byte Spill
; SOFT-NEXT: .LBB18_14: ; SOFT-NEXT: .LBB18_14:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bne .LBB18_16 ; SOFT-NEXT: bne .LBB18_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r7, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: .LBB18_16: ; SOFT-NEXT: .LBB18_16:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: movs r5, #7
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: beq .LBB18_20
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB18_18
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB18_21
; SOFT-NEXT: b .LBB18_22
; SOFT-NEXT: .LBB18_18: ; SOFT-NEXT: .LBB18_18:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: bne .LBB18_12
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: .LBB18_19:
; SOFT-NEXT: ldr r3, .LCPI18_0 ; SOFT-NEXT: str r7, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: beq .LBB18_13
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: b .LBB18_14
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI18_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: movs r7, #7
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB18_20
; SOFT-NEXT: @ %bb.19:
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: b .LBB18_21
; SOFT-NEXT: .LBB18_20: ; SOFT-NEXT: .LBB18_20:
; SOFT-NEXT: mvns r0, r7 ; SOFT-NEXT: mvns r7, r5
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB18_22
; SOFT-NEXT: .LBB18_21: ; SOFT-NEXT: .LBB18_21:
; SOFT-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: mov r5, r7
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: .LBB18_22:
; SOFT-NEXT: bne .LBB18_23 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: @ %bb.22: ; SOFT-NEXT: bne .LBB18_24
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: @ %bb.23:
; SOFT-NEXT: .LBB18_23: ; SOFT-NEXT: mov r4, r5
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: .LBB18_24:
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB18_25
; SOFT-NEXT: @ %bb.24:
; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: .LBB18_25:
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: mov r3, r4 ; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #28
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.26: ; SOFT-NEXT: @ %bb.25:
; SOFT-NEXT: .LCPI18_0: ; SOFT-NEXT: .LCPI18_0:
; SOFT-NEXT: .long 1176502271 @ 0x461fffff ; SOFT-NEXT: .long 1176502271 @ 0x461fffff
; SOFT-NEXT: .LCPI18_1: ; SOFT-NEXT: .LCPI18_1:
; SOFT-NEXT: .long 3323985920 @ 0xc6200000 ; SOFT-NEXT: .long 3323985920 @ 0xc6200000
; ;
; VFP2-LABEL: test_signed_i100_f64: ; VFP2-LABEL: test_signed_i100_f64:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 1176502271
ret i100 %x ret i100 %x
} }
define i128 @test_signed_i128_f64(double %f) nounwind { define i128 @test_signed_i128_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i128_f64: ; SOFT-LABEL: test_signed_i128_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #28
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #28
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: mov r5, r1
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: movs r4, #0 ; SOFT-NEXT: movs r4, #0
; SOFT-NEXT: mvns r2, r4 ; SOFT-NEXT: mvns r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_0 ; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: str r2, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #24] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #20] @ 4-byte Spill
; SOFT-NEXT: ldr r3, .LCPI19_1 ; SOFT-NEXT: ldr r3, .LCPI19_1
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4 ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __fixdfti ; SOFT-NEXT: bl __fixdfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB19_2 ; SOFT-NEXT: bne .LBB19_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB19_2: ; SOFT-NEXT: .LBB19_2:
; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: bne .LBB19_4 ; SOFT-NEXT: bne .LBB19_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: .LBB19_4: ; SOFT-NEXT: .LBB19_4:
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5 ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun ; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB19_6 ; SOFT-NEXT: bne .LBB19_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB19_6: ; SOFT-NEXT: .LBB19_6:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: ldr r6, [sp, #20] @ 4-byte Reload
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_8 ; SOFT-NEXT: bne .LBB19_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r7, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: .LBB19_8: ; SOFT-NEXT: .LBB19_8:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: bne .LBB19_10 ; SOFT-NEXT: bne .LBB19_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: ldr r7, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB19_10: ; SOFT-NEXT: .LBB19_10:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: beq .LBB19_18
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB19_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB19_19
; SOFT-NEXT: .LBB19_12: ; SOFT-NEXT: .LBB19_12:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_14 ; SOFT-NEXT: bne .LBB19_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB19_13:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: str r2, [sp, #24] @ 4-byte Spill
; SOFT-NEXT: .LBB19_14: ; SOFT-NEXT: .LBB19_14:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bne .LBB19_16 ; SOFT-NEXT: bne .LBB19_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: .LBB19_16: ; SOFT-NEXT: .LBB19_16:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: beq .LBB19_20
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: bne .LBB19_18
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB19_21
; SOFT-NEXT: b .LBB19_22
; SOFT-NEXT: .LBB19_18: ; SOFT-NEXT: .LBB19_18:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_1
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_20
; SOFT-NEXT: @ %bb.19:
; SOFT-NEXT: movs r0, #1
; SOFT-NEXT: lsls r0, r0, #31
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: .LBB19_20:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB19_22 ; SOFT-NEXT: bne .LBB19_12
; SOFT-NEXT: @ %bb.21: ; SOFT-NEXT: .LBB19_19:
; SOFT-NEXT: ldr r7, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: str r7, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: b .LBB19_23 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB19_13
; SOFT-NEXT: b .LBB19_14
; SOFT-NEXT: .LBB19_20:
; SOFT-NEXT: movs r5, #1
; SOFT-NEXT: lsls r5, r5, #31
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB19_22
; SOFT-NEXT: .LBB19_21:
; SOFT-NEXT: ldr r5, .LCPI19_2
; SOFT-NEXT: .LBB19_22: ; SOFT-NEXT: .LBB19_22:
; SOFT-NEXT: ldr r7, .LCPI19_2 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: .LBB19_23: ; SOFT-NEXT: bne .LBB19_24
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: @ %bb.23:
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r4, r5
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: .LBB19_24:
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_25
; SOFT-NEXT: @ %bb.24:
; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: .LBB19_25:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: ldr r2, [sp] @ 4-byte Reload
; SOFT-NEXT: mov r3, r4 ; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #28
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.26: ; SOFT-NEXT: @ %bb.25:
; SOFT-NEXT: .LCPI19_0: ; SOFT-NEXT: .LCPI19_0:
; SOFT-NEXT: .long 1205862399 @ 0x47dfffff ; SOFT-NEXT: .long 1205862399 @ 0x47dfffff
; SOFT-NEXT: .LCPI19_1: ; SOFT-NEXT: .LCPI19_1:
; SOFT-NEXT: .long 3353346048 @ 0xc7e00000 ; SOFT-NEXT: .long 3353346048 @ 0xc7e00000
; SOFT-NEXT: .LCPI19_2: ; SOFT-NEXT: .LCPI19_2:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: test_signed_i128_f64: ; VFP2-LABEL: test_signed_i128_f64:
▲ Show 20 Lines • Show All 742 Lines • ▼ Show 20 Lines
; SOFT-LABEL: test_signed_i50_f16: ; SOFT-LABEL: test_signed_i50_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI26_0 ; SOFT-NEXT: ldr r1, .LCPI26_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: movs r0, #27 ; SOFT-NEXT: movs r0, #27
; SOFT-NEXT: lsls r5, r0, #27 ; SOFT-NEXT: lsls r1, r0, #27
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2lz ; SOFT-NEXT: bl __aeabi_f2lz
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB26_2 ; SOFT-NEXT: bne .LBB26_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r6, r7 ; SOFT-NEXT: mov r4, r5
; SOFT-NEXT: .LBB26_2: ; SOFT-NEXT: .LBB26_2:
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB26_4 ; SOFT-NEXT: beq .LBB26_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r6, r7 ; SOFT-NEXT: mvns r4, r6
; SOFT-NEXT: .LBB26_4: ; SOFT-NEXT: .LBB26_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB26_6 ; SOFT-NEXT: bne .LBB26_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: .LBB26_6:
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: .LBB26_6:
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB26_8 ; SOFT-NEXT: beq .LBB26_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r5, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: b .LBB26_9 ; SOFT-NEXT: b .LBB26_9
; SOFT-NEXT: .LBB26_8: ; SOFT-NEXT: .LBB26_8:
; SOFT-NEXT: ldr r5, .LCPI26_1 ; SOFT-NEXT: ldr r3, .LCPI26_1
; SOFT-NEXT: .LBB26_9: ; SOFT-NEXT: .LBB26_9:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, .LCPI26_0 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB26_11 ; SOFT-NEXT: beq .LBB26_11
; SOFT-NEXT: @ %bb.10: ; SOFT-NEXT: @ %bb.10:
; SOFT-NEXT: ldr r5, .LCPI26_2 ; SOFT-NEXT: ldr r3, .LCPI26_2
; SOFT-NEXT: .LBB26_11: ; SOFT-NEXT: .LBB26_11:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB26_13 ; SOFT-NEXT: bne .LBB26_13
; SOFT-NEXT: @ %bb.12: ; SOFT-NEXT: @ %bb.12:
; SOFT-NEXT: mov r7, r5 ; SOFT-NEXT: mov r6, r3
; SOFT-NEXT: .LBB26_13: ; SOFT-NEXT: .LBB26_13:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.14: ; SOFT-NEXT: @ %bb.14:
; SOFT-NEXT: .LCPI26_0: ; SOFT-NEXT: .LCPI26_0:
; SOFT-NEXT: .long 1476395007 @ 0x57ffffff ; SOFT-NEXT: .long 1476395007 @ 0x57ffffff
; SOFT-NEXT: .LCPI26_1: ; SOFT-NEXT: .LCPI26_1:
; SOFT-NEXT: .long 4294836224 @ 0xfffe0000 ; SOFT-NEXT: .long 4294836224 @ 0xfffe0000
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; SOFT-LABEL: test_signed_i64_f16: ; SOFT-LABEL: test_signed_i64_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #12
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #12
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI27_0 ; SOFT-NEXT: ldr r1, .LCPI27_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: movs r0, #223 ; SOFT-NEXT: movs r0, #223
; SOFT-NEXT: lsls r5, r0, #24 ; SOFT-NEXT: lsls r1, r0, #24
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2lz ; SOFT-NEXT: bl __aeabi_f2lz
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB27_2 ; SOFT-NEXT: bne .LBB27_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r6, r7 ; SOFT-NEXT: mov r4, r5
; SOFT-NEXT: .LBB27_2: ; SOFT-NEXT: .LBB27_2:
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB27_4 ; SOFT-NEXT: beq .LBB27_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r6, r7 ; SOFT-NEXT: mvns r4, r6
; SOFT-NEXT: .LBB27_4: ; SOFT-NEXT: .LBB27_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB27_6 ; SOFT-NEXT: bne .LBB27_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: .LBB27_6:
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: .LBB27_6:
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB27_8 ; SOFT-NEXT: beq .LBB27_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r5, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: b .LBB27_9 ; SOFT-NEXT: b .LBB27_9
; SOFT-NEXT: .LBB27_8: ; SOFT-NEXT: .LBB27_8:
; SOFT-NEXT: movs r0, #1 ; SOFT-NEXT: movs r2, #1
; SOFT-NEXT: lsls r5, r0, #31 ; SOFT-NEXT: lsls r3, r2, #31
; SOFT-NEXT: .LBB27_9: ; SOFT-NEXT: .LBB27_9:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, .LCPI27_0 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: beq .LBB27_11 ; SOFT-NEXT: beq .LBB27_11
; SOFT-NEXT: @ %bb.10: ; SOFT-NEXT: @ %bb.10:
; SOFT-NEXT: ldr r5, .LCPI27_1 ; SOFT-NEXT: ldr r3, .LCPI27_1
; SOFT-NEXT: .LBB27_11: ; SOFT-NEXT: .LBB27_11:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB27_13 ; SOFT-NEXT: bne .LBB27_13
; SOFT-NEXT: @ %bb.12: ; SOFT-NEXT: @ %bb.12:
; SOFT-NEXT: mov r7, r5 ; SOFT-NEXT: mov r6, r3
; SOFT-NEXT: .LBB27_13: ; SOFT-NEXT: .LBB27_13:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: add sp, #12
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.14: ; SOFT-NEXT: @ %bb.14:
; SOFT-NEXT: .LCPI27_0: ; SOFT-NEXT: .LCPI27_0:
; SOFT-NEXT: .long 1593835519 @ 0x5effffff ; SOFT-NEXT: .long 1593835519 @ 0x5effffff
; SOFT-NEXT: .LCPI27_1: ; SOFT-NEXT: .LCPI27_1:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; SOFT-LABEL: test_signed_i100_f16: ; SOFT-LABEL: test_signed_i100_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #20
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #20
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: ldr r1, .LCPI28_0 ; SOFT-NEXT: ldr r1, .LCPI28_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r0, #241 ; SOFT-NEXT: movs r0, #241
; SOFT-NEXT: lsls r5, r0, #24 ; SOFT-NEXT: lsls r1, r0, #24
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bl __fixsfti ; SOFT-NEXT: bl __fixsfti
; SOFT-NEXT: str r1, [sp] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB28_2 ; SOFT-NEXT: bne .LBB28_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB28_2: ; SOFT-NEXT: .LBB28_2:
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mvns r1, r6 ; SOFT-NEXT: mvns r1, r5
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: str r4, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r7, r1 ; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: bne .LBB28_4 ; SOFT-NEXT: bne .LBB28_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: .LBB28_4: ; SOFT-NEXT: .LBB28_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: bne .LBB28_6 ; SOFT-NEXT: bne .LBB28_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB28_6:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI28_0 ; SOFT-NEXT: .LBB28_6:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB28_8 ; SOFT-NEXT: bne .LBB28_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: str r7, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: .LBB28_8: ; SOFT-NEXT: .LBB28_8:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: bne .LBB28_10 ; SOFT-NEXT: bne .LBB28_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB28_10: ; SOFT-NEXT: .LBB28_10:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: beq .LBB28_18
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB28_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB28_19
; SOFT-NEXT: .LBB28_12: ; SOFT-NEXT: .LBB28_12:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI28_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB28_14 ; SOFT-NEXT: bne .LBB28_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB28_13:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB28_14: ; SOFT-NEXT: .LBB28_14:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: bne .LBB28_16 ; SOFT-NEXT: bne .LBB28_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: .LBB28_16: ; SOFT-NEXT: .LBB28_16:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: movs r4, #7
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: beq .LBB28_20
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: bne .LBB28_18
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: ldr r7, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload
; SOFT-NEXT: b .LBB28_21
; SOFT-NEXT: .LBB28_18: ; SOFT-NEXT: .LBB28_18:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bne .LBB28_12
; SOFT-NEXT: movs r5, #7 ; SOFT-NEXT: .LBB28_19:
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: str r7, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: bne .LBB28_20 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: @ %bb.19: ; SOFT-NEXT: beq .LBB28_13
; SOFT-NEXT: mvns r0, r5 ; SOFT-NEXT: b .LBB28_14
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: .LBB28_20: ; SOFT-NEXT: .LBB28_20:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mvns r7, r4
; SOFT-NEXT: ldr r1, .LCPI28_0 ; SOFT-NEXT: .LBB28_21:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB28_22 ; SOFT-NEXT: bne .LBB28_23
; SOFT-NEXT: @ %bb.21: ; SOFT-NEXT: @ %bb.22:
; SOFT-NEXT: ldr r5, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: mov r4, r7
; SOFT-NEXT: .LBB28_22: ; SOFT-NEXT: .LBB28_23:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: bne .LBB28_25
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: @ %bb.24:
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: mov r5, r4
; SOFT-NEXT: bne .LBB28_24 ; SOFT-NEXT: .LBB28_25:
; SOFT-NEXT: @ %bb.23: ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: mov r6, r5
; SOFT-NEXT: .LBB28_24:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp] @ 4-byte Reload
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #20
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.25: ; SOFT-NEXT: @ %bb.26:
; SOFT-NEXT: .LCPI28_0: ; SOFT-NEXT: .LCPI28_0:
; SOFT-NEXT: .long 1895825407 @ 0x70ffffff ; SOFT-NEXT: .long 1895825407 @ 0x70ffffff
; ;
; VFP2-LABEL: test_signed_i100_f16: ; VFP2-LABEL: test_signed_i100_f16:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r4, lr} ; VFP2-NEXT: .save {r4, lr}
; VFP2-NEXT: push {r4, lr} ; VFP2-NEXT: push {r4, lr}
; VFP2-NEXT: bl __aeabi_h2f ; VFP2-NEXT: bl __aeabi_h2f
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; SOFT-LABEL: test_signed_i128_f16: ; SOFT-LABEL: test_signed_i128_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #20
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #20
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: ldr r1, .LCPI29_0 ; SOFT-NEXT: ldr r1, .LCPI29_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r0, #255 ; SOFT-NEXT: movs r0, #255
; SOFT-NEXT: lsls r7, r0, #24 ; SOFT-NEXT: lsls r1, r0, #24
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bl __fixsfti ; SOFT-NEXT: bl __fixsfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bne .LBB29_2 ; SOFT-NEXT: bne .LBB29_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: .LBB29_2: ; SOFT-NEXT: .LBB29_2:
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r5, #0
; SOFT-NEXT: mvns r1, r6 ; SOFT-NEXT: mvns r1, r5
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: str r4, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: bne .LBB29_4 ; SOFT-NEXT: bne .LBB29_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: .LBB29_4: ; SOFT-NEXT: .LBB29_4:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: bne .LBB29_6 ; SOFT-NEXT: bne .LBB29_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB29_6:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI29_0 ; SOFT-NEXT: .LBB29_6:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB29_8 ; SOFT-NEXT: bne .LBB29_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: str r7, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: .LBB29_8: ; SOFT-NEXT: .LBB29_8:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r5, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: bne .LBB29_10 ; SOFT-NEXT: bne .LBB29_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: ldr r5, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB29_10: ; SOFT-NEXT: .LBB29_10:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: bl __aeabi_fcmpun ; SOFT-NEXT: beq .LBB29_18
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: bne .LBB29_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: beq .LBB29_19
; SOFT-NEXT: .LBB29_12: ; SOFT-NEXT: .LBB29_12:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI29_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB29_14 ; SOFT-NEXT: bne .LBB29_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB29_13:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB29_14: ; SOFT-NEXT: .LBB29_14:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: bne .LBB29_16 ; SOFT-NEXT: bne .LBB29_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill
; SOFT-NEXT: .LBB29_16: ; SOFT-NEXT: .LBB29_16:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: beq .LBB29_20
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: bne .LBB29_18
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: ldr r5, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r6, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB29_21
; SOFT-NEXT: b .LBB29_22
; SOFT-NEXT: .LBB29_18: ; SOFT-NEXT: .LBB29_18:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: cmp r7, #0
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bne .LBB29_12
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: .LBB29_19:
; SOFT-NEXT: beq .LBB29_20 ; SOFT-NEXT: str r7, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: @ %bb.19: ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: ldr r7, [sp] @ 4-byte Reload ; SOFT-NEXT: beq .LBB29_13
; SOFT-NEXT: b .LBB29_21 ; SOFT-NEXT: b .LBB29_14
; SOFT-NEXT: .LBB29_20: ; SOFT-NEXT: .LBB29_20:
; SOFT-NEXT: movs r0, #1 ; SOFT-NEXT: movs r4, #1
; SOFT-NEXT: lsls r7, r0, #31 ; SOFT-NEXT: lsls r6, r4, #31
; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB29_22
; SOFT-NEXT: .LBB29_21: ; SOFT-NEXT: .LBB29_21:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: ldr r6, .LCPI29_1
; SOFT-NEXT: ldr r1, .LCPI29_0 ; SOFT-NEXT: .LBB29_22:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: bne .LBB29_24
; SOFT-NEXT: beq .LBB29_23 ; SOFT-NEXT: @ %bb.23:
; SOFT-NEXT: @ %bb.22: ; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: ldr r7, .LCPI29_1 ; SOFT-NEXT: .LBB29_24:
; SOFT-NEXT: .LBB29_23: ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bl __aeabi_fcmpun
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB29_25
; SOFT-NEXT: @ %bb.24:
; SOFT-NEXT: mov r6, r7
; SOFT-NEXT: .LBB29_25:
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #20
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.26: ; SOFT-NEXT: @ %bb.25:
; SOFT-NEXT: .LCPI29_0: ; SOFT-NEXT: .LCPI29_0:
; SOFT-NEXT: .long 2130706431 @ 0x7effffff ; SOFT-NEXT: .long 2130706431 @ 0x7effffff
; SOFT-NEXT: .LCPI29_1: ; SOFT-NEXT: .LCPI29_1:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: test_signed_i128_f16: ; VFP2-LABEL: test_signed_i128_f16:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r4, lr} ; VFP2-NEXT: .save {r4, lr}
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll

Show First 20 Lines • Show All 437 Lines • ▼ Show 20 Lines
define i50 @test_signed_i50_f32(float %f) nounwind { define i50 @test_signed_i50_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i50_f32: ; SOFT-LABEL: test_signed_i50_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #4 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI6_0 ; SOFT-NEXT: ldr r1, .LCPI6_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2ulz ; SOFT-NEXT: bl __aeabi_f2ulz
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB6_2 ; SOFT-NEXT: beq .LBB6_5
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB6_6
; SOFT-NEXT: .LBB6_2: ; SOFT-NEXT: .LBB6_2:
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB6_7
; SOFT-NEXT: .LBB6_3:
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB6_4 ; SOFT-NEXT: bne .LBB6_8
; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r0, r7
; SOFT-NEXT: .LBB6_4: ; SOFT-NEXT: .LBB6_4:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: ldr r1, .LCPI6_0 ; SOFT-NEXT: .LBB6_5:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: beq .LBB6_2
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB6_6
; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: .LBB6_6: ; SOFT-NEXT: .LBB6_6:
; SOFT-NEXT: mvns r0, r6
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB6_3
; SOFT-NEXT: .LBB6_7:
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB6_8 ; SOFT-NEXT: beq .LBB6_4
; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r5, .LCPI6_1
; SOFT-NEXT: .LBB6_8: ; SOFT-NEXT: .LBB6_8:
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload ; SOFT-NEXT: ldr r1, .LCPI6_1
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: add sp, #4 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: .LCPI6_0: ; SOFT-NEXT: .LCPI6_0:
; SOFT-NEXT: .long 1484783615 @ 0x587fffff ; SOFT-NEXT: .long 1484783615 @ 0x587fffff
; SOFT-NEXT: .LCPI6_1: ; SOFT-NEXT: .LCPI6_1:
; SOFT-NEXT: .long 262143 @ 0x3ffff ; SOFT-NEXT: .long 262143 @ 0x3ffff
Show All 28 Lines; VFP-NEXT: .long 0x587fffff @ float 1.12589984E+15
ret i50 %x ret i50 %x
} }
define i64 @test_signed_i64_f32(float %f) nounwind { define i64 @test_signed_i64_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i64_f32: ; SOFT-LABEL: test_signed_i64_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI7_0 ; SOFT-NEXT: ldr r1, .LCPI7_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2ulz ; SOFT-NEXT: bl __aeabi_f2ulz
; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB7_2 ; SOFT-NEXT: bne .LBB7_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: .LBB7_2: ; SOFT-NEXT: .LBB7_2:
; SOFT-NEXT: mvns r5, r7 ; SOFT-NEXT: mvns r2, r6
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: bne .LBB7_4 ; SOFT-NEXT: beq .LBB7_7
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB7_8
; SOFT-NEXT: .LBB7_4: ; SOFT-NEXT: .LBB7_4:
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI7_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB7_6 ; SOFT-NEXT: bne .LBB7_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: .LBB7_5:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r2, r1
; SOFT-NEXT: .LBB7_6: ; SOFT-NEXT: .LBB7_6:
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: bne .LBB7_8 ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: .LBB7_7:
; SOFT-NEXT: ldr r5, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: mov r0, r3
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB7_4
; SOFT-NEXT: .LBB7_8: ; SOFT-NEXT: .LBB7_8:
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: beq .LBB7_5
; SOFT-NEXT: b .LBB7_6
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: .LCPI7_0: ; SOFT-NEXT: .LCPI7_0:
; SOFT-NEXT: .long 1602224127 @ 0x5f7fffff ; SOFT-NEXT: .long 1602224127 @ 0x5f7fffff
; ;
; VFP-LABEL: test_signed_i64_f32: ; VFP-LABEL: test_signed_i64_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: .save {r7, lr} ; VFP-NEXT: .save {r7, lr}
Show All 29 Lines; VFP-NEXT: .long 0x5f7fffff @ float 1.8446743E+19
ret i64 %x ret i64 %x
} }
define i100 @test_signed_i100_f32(float %f) nounwind { define i100 @test_signed_i100_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i100_f32: ; SOFT-LABEL: test_signed_i100_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI8_0 ; SOFT-NEXT: ldr r1, .LCPI8_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __fixunssfti ; SOFT-NEXT: bl __fixunssfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB8_2 ; SOFT-NEXT: bne .LBB8_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB8_2: ; SOFT-NEXT: .LBB8_2:
; SOFT-NEXT: str r3, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: mvns r2, r6
; SOFT-NEXT: mvns r7, r6
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r6, r2
; SOFT-NEXT: bne .LBB8_4 ; SOFT-NEXT: bne .LBB8_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: .LBB8_4: ; SOFT-NEXT: .LBB8_4:
; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: ldr r1, .LCPI8_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB8_6 ; SOFT-NEXT: bne .LBB8_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r5
; SOFT-NEXT: .LBB8_6: ; SOFT-NEXT: .LBB8_6:
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: bne .LBB8_8 ; SOFT-NEXT: beq .LBB8_13
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB8_14
; SOFT-NEXT: .LBB8_8: ; SOFT-NEXT: .LBB8_8:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: beq .LBB8_15
; SOFT-NEXT: ldr r1, .LCPI8_0 ; SOFT-NEXT: .LBB8_9:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: beq .LBB8_16
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB8_10
; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: .LBB8_10: ; SOFT-NEXT: .LBB8_10:
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB8_12 ; SOFT-NEXT: beq .LBB8_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: .LBB8_11:
; SOFT-NEXT: ldr r7, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: movs r3, #15
; SOFT-NEXT: .LBB8_12: ; SOFT-NEXT: .LBB8_12:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: ldr r1, .LCPI8_0 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: .LBB8_13:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bne .LBB8_8
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: bne .LBB8_14
; SOFT-NEXT: @ %bb.13:
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: .LBB8_14: ; SOFT-NEXT: .LBB8_14:
; SOFT-NEXT: str r5, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: bne .LBB8_9
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: .LBB8_15:
; SOFT-NEXT: beq .LBB8_16 ; SOFT-NEXT: ldr r2, [sp] @ 4-byte Reload
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: movs r3, #15 ; SOFT-NEXT: bne .LBB8_10
; SOFT-NEXT: .LBB8_16: ; SOFT-NEXT: .LBB8_16:
; SOFT-NEXT: mov r2, r7 ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: bne .LBB8_11
; SOFT-NEXT: b .LBB8_12
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: .LCPI8_0: ; SOFT-NEXT: .LCPI8_0:
; SOFT-NEXT: .long 1904214015 @ 0x717fffff ; SOFT-NEXT: .long 1904214015 @ 0x717fffff
; ;
; VFP-LABEL: test_signed_i100_f32: ; VFP-LABEL: test_signed_i100_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: .save {r7, lr} ; VFP-NEXT: .save {r7, lr}
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; VFP-NEXT: .long 0x717fffff @ float 1.26765052E+30
ret i100 %x ret i100 %x
} }
define i128 @test_signed_i128_f32(float %f) nounwind { define i128 @test_signed_i128_f32(float %f) nounwind {
; SOFT-LABEL: test_signed_i128_f32: ; SOFT-LABEL: test_signed_i128_f32:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI9_0 ; SOFT-NEXT: ldr r1, .LCPI9_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __fixunssfti ; SOFT-NEXT: bl __fixunssfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB9_2 ; SOFT-NEXT: bne .LBB9_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB9_2: ; SOFT-NEXT: .LBB9_2:
; SOFT-NEXT: mvns r6, r7 ; SOFT-NEXT: mvns r6, r6
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bne .LBB9_4 ; SOFT-NEXT: bne .LBB9_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: .LBB9_4: ; SOFT-NEXT: .LBB9_4:
; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI9_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB9_6 ; SOFT-NEXT: bne .LBB9_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r5
; SOFT-NEXT: .LBB9_6: ; SOFT-NEXT: .LBB9_6:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bne .LBB9_8 ; SOFT-NEXT: bne .LBB9_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB9_8:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI9_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: .LBB9_8:
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB9_10 ; SOFT-NEXT: bne .LBB9_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: .LBB9_10: ; SOFT-NEXT: .LBB9_10:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: bne .LBB9_12 ; SOFT-NEXT: beq .LBB9_15
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB9_16
; SOFT-NEXT: .LBB9_12: ; SOFT-NEXT: .LBB9_12:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI9_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB9_14 ; SOFT-NEXT: bne .LBB9_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB9_13:
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: ldr r6, [sp] @ 4-byte Reload
; SOFT-NEXT: .LBB9_14: ; SOFT-NEXT: .LBB9_14:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: mov r0, r3
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: bne .LBB9_16
; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: .LBB9_16:
; SOFT-NEXT: mov r3, r6 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB9_15:
; SOFT-NEXT: mov r7, r2
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB9_12
; SOFT-NEXT: .LBB9_16:
; SOFT-NEXT: str r5, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB9_13
; SOFT-NEXT: b .LBB9_14
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: .LCPI9_0: ; SOFT-NEXT: .LCPI9_0:
; SOFT-NEXT: .long 2139095039 @ 0x7f7fffff ; SOFT-NEXT: .long 2139095039 @ 0x7f7fffff
; ;
; VFP-LABEL: test_signed_i128_f32: ; VFP-LABEL: test_signed_i128_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: .save {r7, lr} ; VFP-NEXT: .save {r7, lr}
▲ Show 20 Lines • Show All 554 Lines • ▼ Show 20 Lines; FP16-NEXT: bx lr
ret i32 %x ret i32 %x
} }
define i50 @test_signed_i50_f64(double %f) nounwind { define i50 @test_signed_i50_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i50_f64: ; SOFT-LABEL: test_signed_i50_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1 ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r0, #7 ; SOFT-NEXT: movs r0, #7
; SOFT-NEXT: mvns r2, r0 ; SOFT-NEXT: mvns r2, r0
; SOFT-NEXT: ldr r3, .LCPI16_0 ; SOFT-NEXT: ldr r3, .LCPI16_0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: str r2, [sp] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r2, r7 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r7 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_d2ulz ; SOFT-NEXT: bl __aeabi_d2ulz
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB16_2 ; SOFT-NEXT: bne .LBB16_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB16_2: ; SOFT-NEXT: .LBB16_2:
; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r2, #0 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: bne .LBB16_6
; SOFT-NEXT: beq .LBB16_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r0, r7 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB16_7
; SOFT-NEXT: .LBB16_4: ; SOFT-NEXT: .LBB16_4:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: bne .LBB16_8
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: .LBB16_5:
; SOFT-NEXT: ldr r2, [sp] @ 4-byte Reload ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: ldr r3, .LCPI16_0 ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: mov r3, r7
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: bne .LBB16_6
; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r1, r0
; SOFT-NEXT: .LBB16_6: ; SOFT-NEXT: .LBB16_6:
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: mvns r0, r6
; SOFT-NEXT: beq .LBB16_8 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: bne .LBB16_4
; SOFT-NEXT: ldr r1, .LCPI16_1 ; SOFT-NEXT: .LBB16_7:
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: beq .LBB16_5
; SOFT-NEXT: .LBB16_8: ; SOFT-NEXT: .LBB16_8:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r1, .LCPI16_1
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: .LCPI16_0: ; SOFT-NEXT: .LCPI16_0:
; SOFT-NEXT: .long 1125122047 @ 0x430fffff ; SOFT-NEXT: .long 1125122047 @ 0x430fffff
; SOFT-NEXT: .LCPI16_1: ; SOFT-NEXT: .LCPI16_1:
; SOFT-NEXT: .long 262143 @ 0x3ffff ; SOFT-NEXT: .long 262143 @ 0x3ffff
; ;
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 1125122047
ret i50 %x ret i50 %x
} }
define i64 @test_signed_i64_f64(double %f) nounwind { define i64 @test_signed_i64_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i64_f64: ; SOFT-LABEL: test_signed_i64_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mvns r2, r6 ; SOFT-NEXT: mvns r4, r6
; SOFT-NEXT: ldr r3, .LCPI17_0 ; SOFT-NEXT: ldr r3, .LCPI17_0
; SOFT-NEXT: str r2, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_d2ulz ; SOFT-NEXT: bl __aeabi_d2ulz
; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: mov r2, r0
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB17_2 ; SOFT-NEXT: bne .LBB17_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: .LBB17_2: ; SOFT-NEXT: .LBB17_2:
; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: ldr r3, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: ldr r4, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: beq .LBB17_7
; SOFT-NEXT: bne .LBB17_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB17_8
; SOFT-NEXT: .LBB17_4: ; SOFT-NEXT: .LBB17_4:
; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI17_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB17_6 ; SOFT-NEXT: bne .LBB17_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: .LBB17_5:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: .LBB17_6: ; SOFT-NEXT: .LBB17_6:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: bne .LBB17_8
; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r4, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB17_8:
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB17_7:
; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB17_4
; SOFT-NEXT: .LBB17_8:
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: cmp r3, #0
; SOFT-NEXT: beq .LBB17_5
; SOFT-NEXT: b .LBB17_6
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: .LCPI17_0: ; SOFT-NEXT: .LCPI17_0:
; SOFT-NEXT: .long 1139802111 @ 0x43efffff ; SOFT-NEXT: .long 1139802111 @ 0x43efffff
; ;
; VFP2-LABEL: test_signed_i64_f64: ; VFP2-LABEL: test_signed_i64_f64:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 1139802111
ret i64 %x ret i64 %x
} }
define i100 @test_signed_i100_f64(double %f) nounwind { define i100 @test_signed_i100_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i100_f64: ; SOFT-LABEL: test_signed_i100_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #28 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #28 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r4, r1 ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r5, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mvns r2, r5 ; SOFT-NEXT: mvns r2, r6
; SOFT-NEXT: ldr r3, .LCPI18_0 ; SOFT-NEXT: ldr r3, .LCPI18_0
; SOFT-NEXT: str r2, [sp, #20] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp] @ 4-byte Spill
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r2, r5 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r5 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __fixunsdfti ; SOFT-NEXT: bl __fixunsdfti
; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB18_2 ; SOFT-NEXT: bne .LBB18_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r4, r6
; SOFT-NEXT: .LBB18_2: ; SOFT-NEXT: .LBB18_2:
; SOFT-NEXT: str r3, [sp, #24] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: ldr r7, [sp, #20] @ 4-byte Reload
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bne .LBB18_4 ; SOFT-NEXT: bne .LBB18_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: .LBB18_4: ; SOFT-NEXT: .LBB18_4:
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: ldr r3, .LCPI18_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB18_6 ; SOFT-NEXT: bne .LBB18_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: .LBB18_6: ; SOFT-NEXT: .LBB18_6:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: ldr r4, [sp] @ 4-byte Reload
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bne .LBB18_8 ; SOFT-NEXT: beq .LBB18_13
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: beq .LBB18_14
; SOFT-NEXT: .LBB18_8: ; SOFT-NEXT: .LBB18_8:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: beq .LBB18_15
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: .LBB18_9:
; SOFT-NEXT: mov r2, r7 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: ldr r3, .LCPI18_0 ; SOFT-NEXT: beq .LBB18_16
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB18_10
; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill
; SOFT-NEXT: .LBB18_10: ; SOFT-NEXT: .LBB18_10:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: beq .LBB18_12
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: .LBB18_11:
; SOFT-NEXT: bne .LBB18_12 ; SOFT-NEXT: movs r3, #15
; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: .LBB18_12: ; SOFT-NEXT: .LBB18_12:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: mov r1, r4 ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: mov r2, r7 ; SOFT-NEXT: .LBB18_13:
; SOFT-NEXT: ldr r3, .LCPI18_0 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: bne .LBB18_8
; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: ldr r3, [sp, #24] @ 4-byte Reload
; SOFT-NEXT: bne .LBB18_14
; SOFT-NEXT: @ %bb.13:
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: .LBB18_14: ; SOFT-NEXT: .LBB18_14:
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: ldr r0, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: bne .LBB18_9
; SOFT-NEXT: beq .LBB18_16 ; SOFT-NEXT: .LBB18_15:
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: mov r4, r2
; SOFT-NEXT: movs r3, #15 ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB18_10
; SOFT-NEXT: .LBB18_16: ; SOFT-NEXT: .LBB18_16:
; SOFT-NEXT: ldr r2, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #28 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: bne .LBB18_11
; SOFT-NEXT: b .LBB18_12
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: .LCPI18_0: ; SOFT-NEXT: .LCPI18_0:
; SOFT-NEXT: .long 1177550847 @ 0x462fffff ; SOFT-NEXT: .long 1177550847 @ 0x462fffff
; ;
; VFP2-LABEL: test_signed_i100_f64: ; VFP2-LABEL: test_signed_i100_f64:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 1177550847
ret i100 %x ret i100 %x
} }
define i128 @test_signed_i128_f64(double %f) nounwind { define i128 @test_signed_i128_f64(double %f) nounwind {
; SOFT-LABEL: test_signed_i128_f64: ; SOFT-LABEL: test_signed_i128_f64:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #28 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #28 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mvns r2, r6 ; SOFT-NEXT: mvns r4, r6
; SOFT-NEXT: ldr r3, .LCPI19_0 ; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: str r2, [sp, #24] @ 4-byte Spill ; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: bl __aeabi_dcmpgt ; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r2, r6 ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge ; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __fixunsdfti ; SOFT-NEXT: bl __fixunsdfti
; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: str r2, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: str r3, [sp, #20] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB19_2 ; SOFT-NEXT: bne .LBB19_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r5, r6
; SOFT-NEXT: .LBB19_2: ; SOFT-NEXT: .LBB19_2:
; SOFT-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r1, #0 ; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: ldr r4, [sp, #24] @ 4-byte Reload ; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bne .LBB19_4 ; SOFT-NEXT: bne .LBB19_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB19_4: ; SOFT-NEXT: .LBB19_4:
; SOFT-NEXT: str r1, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_6 ; SOFT-NEXT: bne .LBB19_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: .LBB19_6: ; SOFT-NEXT: .LBB19_6:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r1, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r1, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r1, r4
; SOFT-NEXT: bne .LBB19_8 ; SOFT-NEXT: bne .LBB19_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: .LBB19_8: ; SOFT-NEXT: .LBB19_8:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_10 ; SOFT-NEXT: bne .LBB19_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: .LBB19_10: ; SOFT-NEXT: .LBB19_10:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r5, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r5, r4
; SOFT-NEXT: bne .LBB19_12 ; SOFT-NEXT: bne .LBB19_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: mov r5, r2
; SOFT-NEXT: .LBB19_12: ; SOFT-NEXT: .LBB19_12:
; SOFT-NEXT: str r0, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r4
; SOFT-NEXT: ldr r3, .LCPI19_0
; SOFT-NEXT: bl __aeabi_dcmpgt
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: mov r2, r6
; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bl __aeabi_dcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB19_14 ; SOFT-NEXT: bne .LBB19_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: @ %bb.13:
; SOFT-NEXT: str r0, [sp, #20] @ 4-byte Spill ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: .LBB19_14: ; SOFT-NEXT: .LBB19_14:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: ldr r2, [sp] @ 4-byte Reload
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: bne .LBB19_16 ; SOFT-NEXT: bne .LBB19_16
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r4, [sp, #20] @ 4-byte Reload ; SOFT-NEXT: mov r4, r3
; SOFT-NEXT: .LBB19_16: ; SOFT-NEXT: .LBB19_16:
; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: mov r3, r4 ; SOFT-NEXT: mov r3, r4
; SOFT-NEXT: add sp, #28 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: .LCPI19_0: ; SOFT-NEXT: .LCPI19_0:
; SOFT-NEXT: .long 1206910975 @ 0x47efffff ; SOFT-NEXT: .long 1206910975 @ 0x47efffff
; ;
; VFP2-LABEL: test_signed_i128_f64: ; VFP2-LABEL: test_signed_i128_f64:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
▲ Show 20 Lines • Show All 575 Lines • ▼ Show 20 Lines
; SOFT-LABEL: test_signed_i50_f16: ; SOFT-LABEL: test_signed_i50_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #4 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #4 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI26_0 ; SOFT-NEXT: ldr r1, .LCPI26_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2ulz ; SOFT-NEXT: bl __aeabi_f2ulz
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB26_2 ; SOFT-NEXT: beq .LBB26_5
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB26_6
; SOFT-NEXT: .LBB26_2: ; SOFT-NEXT: .LBB26_2:
; SOFT-NEXT: mov r5, r1 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB26_7
; SOFT-NEXT: .LBB26_3:
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB26_4 ; SOFT-NEXT: bne .LBB26_8
; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mvns r0, r7
; SOFT-NEXT: .LBB26_4: ; SOFT-NEXT: .LBB26_4:
; SOFT-NEXT: str r0, [sp] @ 4-byte Spill ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: ldr r1, .LCPI26_0 ; SOFT-NEXT: .LBB26_5:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: beq .LBB26_2
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB26_6
; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: .LBB26_6: ; SOFT-NEXT: .LBB26_6:
; SOFT-NEXT: mvns r0, r6
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB26_3
; SOFT-NEXT: .LBB26_7:
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB26_8 ; SOFT-NEXT: beq .LBB26_4
; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r5, .LCPI26_1
; SOFT-NEXT: .LBB26_8: ; SOFT-NEXT: .LBB26_8:
; SOFT-NEXT: ldr r0, [sp] @ 4-byte Reload ; SOFT-NEXT: ldr r1, .LCPI26_1
; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: add sp, #4 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: .LCPI26_0: ; SOFT-NEXT: .LCPI26_0:
; SOFT-NEXT: .long 1484783615 @ 0x587fffff ; SOFT-NEXT: .long 1484783615 @ 0x587fffff
; SOFT-NEXT: .LCPI26_1: ; SOFT-NEXT: .LCPI26_1:
; SOFT-NEXT: .long 262143 @ 0x3ffff ; SOFT-NEXT: .long 262143 @ 0x3ffff
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 0x587fffff @ float 1.12589984E+15
ret i50 %x ret i50 %x
} }
define i64 @test_signed_i64_f16(half %f) nounwind { define i64 @test_signed_i64_f16(half %f) nounwind {
; SOFT-LABEL: test_signed_i64_f16: ; SOFT-LABEL: test_signed_i64_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #12 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #12 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI27_0 ; SOFT-NEXT: ldr r1, .LCPI27_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __aeabi_f2ulz ; SOFT-NEXT: bl __aeabi_f2ulz
; SOFT-NEXT: str r1, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB27_2 ; SOFT-NEXT: bne .LBB27_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: .LBB27_2: ; SOFT-NEXT: .LBB27_2:
; SOFT-NEXT: mvns r5, r7 ; SOFT-NEXT: mvns r2, r6
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: bne .LBB27_4 ; SOFT-NEXT: beq .LBB27_7
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB27_8
; SOFT-NEXT: .LBB27_4: ; SOFT-NEXT: .LBB27_4:
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI27_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB27_6 ; SOFT-NEXT: bne .LBB27_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: .LBB27_5:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r2, r1
; SOFT-NEXT: .LBB27_6: ; SOFT-NEXT: .LBB27_6:
; SOFT-NEXT: cmp r6, #0 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: bne .LBB27_8 ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: .LBB27_7:
; SOFT-NEXT: ldr r5, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: mov r0, r3
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB27_4
; SOFT-NEXT: .LBB27_8: ; SOFT-NEXT: .LBB27_8:
; SOFT-NEXT: mov r1, r5 ; SOFT-NEXT: mov r1, r5
; SOFT-NEXT: add sp, #12 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: beq .LBB27_5
; SOFT-NEXT: b .LBB27_6
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: .LCPI27_0: ; SOFT-NEXT: .LCPI27_0:
; SOFT-NEXT: .long 1602224127 @ 0x5f7fffff ; SOFT-NEXT: .long 1602224127 @ 0x5f7fffff
; ;
; VFP2-LABEL: test_signed_i64_f16: ; VFP2-LABEL: test_signed_i64_f16:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 0x5f7fffff @ float 1.8446743E+19
ret i64 %x ret i64 %x
} }
define i100 @test_signed_i100_f16(half %f) nounwind { define i100 @test_signed_i100_f16(half %f) nounwind {
; SOFT-LABEL: test_signed_i100_f16: ; SOFT-LABEL: test_signed_i100_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI28_0 ; SOFT-NEXT: ldr r1, .LCPI28_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r6, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r7, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __fixunssfti ; SOFT-NEXT: bl __fixunssfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r2, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r7, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB28_2 ; SOFT-NEXT: bne .LBB28_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB28_2: ; SOFT-NEXT: .LBB28_2:
; SOFT-NEXT: str r3, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: mvns r2, r6
; SOFT-NEXT: mvns r7, r6
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r6, r2
; SOFT-NEXT: bne .LBB28_4 ; SOFT-NEXT: bne .LBB28_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: mov r6, r0
; SOFT-NEXT: .LBB28_4: ; SOFT-NEXT: .LBB28_4:
; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: ldr r1, .LCPI28_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB28_6 ; SOFT-NEXT: bne .LBB28_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r5
; SOFT-NEXT: .LBB28_6: ; SOFT-NEXT: .LBB28_6:
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r7 ; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: bne .LBB28_8 ; SOFT-NEXT: beq .LBB28_13
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB28_14
; SOFT-NEXT: .LBB28_8: ; SOFT-NEXT: .LBB28_8:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: beq .LBB28_15
; SOFT-NEXT: ldr r1, .LCPI28_0 ; SOFT-NEXT: .LBB28_9:
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: beq .LBB28_16
; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB28_10
; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
; SOFT-NEXT: .LBB28_10: ; SOFT-NEXT: .LBB28_10:
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: bne .LBB28_12 ; SOFT-NEXT: beq .LBB28_12
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: .LBB28_11:
; SOFT-NEXT: ldr r7, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: movs r3, #15
; SOFT-NEXT: .LBB28_12: ; SOFT-NEXT: .LBB28_12:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r0, r6
; SOFT-NEXT: ldr r1, .LCPI28_0 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: .LBB28_13:
; SOFT-NEXT: mov r0, r5 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bne .LBB28_8
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: bne .LBB28_14
; SOFT-NEXT: @ %bb.13:
; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: .LBB28_14: ; SOFT-NEXT: .LBB28_14:
; SOFT-NEXT: str r5, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r4, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: bne .LBB28_9
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload ; SOFT-NEXT: .LBB28_15:
; SOFT-NEXT: beq .LBB28_16 ; SOFT-NEXT: ldr r2, [sp] @ 4-byte Reload
; SOFT-NEXT: @ %bb.15: ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: movs r3, #15 ; SOFT-NEXT: bne .LBB28_10
; SOFT-NEXT: .LBB28_16: ; SOFT-NEXT: .LBB28_16:
; SOFT-NEXT: mov r2, r7 ; SOFT-NEXT: mov r3, r5
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: bne .LBB28_11
; SOFT-NEXT: b .LBB28_12
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: .LCPI28_0: ; SOFT-NEXT: .LCPI28_0:
; SOFT-NEXT: .long 1904214015 @ 0x717fffff ; SOFT-NEXT: .long 1904214015 @ 0x717fffff
; ;
; VFP2-LABEL: test_signed_i100_f16: ; VFP2-LABEL: test_signed_i100_f16:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines; FP16-NEXT: .long 0x717fffff @ float 1.26765052E+30
ret i100 %x ret i100 %x
} }
define i128 @test_signed_i128_f16(half %f) nounwind { define i128 @test_signed_i128_f16(half %f) nounwind {
; SOFT-LABEL: test_signed_i128_f16: ; SOFT-LABEL: test_signed_i128_f16:
; SOFT: @ %bb.0: ; SOFT: @ %bb.0:
; SOFT-NEXT: .save {r4, r5, r6, r7, lr} ; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
; SOFT-NEXT: push {r4, r5, r6, r7, lr} ; SOFT-NEXT: push {r4, r5, r6, r7, lr}
; SOFT-NEXT: .pad #20 ; SOFT-NEXT: .pad #4
; SOFT-NEXT: sub sp, #20 ; SOFT-NEXT: sub sp, #4
; SOFT-NEXT: uxth r0, r0 ; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f ; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: mov r4, r0 ; SOFT-NEXT: mov r7, r0
; SOFT-NEXT: ldr r1, .LCPI29_0 ; SOFT-NEXT: ldr r1, .LCPI29_0
; SOFT-NEXT: bl __aeabi_fcmpgt ; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0 ; SOFT-NEXT: mov r4, r0
; SOFT-NEXT: movs r7, #0 ; SOFT-NEXT: movs r6, #0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: mov r6, r0 ; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4 ; SOFT-NEXT: mov r0, r7
; SOFT-NEXT: bl __fixunssfti ; SOFT-NEXT: bl __fixunssfti
; SOFT-NEXT: str r1, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r1
; SOFT-NEXT: str r2, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: str r3, [sp] @ 4-byte Spill
; SOFT-NEXT: str r3, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: cmp r6, #0
; SOFT-NEXT: bne .LBB29_2 ; SOFT-NEXT: bne .LBB29_2
; SOFT-NEXT: @ %bb.1: ; SOFT-NEXT: @ %bb.1:
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r0, r5
; SOFT-NEXT: .LBB29_2: ; SOFT-NEXT: .LBB29_2:
; SOFT-NEXT: mvns r6, r7 ; SOFT-NEXT: mvns r6, r6
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r1, r6 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: bne .LBB29_4 ; SOFT-NEXT: bne .LBB29_4
; SOFT-NEXT: @ %bb.3: ; SOFT-NEXT: @ %bb.3:
; SOFT-NEXT: mov r1, r0 ; SOFT-NEXT: mov r3, r0
; SOFT-NEXT: .LBB29_4: ; SOFT-NEXT: .LBB29_4:
; SOFT-NEXT: str r1, [sp, #12] @ 4-byte Spill ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI29_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB29_6 ; SOFT-NEXT: bne .LBB29_6
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill ; SOFT-NEXT: mov r7, r5
; SOFT-NEXT: .LBB29_6: ; SOFT-NEXT: .LBB29_6:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r1, r6
; SOFT-NEXT: bne .LBB29_8 ; SOFT-NEXT: bne .LBB29_8
; SOFT-NEXT: @ %bb.7: ; SOFT-NEXT: @ %bb.7:
; SOFT-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: .LBB29_8:
; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI29_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7 ; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge ; SOFT-NEXT: .LBB29_8:
; SOFT-NEXT: cmp r0, #0 ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB29_10 ; SOFT-NEXT: bne .LBB29_10
; SOFT-NEXT: @ %bb.9: ; SOFT-NEXT: @ %bb.9:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: mov r2, r5
; SOFT-NEXT: .LBB29_10: ; SOFT-NEXT: .LBB29_10:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r6 ; SOFT-NEXT: mov r7, r6
; SOFT-NEXT: bne .LBB29_12 ; SOFT-NEXT: beq .LBB29_15
; SOFT-NEXT: @ %bb.11: ; SOFT-NEXT: @ %bb.11:
; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: beq .LBB29_16
; SOFT-NEXT: .LBB29_12: ; SOFT-NEXT: .LBB29_12:
; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill ; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: ldr r1, .LCPI29_0
; SOFT-NEXT: bl __aeabi_fcmpgt
; SOFT-NEXT: mov r5, r0
; SOFT-NEXT: mov r0, r4
; SOFT-NEXT: mov r1, r7
; SOFT-NEXT: bl __aeabi_fcmpge
; SOFT-NEXT: cmp r0, #0
; SOFT-NEXT: bne .LBB29_14 ; SOFT-NEXT: bne .LBB29_14
; SOFT-NEXT: @ %bb.13: ; SOFT-NEXT: .LBB29_13:
; SOFT-NEXT: str r0, [sp, #16] @ 4-byte Spill ; SOFT-NEXT: ldr r6, [sp] @ 4-byte Reload
; SOFT-NEXT: .LBB29_14: ; SOFT-NEXT: .LBB29_14:
; SOFT-NEXT: cmp r5, #0 ; SOFT-NEXT: mov r0, r3
; SOFT-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; SOFT-NEXT: mov r2, r7
; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; SOFT-NEXT: bne .LBB29_16
; SOFT-NEXT: @ %bb.15:
; SOFT-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: .LBB29_16:
; SOFT-NEXT: mov r3, r6 ; SOFT-NEXT: mov r3, r6
; SOFT-NEXT: add sp, #20 ; SOFT-NEXT: add sp, #4
; SOFT-NEXT: pop {r4, r5, r6, r7, pc} ; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
; SOFT-NEXT: .LBB29_15:
; SOFT-NEXT: mov r7, r2
; SOFT-NEXT: cmp r5, #0
; SOFT-NEXT: bne .LBB29_12
; SOFT-NEXT: .LBB29_16:
; SOFT-NEXT: str r5, [sp] @ 4-byte Spill
; SOFT-NEXT: cmp r4, #0
; SOFT-NEXT: beq .LBB29_13
; SOFT-NEXT: b .LBB29_14
; SOFT-NEXT: .p2align 2 ; SOFT-NEXT: .p2align 2
; SOFT-NEXT: @ %bb.17: ; SOFT-NEXT: @ %bb.17:
; SOFT-NEXT: .LCPI29_0: ; SOFT-NEXT: .LCPI29_0:
; SOFT-NEXT: .long 2139095039 @ 0x7f7fffff ; SOFT-NEXT: .long 2139095039 @ 0x7f7fffff
; ;
; VFP2-LABEL: test_signed_i128_f16: ; VFP2-LABEL: test_signed_i128_f16:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
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llvm/test/CodeGen/RISCV/double-convert.ll

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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lui a3, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: bnez s0, .LBB12_2 ; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: beqz s0, .LBB12_2
; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: # %bb.1: # %start
; RV32IFD-NEXT: lui a1, 524288 ; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB12_2: # %start ; RV32IFD-NEXT: .LBB12_2: # %start
; RV32IFD-NEXT: lui a2, %hi(.LCPI12_1) ; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a2) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1)
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
; RV32IFD-NEXT: beqz a2, .LBB12_4 ; RV32IFD-NEXT: beqz a3, .LBB12_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a2, a4, -1
; RV32IFD-NEXT: .LBB12_4: # %start ; RV32IFD-NEXT: .LBB12_4: # %start
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: seqz a3, a3 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a4, a1, -1
; RV32IFD-NEXT: and a1, a4, a2
; RV32IFD-NEXT: neg a2, a3
; RV32IFD-NEXT: xori a3, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1 ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_l_d_sat: ; RV64IFD-LABEL: fcvt_l_d_sat:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
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; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui s2, 278016 ; RV32I-NEXT: lui a3, 278016
; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi@plt ; RV32I-NEXT: call __fixdfdi@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: bgez s6, .LBB12_2 ; RV32I-NEXT: bgez s3, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s5, 524288 ; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: .LBB12_2: # %start ; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: blez s4, .LBB12_4 ; RV32I-NEXT: blez s2, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: addi s5, a0, -1 ; RV32I-NEXT: addi s5, a0, -1
; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and s4, a0, s5 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: slti a2, s3, 0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: sgtz a3, s2
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and s3, a0, s3
; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: or s2, a0, s3
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_l_d_sat: ; RV64I-LABEL: fcvt_l_d_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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} }
define i64 @fcvt_lu_d_sat(double %a) nounwind { define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_lu_d_sat: ; RV32IFD-LABEL: fcvt_lu_d_sat:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0
; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fcvt.d.w fa5, zero
; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi s1, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IFD-NEXT: and a0, s1, a0
; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2) ; RV32IFD-NEXT: or a0, s0, a0
; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: and a1, s1, a1
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: or a1, s0, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a1, s0, a1
; RV32IFD-NEXT: or a1, a2, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_lu_d_sat: ; RV64IFD-LABEL: fcvt_lu_d_sat:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1 ; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_lu_d_sat: ; RV32I-LABEL: fcvt_lu_d_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui s2, 278272 ; RV32I-NEXT: lui a3, 278272
; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg s4, a0 ; RV32I-NEXT: neg s2, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi s5, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixunsdfdi@plt ; RV32I-NEXT: call __fixunsdfdi@plt
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: and a0, s3, a0
; RV32I-NEXT: and a0, s5, a0 ; RV32I-NEXT: or a0, s2, a0
; RV32I-NEXT: or s4, s4, a0 ; RV32I-NEXT: and a1, s3, a1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: or a1, s2, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg s2, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: or a1, s2, a0
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_lu_d_sat: ; RV64I-LABEL: fcvt_lu_d_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0) ; RV32IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
; RV32IFD-NEXT: fmax.d fa5, fa0, fa5 ; RV32IFD-NEXT: fmax.d fa5, fa0, fa5
; RV32IFD-NEXT: fmin.d fa5, fa5, fa4 ; RV32IFD-NEXT: fmin.d fa5, fa5, fa4
; RV32IFD-NEXT: fcvt.w.d a0, fa5, rtz ; RV32IFD-NEXT: fcvt.w.d a0, fa5, rtz
; RV32IFD-NEXT: feq.d a1, fa0, fa0 ; RV32IFD-NEXT: feq.d a1, fa0, fa0
; RV32IFD-NEXT: seqz a1, a1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a1, a1, -1 ; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_w_s_sat_i16: ; RV64IFD-LABEL: fcvt_w_s_sat_i16:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV64IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0) ; RV64IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV64IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0) ; RV64IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5 ; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
; RV64IFD-NEXT: fmin.d fa5, fa5, fa4 ; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
; RV64IFD-NEXT: fcvt.l.d a0, fa5, rtz ; RV64IFD-NEXT: fcvt.l.d a0, fa5, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: addi a1, a1, -1 ; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0) ; RV32IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
; RV32IFD-NEXT: fmax.d fa5, fa0, fa5 ; RV32IFD-NEXT: fmax.d fa5, fa0, fa5
; RV32IFD-NEXT: fmin.d fa5, fa5, fa4 ; RV32IFD-NEXT: fmin.d fa5, fa5, fa4
; RV32IFD-NEXT: fcvt.w.d a0, fa5, rtz ; RV32IFD-NEXT: fcvt.w.d a0, fa5, rtz
; RV32IFD-NEXT: feq.d a1, fa0, fa0 ; RV32IFD-NEXT: feq.d a1, fa0, fa0
; RV32IFD-NEXT: seqz a1, a1 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a1, a1, -1 ; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_w_s_sat_i8: ; RV64IFD-LABEL: fcvt_w_s_sat_i8:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV64IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0) ; RV64IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV64IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0) ; RV64IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5 ; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
; RV64IFD-NEXT: fmin.d fa5, fa5, fa4 ; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
; RV64IFD-NEXT: fcvt.l.d a0, fa5, rtz ; RV64IFD-NEXT: fcvt.l.d a0, fa5, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1 ; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: addi a1, a1, -1 ; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

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; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call floor@plt ; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lui a3, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: bnez s0, .LBB1_2 ; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: beqz s0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a1, 524288 ; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB1_2: ; RV32IFD-NEXT: .LBB1_2:
; RV32IFD-NEXT: lui a2, %hi(.LCPI1_1) ; RV32IFD-NEXT: lui a1, %hi(.LCPI1_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_1)(a2) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_1)(a1)
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
; RV32IFD-NEXT: beqz a2, .LBB1_4 ; RV32IFD-NEXT: beqz a3, .LBB1_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a2, a4, -1
; RV32IFD-NEXT: .LBB1_4: ; RV32IFD-NEXT: .LBB1_4:
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: seqz a3, a3 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a4, a1, -1
; RV32IFD-NEXT: and a1, a4, a2
; RV32IFD-NEXT: neg a2, a3
; RV32IFD-NEXT: xori a3, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1 ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: test_floor_si64: ; RV64IFD-LABEL: test_floor_si64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
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; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call floor@plt ; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI3_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI3_0)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: flt.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: neg s0, a0
; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fcvt.d.w fa5, zero
; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
; RV32IFD-NEXT: neg s1, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi s1, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: and a0, s1, a0
; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: or a0, s0, a0
; RV32IFD-NEXT: and a1, s1, a1 ; RV32IFD-NEXT: and a1, s1, a1
; RV32IFD-NEXT: or a1, s0, a1 ; RV32IFD-NEXT: or a1, s0, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call ceil@plt ; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lui a3, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: bnez s0, .LBB5_2 ; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: beqz s0, .LBB5_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a1, 524288 ; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB5_2: ; RV32IFD-NEXT: .LBB5_2:
; RV32IFD-NEXT: lui a2, %hi(.LCPI5_1) ; RV32IFD-NEXT: lui a1, %hi(.LCPI5_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_1)(a2) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_1)(a1)
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
; RV32IFD-NEXT: beqz a2, .LBB5_4 ; RV32IFD-NEXT: beqz a3, .LBB5_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a2, a4, -1
; RV32IFD-NEXT: .LBB5_4: ; RV32IFD-NEXT: .LBB5_4:
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: seqz a3, a3 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a4, a1, -1
; RV32IFD-NEXT: and a1, a4, a2
; RV32IFD-NEXT: neg a2, a3
; RV32IFD-NEXT: xori a3, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1 ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: test_ceil_si64: ; RV64IFD-LABEL: test_ceil_si64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
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; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call ceil@plt ; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI7_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI7_0)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: flt.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: neg s0, a0
; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fcvt.d.w fa5, zero
; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
; RV32IFD-NEXT: neg s1, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi s1, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: and a0, s1, a0
; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: or a0, s0, a0
; RV32IFD-NEXT: and a1, s1, a1 ; RV32IFD-NEXT: and a1, s1, a1
; RV32IFD-NEXT: or a1, s0, a1 ; RV32IFD-NEXT: or a1, s0, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call trunc@plt ; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lui a3, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: bnez s0, .LBB9_2 ; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: beqz s0, .LBB9_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a1, 524288 ; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB9_2: ; RV32IFD-NEXT: .LBB9_2:
; RV32IFD-NEXT: lui a2, %hi(.LCPI9_1) ; RV32IFD-NEXT: lui a1, %hi(.LCPI9_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_1)(a2) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_1)(a1)
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
; RV32IFD-NEXT: beqz a2, .LBB9_4 ; RV32IFD-NEXT: beqz a3, .LBB9_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a2, a4, -1
; RV32IFD-NEXT: .LBB9_4: ; RV32IFD-NEXT: .LBB9_4:
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: seqz a3, a3 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a4, a1, -1
; RV32IFD-NEXT: and a1, a4, a2
; RV32IFD-NEXT: neg a2, a3
; RV32IFD-NEXT: xori a3, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1 ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: test_trunc_si64: ; RV64IFD-LABEL: test_trunc_si64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
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; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call trunc@plt ; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI11_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: flt.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: neg s0, a0
; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fcvt.d.w fa5, zero
; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
; RV32IFD-NEXT: neg s1, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi s1, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: and a0, s1, a0
; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: or a0, s0, a0
; RV32IFD-NEXT: and a1, s1, a1 ; RV32IFD-NEXT: and a1, s1, a1
; RV32IFD-NEXT: or a1, s0, a1 ; RV32IFD-NEXT: or a1, s0, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call round@plt ; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lui a3, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: bnez s0, .LBB13_2 ; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: beqz s0, .LBB13_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a1, 524288 ; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB13_2: ; RV32IFD-NEXT: .LBB13_2:
; RV32IFD-NEXT: lui a2, %hi(.LCPI13_1) ; RV32IFD-NEXT: lui a1, %hi(.LCPI13_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_1)(a2) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_1)(a1)
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
; RV32IFD-NEXT: beqz a2, .LBB13_4 ; RV32IFD-NEXT: beqz a3, .LBB13_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a2, a4, -1
; RV32IFD-NEXT: .LBB13_4: ; RV32IFD-NEXT: .LBB13_4:
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: seqz a3, a3 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a4, a1, -1
; RV32IFD-NEXT: and a1, a4, a2
; RV32IFD-NEXT: neg a2, a3
; RV32IFD-NEXT: xori a3, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1 ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: test_round_si64: ; RV64IFD-LABEL: test_round_si64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
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; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call round@plt ; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI15_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI15_0)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: flt.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: neg s0, a0
; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fcvt.d.w fa5, zero
; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
; RV32IFD-NEXT: neg s1, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi s1, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: and a0, s1, a0
; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: or a0, s0, a0
; RV32IFD-NEXT: and a1, s1, a1 ; RV32IFD-NEXT: and a1, s1, a1
; RV32IFD-NEXT: or a1, s0, a1 ; RV32IFD-NEXT: or a1, s0, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt ; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
; RV32IFD-NEXT: call __fixdfdi@plt ; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lui a3, 524288 ; RV32IFD-NEXT: lui a4, 524288
; RV32IFD-NEXT: bnez s0, .LBB17_2 ; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: beqz s0, .LBB17_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a1, 524288 ; RV32IFD-NEXT: mv a2, a1
; RV32IFD-NEXT: .LBB17_2: ; RV32IFD-NEXT: .LBB17_2:
; RV32IFD-NEXT: lui a2, %hi(.LCPI17_1) ; RV32IFD-NEXT: lui a1, %hi(.LCPI17_1)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_1)(a2) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_1)(a1)
; RV32IFD-NEXT: flt.d a2, fa5, fs0 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
; RV32IFD-NEXT: beqz a2, .LBB17_4 ; RV32IFD-NEXT: beqz a3, .LBB17_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a2, a4, -1
; RV32IFD-NEXT: .LBB17_4: ; RV32IFD-NEXT: .LBB17_4:
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
; RV32IFD-NEXT: seqz a3, a3 ; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: addi a4, a1, -1
; RV32IFD-NEXT: and a1, a4, a2
; RV32IFD-NEXT: neg a2, a3
; RV32IFD-NEXT: xori a3, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1 ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: neg a2, a2
; RV32IFD-NEXT: neg a4, s0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: test_roundeven_si64: ; RV64IFD-LABEL: test_roundeven_si64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
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; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt ; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IFD-NEXT: fld fa5, %lo(.LCPI19_0)(a0) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32IFD-NEXT: flt.d a0, fa5, fa0 ; RV32IFD-NEXT: flt.d a0, fa5, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: neg s0, a0
; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fcvt.d.w fa5, zero
; RV32IFD-NEXT: fle.d a0, fa5, fa0 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
; RV32IFD-NEXT: neg s1, a0 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi s1, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: and a0, s1, a0 ; RV32IFD-NEXT: and a0, s1, a0
; RV32IFD-NEXT: or a0, s0, a0 ; RV32IFD-NEXT: or a0, s0, a0
; RV32IFD-NEXT: and a1, s1, a1 ; RV32IFD-NEXT: and a1, s1, a1
; RV32IFD-NEXT: or a1, s0, a1 ; RV32IFD-NEXT: or a1, s0, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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llvm/test/CodeGen/RISCV/float-convert.ll

Show First 20 Lines • Show All 514 Lines • ▼ Show 20 Lines
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: lui a0, 913408
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fle.s s0, fa5, fa0 ; RV32IF-NEXT: fle.s s0, fa5, fa0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lui a3, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB12_2 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: beqz s0, .LBB12_2
; RV32IF-NEXT: # %bb.1: # %start ; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: lui a1, 524288 ; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB12_2: # %start ; RV32IF-NEXT: .LBB12_2: # %start
; RV32IF-NEXT: lui a2, %hi(.LCPI12_0) ; RV32IF-NEXT: lui a1, %hi(.LCPI12_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a2) ; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a1)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: beqz a2, .LBB12_4 ; RV32IF-NEXT: beqz a3, .LBB12_4
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: addi a1, a3, -1 ; RV32IF-NEXT: addi a2, a4, -1
; RV32IF-NEXT: .LBB12_4: # %start ; RV32IF-NEXT: .LBB12_4: # %start
; RV32IF-NEXT: feq.s a3, fs0, fs0 ; RV32IF-NEXT: feq.s a1, fs0, fs0
; RV32IF-NEXT: seqz a3, a3 ; RV32IF-NEXT: xori a1, a1, 1
craig.topperAuthorUnsubmitted
Done
ReplyInline Actions

The xori+addi here are equivalent to neg. I'll fix this in a follow up patch.

craig.topper: The xori+addi here are equivalent to neg. I'll fix this in a follow up patch.
; RV32IF-NEXT: addi a4, a1, -1
; RV32IF-NEXT: and a1, a4, a2
; RV32IF-NEXT: neg a2, a3
; RV32IF-NEXT: xori a3, s0, 1
; RV32IF-NEXT: addi a3, a3, -1 ; RV32IF-NEXT: addi a3, a3, -1
; RV32IF-NEXT: and a1, a3, a1
; RV32IF-NEXT: neg a2, a2
; RV32IF-NEXT: neg a4, s0
; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a0, a3, a0
; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_l_s_sat: ; RV64IF-LABEL: fcvt_l_s_sat:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
; RV64IF-NEXT: addi a1, a1, -1 ; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_l_s_sat: ; RV32I-LABEL: fcvt_l_s_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 913408 ; RV32I-NEXT: lui a1, 913408
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfdi@plt ; RV32I-NEXT: call __fixsfdi@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: bgez s2, .LBB12_2 ; RV32I-NEXT: bgez s1, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s3, 524288 ; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: .LBB12_2: # %start ; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: lui s2, 389120 ; RV32I-NEXT: lui a1, 389120
; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: blez a0, .LBB12_4 ; RV32I-NEXT: blez a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: addi s3, s4, -1 ; RV32I-NEXT: addi s3, s5, -1
; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt ; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and s3, a0, s3 ; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: lui a1, 913408 ; RV32I-NEXT: slti a2, s1, 0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: and a2, a2, s2
; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: sgtz a3, s4
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: and s1, a0, s1 ; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: or s1, a0, s1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_l_s_sat: ; RV64I-LABEL: fcvt_l_s_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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} }
define i64 @fcvt_lu_s_sat(float %a) nounwind { define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_lu_s_sat: ; RV32IF-LABEL: fcvt_lu_s_sat:
; RV32IF: # %bb.0: # %start ; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, %hi(.LCPI14_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a0)
; RV32IF-NEXT: flt.s a0, fa5, fa0
; RV32IF-NEXT: neg s0, a0
; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: fle.s a0, fa5, fa0 ; RV32IF-NEXT: fle.s a0, fa5, fa0
; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: addi s1, a0, -1
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IF-NEXT: and a0, s1, a0
; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) ; RV32IF-NEXT: or a0, s0, a0
; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: and a1, s1, a1
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: or a1, s0, a1
; RV32IF-NEXT: neg a2, a2
; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a1, s0, a1
; RV32IF-NEXT: or a1, a2, a1
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_lu_s_sat: ; RV64IF-LABEL: fcvt_lu_s_sat:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
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; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt ; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: and s3, s2, a0 ; RV32I-NEXT: and s3, s2, a0
; RV32I-NEXT: lui s2, 391168 ; RV32I-NEXT: lui a1, 391168
; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: or s3, a0, s3
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and s1, a0, s1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg a1, a0 ; RV32I-NEXT: neg a1, a0
; RV32I-NEXT: or a1, a1, s1 ; RV32I-NEXT: or a0, a1, s3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: and a2, s2, s1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
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; RV32IF-NEXT: lui a0, %hi(.LCPI24_0) ; RV32IF-NEXT: lui a0, %hi(.LCPI24_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI24_0)(a0) ; RV32IF-NEXT: flw fa5, %lo(.LCPI24_0)(a0)
; RV32IF-NEXT: lui a0, 815104 ; RV32IF-NEXT: lui a0, 815104
; RV32IF-NEXT: fmv.w.x fa4, a0 ; RV32IF-NEXT: fmv.w.x fa4, a0
; RV32IF-NEXT: fmax.s fa4, fa0, fa4 ; RV32IF-NEXT: fmax.s fa4, fa0, fa4
; RV32IF-NEXT: fmin.s fa5, fa4, fa5 ; RV32IF-NEXT: fmin.s fa5, fa4, fa5
; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IF-NEXT: feq.s a1, fa0, fa0 ; RV32IF-NEXT: feq.s a1, fa0, fa0
; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: addi a1, a1, -1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_w_s_sat_i16: ; RV64IF-LABEL: fcvt_w_s_sat_i16:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: lui a0, %hi(.LCPI24_0) ; RV64IF-NEXT: lui a0, %hi(.LCPI24_0)
; RV64IF-NEXT: flw fa5, %lo(.LCPI24_0)(a0) ; RV64IF-NEXT: flw fa5, %lo(.LCPI24_0)(a0)
; RV64IF-NEXT: lui a0, 815104 ; RV64IF-NEXT: lui a0, 815104
; RV64IF-NEXT: fmv.w.x fa4, a0 ; RV64IF-NEXT: fmv.w.x fa4, a0
; RV64IF-NEXT: fmax.s fa4, fa0, fa4 ; RV64IF-NEXT: fmax.s fa4, fa0, fa4
; RV64IF-NEXT: fmin.s fa5, fa4, fa5 ; RV64IF-NEXT: fmin.s fa5, fa4, fa5
; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: addi a1, a1, -1 ; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: lui a0, 798720 ; RV32IF-NEXT: lui a0, 798720
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fmax.s fa5, fa0, fa5 ; RV32IF-NEXT: fmax.s fa5, fa0, fa5
; RV32IF-NEXT: lui a0, 274400 ; RV32IF-NEXT: lui a0, 274400
; RV32IF-NEXT: fmv.w.x fa4, a0 ; RV32IF-NEXT: fmv.w.x fa4, a0
; RV32IF-NEXT: fmin.s fa5, fa5, fa4 ; RV32IF-NEXT: fmin.s fa5, fa5, fa4
; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz ; RV32IF-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IF-NEXT: feq.s a1, fa0, fa0 ; RV32IF-NEXT: feq.s a1, fa0, fa0
; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: addi a1, a1, -1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcvt_w_s_sat_i8: ; RV64IF-LABEL: fcvt_w_s_sat_i8:
; RV64IF: # %bb.0: # %start ; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: lui a0, 798720 ; RV64IF-NEXT: lui a0, 798720
; RV64IF-NEXT: fmv.w.x fa5, a0 ; RV64IF-NEXT: fmv.w.x fa5, a0
; RV64IF-NEXT: fmax.s fa5, fa0, fa5 ; RV64IF-NEXT: fmax.s fa5, fa0, fa5
; RV64IF-NEXT: lui a0, 274400 ; RV64IF-NEXT: lui a0, 274400
; RV64IF-NEXT: fmv.w.x fa4, a0 ; RV64IF-NEXT: fmv.w.x fa4, a0
; RV64IF-NEXT: fmin.s fa5, fa5, fa4 ; RV64IF-NEXT: fmin.s fa5, fa5, fa4
; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz ; RV64IF-NEXT: fcvt.l.s a0, fa5, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: addi a1, a1, -1 ; RV64IF-NEXT: addi a1, a1, -1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

Show All 35 Lines
; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn ; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB1_2: ; RV32IF-NEXT: .LBB1_2:
; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: lui a0, 913408
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fle.s s0, fa5, fs0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lui a3, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB1_4 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: beqz s0, .LBB1_4
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: lui a1, 524288 ; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB1_4: ; RV32IF-NEXT: .LBB1_4:
; RV32IF-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IF-NEXT: lui a1, %hi(.LCPI1_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a2) ; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a1)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: beqz a2, .LBB1_6 ; RV32IF-NEXT: beqz a3, .LBB1_6
; RV32IF-NEXT: # %bb.5: ; RV32IF-NEXT: # %bb.5:
; RV32IF-NEXT: addi a1, a3, -1 ; RV32IF-NEXT: addi a2, a4, -1
; RV32IF-NEXT: .LBB1_6: ; RV32IF-NEXT: .LBB1_6:
; RV32IF-NEXT: feq.s a3, fs0, fs0 ; RV32IF-NEXT: feq.s a1, fs0, fs0
; RV32IF-NEXT: seqz a3, a3 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a3, a3, -1 ; RV32IF-NEXT: addi a4, a1, -1
; RV32IF-NEXT: and a1, a3, a1 ; RV32IF-NEXT: and a1, a4, a2
; RV32IF-NEXT: neg a4, s0 ; RV32IF-NEXT: xori a2, s0, 1
; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: neg a2, a3
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_floor_si64: ; RV64IF-LABEL: test_floor_si64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
Show All 22 Lines; CHECKIF-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_floor_ui64(float %x) nounwind { define i64 @test_floor_ui64(float %x) nounwind {
; RV32IF-LABEL: test_floor_ui64: ; RV32IF-LABEL: test_floor_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: lui a0, 307200
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0 ; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5 ; RV32IF-NEXT: flt.s a0, fa4, fa5
; RV32IF-NEXT: beqz a0, .LBB3_2 ; RV32IF-NEXT: beqz a0, .LBB3_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fs0, rdn ; RV32IF-NEXT: fcvt.w.s a0, fs0, rdn
; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn ; RV32IF-NEXT: fcvt.s.w fa5, a0, rdn
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB3_2: ; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: fle.s a0, fa5, fs0
; RV32IF-NEXT: neg s0, a0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: flw fa5, %lo(.LCPI3_0)(a2) ; RV32IF-NEXT: fle.s a2, fa5, fs0
; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: lui a3, %hi(.LCPI3_0)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flw fa5, %lo(.LCPI3_0)(a3)
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: xori a2, a2, 1
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: and a1, s0, a1 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: neg a3, a3
; RV32IF-NEXT: or a0, a3, a0
; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: or a1, a3, a1
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_floor_ui64: ; RV64IF-LABEL: test_floor_ui64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
Show All 37 Lines
; RV32IF-NEXT: fcvt.s.w fa5, a0, rup ; RV32IF-NEXT: fcvt.s.w fa5, a0, rup
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB5_2: ; RV32IF-NEXT: .LBB5_2:
; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: lui a0, 913408
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fle.s s0, fa5, fs0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lui a3, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB5_4 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: beqz s0, .LBB5_4
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: lui a1, 524288 ; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB5_4: ; RV32IF-NEXT: .LBB5_4:
; RV32IF-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IF-NEXT: lui a1, %hi(.LCPI5_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a2) ; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a1)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: beqz a2, .LBB5_6 ; RV32IF-NEXT: beqz a3, .LBB5_6
; RV32IF-NEXT: # %bb.5: ; RV32IF-NEXT: # %bb.5:
; RV32IF-NEXT: addi a1, a3, -1 ; RV32IF-NEXT: addi a2, a4, -1
; RV32IF-NEXT: .LBB5_6: ; RV32IF-NEXT: .LBB5_6:
; RV32IF-NEXT: feq.s a3, fs0, fs0 ; RV32IF-NEXT: feq.s a1, fs0, fs0
; RV32IF-NEXT: seqz a3, a3 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a3, a3, -1 ; RV32IF-NEXT: addi a4, a1, -1
; RV32IF-NEXT: and a1, a3, a1 ; RV32IF-NEXT: and a1, a4, a2
; RV32IF-NEXT: neg a4, s0 ; RV32IF-NEXT: xori a2, s0, 1
; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: neg a2, a3
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_ceil_si64: ; RV64IF-LABEL: test_ceil_si64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
Show All 22 Lines; CHECKIF-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_ceil_ui64(float %x) nounwind { define i64 @test_ceil_ui64(float %x) nounwind {
; RV32IF-LABEL: test_ceil_ui64: ; RV32IF-LABEL: test_ceil_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: lui a0, 307200
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0 ; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5 ; RV32IF-NEXT: flt.s a0, fa4, fa5
; RV32IF-NEXT: beqz a0, .LBB7_2 ; RV32IF-NEXT: beqz a0, .LBB7_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fs0, rup ; RV32IF-NEXT: fcvt.w.s a0, fs0, rup
; RV32IF-NEXT: fcvt.s.w fa5, a0, rup ; RV32IF-NEXT: fcvt.s.w fa5, a0, rup
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB7_2: ; RV32IF-NEXT: .LBB7_2:
; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: fle.s a0, fa5, fs0
; RV32IF-NEXT: neg s0, a0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: flw fa5, %lo(.LCPI7_0)(a2) ; RV32IF-NEXT: fle.s a2, fa5, fs0
; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: lui a3, %hi(.LCPI7_0)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flw fa5, %lo(.LCPI7_0)(a3)
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: xori a2, a2, 1
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: and a1, s0, a1 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: neg a3, a3
; RV32IF-NEXT: or a0, a3, a0
; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: or a1, a3, a1
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_ceil_ui64: ; RV64IF-LABEL: test_ceil_ui64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
Show All 37 Lines
; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz ; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB9_2: ; RV32IF-NEXT: .LBB9_2:
; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: lui a0, 913408
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fle.s s0, fa5, fs0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lui a3, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB9_4 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: beqz s0, .LBB9_4
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: lui a1, 524288 ; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB9_4: ; RV32IF-NEXT: .LBB9_4:
; RV32IF-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IF-NEXT: lui a1, %hi(.LCPI9_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a2) ; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a1)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: beqz a2, .LBB9_6 ; RV32IF-NEXT: beqz a3, .LBB9_6
; RV32IF-NEXT: # %bb.5: ; RV32IF-NEXT: # %bb.5:
; RV32IF-NEXT: addi a1, a3, -1 ; RV32IF-NEXT: addi a2, a4, -1
; RV32IF-NEXT: .LBB9_6: ; RV32IF-NEXT: .LBB9_6:
; RV32IF-NEXT: feq.s a3, fs0, fs0 ; RV32IF-NEXT: feq.s a1, fs0, fs0
; RV32IF-NEXT: seqz a3, a3 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a3, a3, -1 ; RV32IF-NEXT: addi a4, a1, -1
; RV32IF-NEXT: and a1, a3, a1 ; RV32IF-NEXT: and a1, a4, a2
; RV32IF-NEXT: neg a4, s0 ; RV32IF-NEXT: xori a2, s0, 1
; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: neg a2, a3
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_trunc_si64: ; RV64IF-LABEL: test_trunc_si64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
Show All 22 Lines; CHECKIF-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_trunc_ui64(float %x) nounwind { define i64 @test_trunc_ui64(float %x) nounwind {
; RV32IF-LABEL: test_trunc_ui64: ; RV32IF-LABEL: test_trunc_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: lui a0, 307200
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0 ; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5 ; RV32IF-NEXT: flt.s a0, fa4, fa5
; RV32IF-NEXT: beqz a0, .LBB11_2 ; RV32IF-NEXT: beqz a0, .LBB11_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fs0, rtz ; RV32IF-NEXT: fcvt.w.s a0, fs0, rtz
; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz ; RV32IF-NEXT: fcvt.s.w fa5, a0, rtz
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB11_2: ; RV32IF-NEXT: .LBB11_2:
; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: fle.s a0, fa5, fs0
; RV32IF-NEXT: neg s0, a0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: flw fa5, %lo(.LCPI11_0)(a2) ; RV32IF-NEXT: fle.s a2, fa5, fs0
; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: lui a3, %hi(.LCPI11_0)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flw fa5, %lo(.LCPI11_0)(a3)
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: xori a2, a2, 1
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: and a1, s0, a1 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: neg a3, a3
; RV32IF-NEXT: or a0, a3, a0
; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: or a1, a3, a1
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_trunc_ui64: ; RV64IF-LABEL: test_trunc_ui64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
Show All 37 Lines
; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm ; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB13_2: ; RV32IF-NEXT: .LBB13_2:
; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: lui a0, 913408
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fle.s s0, fa5, fs0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lui a3, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB13_4 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: beqz s0, .LBB13_4
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: lui a1, 524288 ; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB13_4: ; RV32IF-NEXT: .LBB13_4:
; RV32IF-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IF-NEXT: lui a1, %hi(.LCPI13_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a2) ; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a1)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: beqz a2, .LBB13_6 ; RV32IF-NEXT: beqz a3, .LBB13_6
; RV32IF-NEXT: # %bb.5: ; RV32IF-NEXT: # %bb.5:
; RV32IF-NEXT: addi a1, a3, -1 ; RV32IF-NEXT: addi a2, a4, -1
; RV32IF-NEXT: .LBB13_6: ; RV32IF-NEXT: .LBB13_6:
; RV32IF-NEXT: feq.s a3, fs0, fs0 ; RV32IF-NEXT: feq.s a1, fs0, fs0
; RV32IF-NEXT: seqz a3, a3 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a3, a3, -1 ; RV32IF-NEXT: addi a4, a1, -1
; RV32IF-NEXT: and a1, a3, a1 ; RV32IF-NEXT: and a1, a4, a2
; RV32IF-NEXT: neg a4, s0 ; RV32IF-NEXT: xori a2, s0, 1
; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: neg a2, a3
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_round_si64: ; RV64IF-LABEL: test_round_si64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
Show All 22 Lines; CHECKIF-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_round_ui64(float %x) nounwind { define i64 @test_round_ui64(float %x) nounwind {
; RV32IF-LABEL: test_round_ui64: ; RV32IF-LABEL: test_round_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: lui a0, 307200
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0 ; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5 ; RV32IF-NEXT: flt.s a0, fa4, fa5
; RV32IF-NEXT: beqz a0, .LBB15_2 ; RV32IF-NEXT: beqz a0, .LBB15_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fs0, rmm ; RV32IF-NEXT: fcvt.w.s a0, fs0, rmm
; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm ; RV32IF-NEXT: fcvt.s.w fa5, a0, rmm
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB15_2: ; RV32IF-NEXT: .LBB15_2:
; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: fle.s a0, fa5, fs0
; RV32IF-NEXT: neg s0, a0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: flw fa5, %lo(.LCPI15_0)(a2) ; RV32IF-NEXT: fle.s a2, fa5, fs0
; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: lui a3, %hi(.LCPI15_0)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flw fa5, %lo(.LCPI15_0)(a3)
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: xori a2, a2, 1
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: and a1, s0, a1 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: neg a3, a3
; RV32IF-NEXT: or a0, a3, a0
; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: or a1, a3, a1
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_round_ui64: ; RV64IF-LABEL: test_round_ui64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
Show All 37 Lines
; RV32IF-NEXT: fcvt.s.w fa5, a0, rne ; RV32IF-NEXT: fcvt.s.w fa5, a0, rne
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB17_2: ; RV32IF-NEXT: .LBB17_2:
; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: lui a0, 913408
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fle.s s0, fa5, fs0 ; RV32IF-NEXT: fle.s s0, fa5, fs0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixsfdi@plt ; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lui a3, 524288 ; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB17_4 ; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: beqz s0, .LBB17_4
; RV32IF-NEXT: # %bb.3: ; RV32IF-NEXT: # %bb.3:
; RV32IF-NEXT: lui a1, 524288 ; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB17_4: ; RV32IF-NEXT: .LBB17_4:
; RV32IF-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IF-NEXT: lui a1, %hi(.LCPI17_0)
; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a2) ; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a1)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: beqz a2, .LBB17_6 ; RV32IF-NEXT: beqz a3, .LBB17_6
; RV32IF-NEXT: # %bb.5: ; RV32IF-NEXT: # %bb.5:
; RV32IF-NEXT: addi a1, a3, -1 ; RV32IF-NEXT: addi a2, a4, -1
; RV32IF-NEXT: .LBB17_6: ; RV32IF-NEXT: .LBB17_6:
; RV32IF-NEXT: feq.s a3, fs0, fs0 ; RV32IF-NEXT: feq.s a1, fs0, fs0
; RV32IF-NEXT: seqz a3, a3 ; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: addi a3, a3, -1 ; RV32IF-NEXT: addi a4, a1, -1
; RV32IF-NEXT: and a1, a3, a1 ; RV32IF-NEXT: and a1, a4, a2
; RV32IF-NEXT: neg a4, s0 ; RV32IF-NEXT: xori a2, s0, 1
; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: neg a2, a3
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: or a0, a2, a0
; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a0, a4, a0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_roundeven_si64: ; RV64IF-LABEL: test_roundeven_si64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
Show All 22 Lines; CHECKIF-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_roundeven_ui64(float %x) nounwind { define i64 @test_roundeven_ui64(float %x) nounwind {
; RV32IF-LABEL: test_roundeven_ui64: ; RV32IF-LABEL: test_roundeven_ui64:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: lui a0, 307200
; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fmv.w.x fa5, a0
; RV32IF-NEXT: fabs.s fa4, fa0 ; RV32IF-NEXT: fabs.s fa4, fa0
; RV32IF-NEXT: flt.s a0, fa4, fa5 ; RV32IF-NEXT: flt.s a0, fa4, fa5
; RV32IF-NEXT: beqz a0, .LBB19_2 ; RV32IF-NEXT: beqz a0, .LBB19_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fs0, rne ; RV32IF-NEXT: fcvt.w.s a0, fs0, rne
; RV32IF-NEXT: fcvt.s.w fa5, a0, rne ; RV32IF-NEXT: fcvt.s.w fa5, a0, rne
; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0 ; RV32IF-NEXT: fsgnj.s fs0, fa5, fs0
; RV32IF-NEXT: .LBB19_2: ; RV32IF-NEXT: .LBB19_2:
; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: fle.s a0, fa5, fs0
; RV32IF-NEXT: neg s0, a0
; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: fmv.s fa0, fs0
; RV32IF-NEXT: call __fixunssfdi@plt ; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IF-NEXT: fmv.w.x fa5, zero
; RV32IF-NEXT: flw fa5, %lo(.LCPI19_0)(a2) ; RV32IF-NEXT: fle.s a2, fa5, fs0
; RV32IF-NEXT: and a0, s0, a0 ; RV32IF-NEXT: lui a3, %hi(.LCPI19_0)
; RV32IF-NEXT: flt.s a2, fa5, fs0 ; RV32IF-NEXT: flw fa5, %lo(.LCPI19_0)(a3)
; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: xori a2, a2, 1
; RV32IF-NEXT: or a0, a2, a0 ; RV32IF-NEXT: addi a2, a2, -1
; RV32IF-NEXT: and a1, s0, a1 ; RV32IF-NEXT: and a0, a2, a0
; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: flt.s a3, fa5, fs0
; RV32IF-NEXT: neg a3, a3
; RV32IF-NEXT: or a0, a3, a0
; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: or a1, a3, a1
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: test_roundeven_ui64: ; RV64IF-LABEL: test_roundeven_ui64:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne
; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: seqz a1, a1 ; RV64IF-NEXT: seqz a1, a1
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llvm/test/CodeGen/RISCV/half-convert.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0) ; RV32IZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: lui a0, 815104 ; RV32IZFH-NEXT: lui a0, 815104
; RV32IZFH-NEXT: fmv.w.x fa3, a0 ; RV32IZFH-NEXT: fmv.w.x fa3, a0
; RV32IZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV32IZFH-NEXT: fmax.s fa3, fa5, fa3
; RV32IZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV32IZFH-NEXT: fmin.s fa4, fa3, fa4
; RV32IZFH-NEXT: fcvt.w.s a0, fa4, rtz ; RV32IZFH-NEXT: fcvt.w.s a0, fa4, rtz
; RV32IZFH-NEXT: feq.s a1, fa5, fa5 ; RV32IZFH-NEXT: feq.s a1, fa5, fa5
; RV32IZFH-NEXT: seqz a1, a1 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a1, a1, -1 ; RV32IZFH-NEXT: addi a1, a1, -1
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_si_h_sat: ; RV64IZFH-LABEL: fcvt_si_h_sat:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0) ; RV64IZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; RV64IZFH-NEXT: lui a0, 815104 ; RV64IZFH-NEXT: lui a0, 815104
; RV64IZFH-NEXT: fmv.w.x fa3, a0 ; RV64IZFH-NEXT: fmv.w.x fa3, a0
; RV64IZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV64IZFH-NEXT: fmax.s fa3, fa5, fa3
; RV64IZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV64IZFH-NEXT: fmin.s fa4, fa3, fa4
; RV64IZFH-NEXT: fcvt.l.s a0, fa4, rtz ; RV64IZFH-NEXT: fcvt.l.s a0, fa4, rtz
; RV64IZFH-NEXT: feq.s a1, fa5, fa5 ; RV64IZFH-NEXT: feq.s a1, fa5, fa5
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: xori a1, a1, 1
; RV64IZFH-NEXT: addi a1, a1, -1 ; RV64IZFH-NEXT: addi a1, a1, -1
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_si_h_sat: ; RV32IDZFH-LABEL: fcvt_si_h_sat:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h fa5, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IDZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0) ; RV32IDZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; RV32IDZFH-NEXT: lui a0, 815104 ; RV32IDZFH-NEXT: lui a0, 815104
; RV32IDZFH-NEXT: fmv.w.x fa3, a0 ; RV32IDZFH-NEXT: fmv.w.x fa3, a0
; RV32IDZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV32IDZFH-NEXT: fmax.s fa3, fa5, fa3
; RV32IDZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV32IDZFH-NEXT: fmin.s fa4, fa3, fa4
; RV32IDZFH-NEXT: fcvt.w.s a0, fa4, rtz ; RV32IDZFH-NEXT: fcvt.w.s a0, fa4, rtz
; RV32IDZFH-NEXT: feq.s a1, fa5, fa5 ; RV32IDZFH-NEXT: feq.s a1, fa5, fa5
; RV32IDZFH-NEXT: seqz a1, a1 ; RV32IDZFH-NEXT: xori a1, a1, 1
; RV32IDZFH-NEXT: addi a1, a1, -1 ; RV32IDZFH-NEXT: addi a1, a1, -1
; RV32IDZFH-NEXT: and a0, a1, a0 ; RV32IDZFH-NEXT: and a0, a1, a0
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_si_h_sat: ; RV64IDZFH-LABEL: fcvt_si_h_sat:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IDZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0) ; RV64IDZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; RV64IDZFH-NEXT: lui a0, 815104 ; RV64IDZFH-NEXT: lui a0, 815104
; RV64IDZFH-NEXT: fmv.w.x fa3, a0 ; RV64IDZFH-NEXT: fmv.w.x fa3, a0
; RV64IDZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV64IDZFH-NEXT: fmax.s fa3, fa5, fa3
; RV64IDZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV64IDZFH-NEXT: fmin.s fa4, fa3, fa4
; RV64IDZFH-NEXT: fcvt.l.s a0, fa4, rtz ; RV64IDZFH-NEXT: fcvt.l.s a0, fa4, rtz
; RV64IDZFH-NEXT: feq.s a1, fa5, fa5 ; RV64IDZFH-NEXT: feq.s a1, fa5, fa5
; RV64IDZFH-NEXT: seqz a1, a1 ; RV64IDZFH-NEXT: xori a1, a1, 1
; RV64IDZFH-NEXT: addi a1, a1, -1 ; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a1, a0 ; RV64IDZFH-NEXT: and a0, a1, a0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_si_h_sat: ; RV32I-LABEL: fcvt_si_h_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK32-IZFHMIN-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK32-IZFHMIN-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK32-IZFHMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a0) ; CHECK32-IZFHMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; CHECK32-IZFHMIN-NEXT: lui a0, 815104 ; CHECK32-IZFHMIN-NEXT: lui a0, 815104
; CHECK32-IZFHMIN-NEXT: fmv.w.x fa3, a0 ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa3, a0
; CHECK32-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3 ; CHECK32-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3
; CHECK32-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4 ; CHECK32-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa4, rtz ; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa4, rtz
; CHECK32-IZFHMIN-NEXT: feq.s a1, fa5, fa5 ; CHECK32-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK32-IZFHMIN-NEXT: seqz a1, a1 ; CHECK32-IZFHMIN-NEXT: xori a1, a1, 1
; CHECK32-IZFHMIN-NEXT: addi a1, a1, -1 ; CHECK32-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK32-IZFHMIN-NEXT: and a0, a1, a0 ; CHECK32-IZFHMIN-NEXT: and a0, a1, a0
; CHECK32-IZFHMIN-NEXT: ret ; CHECK32-IZFHMIN-NEXT: ret
; ;
; CHECK64-IZFHMIN-LABEL: fcvt_si_h_sat: ; CHECK64-IZFHMIN-LABEL: fcvt_si_h_sat:
; CHECK64-IZFHMIN: # %bb.0: # %start ; CHECK64-IZFHMIN: # %bb.0: # %start
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK64-IZFHMIN-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK64-IZFHMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a0) ; CHECK64-IZFHMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a0)
; CHECK64-IZFHMIN-NEXT: lui a0, 815104 ; CHECK64-IZFHMIN-NEXT: lui a0, 815104
; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a0 ; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a0
; CHECK64-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3 ; CHECK64-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3
; CHECK64-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4 ; CHECK64-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa4, rtz ; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa4, rtz
; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5 ; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64-IZFHMIN-NEXT: seqz a1, a1 ; CHECK64-IZFHMIN-NEXT: xori a1, a1, 1
; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1 ; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK64-IZFHMIN-NEXT: and a0, a1, a0 ; CHECK64-IZFHMIN-NEXT: and a0, a1, a0
; CHECK64-IZFHMIN-NEXT: ret ; CHECK64-IZFHMIN-NEXT: ret
start: start:
%0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a) %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
ret i16 %0 ret i16 %0
} }
declare i16 @llvm.fptosi.sat.i16.f16(half) declare i16 @llvm.fptosi.sat.i16.f16(half)
▲ Show 20 Lines • Show All 749 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: lui a0, 913408
; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: lui a3, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: bnez s0, .LBB10_2 ; RV32IZFH-NEXT: lui a2, 524288
; RV32IZFH-NEXT: beqz s0, .LBB10_2
; RV32IZFH-NEXT: # %bb.1: # %start ; RV32IZFH-NEXT: # %bb.1: # %start
; RV32IZFH-NEXT: lui a1, 524288 ; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB10_2: # %start ; RV32IZFH-NEXT: .LBB10_2: # %start
; RV32IZFH-NEXT: lui a2, %hi(.LCPI10_0) ; RV32IZFH-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a2) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: beqz a2, .LBB10_4 ; RV32IZFH-NEXT: beqz a3, .LBB10_4
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: addi a1, a3, -1 ; RV32IZFH-NEXT: addi a2, a4, -1
; RV32IZFH-NEXT: .LBB10_4: # %start ; RV32IZFH-NEXT: .LBB10_4: # %start
; RV32IZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
; RV32IZFH-NEXT: seqz a3, a3 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a4, a1, -1
; RV32IZFH-NEXT: and a1, a4, a2
; RV32IZFH-NEXT: neg a2, a3
; RV32IZFH-NEXT: xori a3, s0, 1
; RV32IZFH-NEXT: addi a3, a3, -1 ; RV32IZFH-NEXT: addi a3, a3, -1
; RV32IZFH-NEXT: and a1, a3, a1
; RV32IZFH-NEXT: neg a2, a2
; RV32IZFH-NEXT: neg a4, s0
; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a3, a0 ; RV32IZFH-NEXT: and a0, a3, a0
; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_l_h_sat: ; RV64IZFH-LABEL: fcvt_l_h_sat:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
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; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IDZFH-NEXT: lui a0, 913408 ; RV32IDZFH-NEXT: lui a0, 913408
; RV32IDZFH-NEXT: fmv.w.x fa5, a0 ; RV32IDZFH-NEXT: fmv.w.x fa5, a0
; RV32IDZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFH-NEXT: fle.s s0, fa5, fs0
; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
; RV32IDZFH-NEXT: call __fixsfdi@plt ; RV32IDZFH-NEXT: call __fixsfdi@plt
; RV32IDZFH-NEXT: lui a3, 524288 ; RV32IDZFH-NEXT: lui a4, 524288
; RV32IDZFH-NEXT: bnez s0, .LBB10_2 ; RV32IDZFH-NEXT: lui a2, 524288
; RV32IDZFH-NEXT: beqz s0, .LBB10_2
; RV32IDZFH-NEXT: # %bb.1: # %start ; RV32IDZFH-NEXT: # %bb.1: # %start
; RV32IDZFH-NEXT: lui a1, 524288 ; RV32IDZFH-NEXT: mv a2, a1
; RV32IDZFH-NEXT: .LBB10_2: # %start ; RV32IDZFH-NEXT: .LBB10_2: # %start
; RV32IDZFH-NEXT: lui a2, %hi(.LCPI10_0) ; RV32IDZFH-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a2) ; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; RV32IDZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IDZFH-NEXT: flt.s a3, fa5, fs0
; RV32IDZFH-NEXT: beqz a2, .LBB10_4 ; RV32IDZFH-NEXT: beqz a3, .LBB10_4
; RV32IDZFH-NEXT: # %bb.3: ; RV32IDZFH-NEXT: # %bb.3:
; RV32IDZFH-NEXT: addi a1, a3, -1 ; RV32IDZFH-NEXT: addi a2, a4, -1
; RV32IDZFH-NEXT: .LBB10_4: # %start ; RV32IDZFH-NEXT: .LBB10_4: # %start
; RV32IDZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IDZFH-NEXT: feq.s a1, fs0, fs0
; RV32IDZFH-NEXT: seqz a3, a3 ; RV32IDZFH-NEXT: xori a1, a1, 1
; RV32IDZFH-NEXT: addi a4, a1, -1
; RV32IDZFH-NEXT: and a1, a4, a2
; RV32IDZFH-NEXT: neg a2, a3
; RV32IDZFH-NEXT: xori a3, s0, 1
; RV32IDZFH-NEXT: addi a3, a3, -1 ; RV32IDZFH-NEXT: addi a3, a3, -1
; RV32IDZFH-NEXT: and a1, a3, a1
; RV32IDZFH-NEXT: neg a2, a2
; RV32IDZFH-NEXT: neg a4, s0
; RV32IDZFH-NEXT: and a0, a4, a0
; RV32IDZFH-NEXT: or a0, a2, a0
; RV32IDZFH-NEXT: and a0, a3, a0 ; RV32IDZFH-NEXT: and a0, a3, a0
; RV32IDZFH-NEXT: or a0, a2, a0
; RV32IDZFH-NEXT: and a0, a4, a0
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_l_h_sat: ; RV64IDZFH-LABEL: fcvt_l_h_sat:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz ; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IDZFH-NEXT: feq.h a1, fa0, fa0
; RV64IDZFH-NEXT: seqz a1, a1 ; RV64IDZFH-NEXT: seqz a1, a1
; RV64IDZFH-NEXT: addi a1, a1, -1 ; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a1, a0 ; RV64IDZFH-NEXT: and a0, a1, a0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_l_h_sat: ; RV32I-LABEL: fcvt_l_h_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a1, 913408 ; RV32I-NEXT: lui a1, 913408
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __fixsfdi@plt ; RV32I-NEXT: call __fixsfdi@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: bgez s3, .LBB10_2 ; RV32I-NEXT: bgez s0, .LBB10_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s2, 524288 ; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: .LBB10_2: # %start ; RV32I-NEXT: .LBB10_2: # %start
; RV32I-NEXT: lui s3, 389120 ; RV32I-NEXT: lui a1, 389120
; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: blez a0, .LBB10_4 ; RV32I-NEXT: blez a0, .LBB10_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: addi s2, s4, -1 ; RV32I-NEXT: addi s3, s5, -1
; RV32I-NEXT: .LBB10_4: # %start ; RV32I-NEXT: .LBB10_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and s2, a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg s3, a0
; RV32I-NEXT: lui a1, 913408
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: or s1, s3, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt ; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: sgtz a2, s4
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: slti a3, s0, 0
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: and a3, a3, s2
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_l_h_sat: ; RV64I-LABEL: fcvt_l_h_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; RV32IFZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0
; RV32IFZFHMIN-NEXT: lui a0, 913408 ; RV32IFZFHMIN-NEXT: lui a0, 913408
; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IFZFHMIN-NEXT: call __fixsfdi@plt ; RV32IFZFHMIN-NEXT: call __fixsfdi@plt
; RV32IFZFHMIN-NEXT: lui a3, 524288 ; RV32IFZFHMIN-NEXT: lui a4, 524288
; RV32IFZFHMIN-NEXT: bnez s0, .LBB10_2 ; RV32IFZFHMIN-NEXT: lui a2, 524288
; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_2
; RV32IFZFHMIN-NEXT: # %bb.1: # %start ; RV32IFZFHMIN-NEXT: # %bb.1: # %start
; RV32IFZFHMIN-NEXT: lui a1, 524288 ; RV32IFZFHMIN-NEXT: mv a2, a1
; RV32IFZFHMIN-NEXT: .LBB10_2: # %start ; RV32IFZFHMIN-NEXT: .LBB10_2: # %start
; RV32IFZFHMIN-NEXT: lui a2, %hi(.LCPI10_0) ; RV32IFZFHMIN-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a2) ; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; RV32IFZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IFZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IFZFHMIN-NEXT: beqz a2, .LBB10_4 ; RV32IFZFHMIN-NEXT: beqz a3, .LBB10_4
; RV32IFZFHMIN-NEXT: # %bb.3: ; RV32IFZFHMIN-NEXT: # %bb.3:
; RV32IFZFHMIN-NEXT: addi a1, a3, -1 ; RV32IFZFHMIN-NEXT: addi a2, a4, -1
; RV32IFZFHMIN-NEXT: .LBB10_4: # %start ; RV32IFZFHMIN-NEXT: .LBB10_4: # %start
; RV32IFZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IFZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IFZFHMIN-NEXT: seqz a3, a3 ; RV32IFZFHMIN-NEXT: xori a1, a1, 1
; RV32IFZFHMIN-NEXT: addi a4, a1, -1
; RV32IFZFHMIN-NEXT: and a1, a4, a2
; RV32IFZFHMIN-NEXT: neg a2, a3
; RV32IFZFHMIN-NEXT: xori a3, s0, 1
; RV32IFZFHMIN-NEXT: addi a3, a3, -1 ; RV32IFZFHMIN-NEXT: addi a3, a3, -1
; RV32IFZFHMIN-NEXT: and a1, a3, a1
; RV32IFZFHMIN-NEXT: neg a2, a2
; RV32IFZFHMIN-NEXT: neg a4, s0
; RV32IFZFHMIN-NEXT: and a0, a4, a0
; RV32IFZFHMIN-NEXT: or a0, a2, a0
; RV32IFZFHMIN-NEXT: and a0, a3, a0 ; RV32IFZFHMIN-NEXT: and a0, a3, a0
; RV32IFZFHMIN-NEXT: or a0, a2, a0
; RV32IFZFHMIN-NEXT: and a0, a4, a0
; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IFZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: addi sp, sp, 16
; RV32IFZFHMIN-NEXT: ret ; RV32IFZFHMIN-NEXT: ret
; ;
; CHECK64-IZFHMIN-LABEL: fcvt_l_h_sat: ; CHECK64-IZFHMIN-LABEL: fcvt_l_h_sat:
; CHECK64-IZFHMIN: # %bb.0: # %start ; CHECK64-IZFHMIN: # %bb.0: # %start
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; RV32IDZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IDZFHMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IDZFHMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0
; RV32IDZFHMIN-NEXT: lui a0, 913408 ; RV32IDZFHMIN-NEXT: lui a0, 913408
; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IDZFHMIN-NEXT: call __fixsfdi@plt ; RV32IDZFHMIN-NEXT: call __fixsfdi@plt
; RV32IDZFHMIN-NEXT: lui a3, 524288 ; RV32IDZFHMIN-NEXT: lui a4, 524288
; RV32IDZFHMIN-NEXT: bnez s0, .LBB10_2 ; RV32IDZFHMIN-NEXT: lui a2, 524288
; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_2
; RV32IDZFHMIN-NEXT: # %bb.1: # %start ; RV32IDZFHMIN-NEXT: # %bb.1: # %start
; RV32IDZFHMIN-NEXT: lui a1, 524288 ; RV32IDZFHMIN-NEXT: mv a2, a1
; RV32IDZFHMIN-NEXT: .LBB10_2: # %start ; RV32IDZFHMIN-NEXT: .LBB10_2: # %start
; RV32IDZFHMIN-NEXT: lui a2, %hi(.LCPI10_0) ; RV32IDZFHMIN-NEXT: lui a1, %hi(.LCPI10_0)
; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a2) ; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
; RV32IDZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IDZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IDZFHMIN-NEXT: beqz a2, .LBB10_4 ; RV32IDZFHMIN-NEXT: beqz a3, .LBB10_4
; RV32IDZFHMIN-NEXT: # %bb.3: ; RV32IDZFHMIN-NEXT: # %bb.3:
; RV32IDZFHMIN-NEXT: addi a1, a3, -1 ; RV32IDZFHMIN-NEXT: addi a2, a4, -1
; RV32IDZFHMIN-NEXT: .LBB10_4: # %start ; RV32IDZFHMIN-NEXT: .LBB10_4: # %start
; RV32IDZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IDZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IDZFHMIN-NEXT: seqz a3, a3 ; RV32IDZFHMIN-NEXT: xori a1, a1, 1
; RV32IDZFHMIN-NEXT: addi a4, a1, -1
; RV32IDZFHMIN-NEXT: and a1, a4, a2
; RV32IDZFHMIN-NEXT: neg a2, a3
; RV32IDZFHMIN-NEXT: xori a3, s0, 1
; RV32IDZFHMIN-NEXT: addi a3, a3, -1 ; RV32IDZFHMIN-NEXT: addi a3, a3, -1
; RV32IDZFHMIN-NEXT: and a1, a3, a1
; RV32IDZFHMIN-NEXT: neg a2, a2
; RV32IDZFHMIN-NEXT: neg a4, s0
; RV32IDZFHMIN-NEXT: and a0, a4, a0
; RV32IDZFHMIN-NEXT: or a0, a2, a0
; RV32IDZFHMIN-NEXT: and a0, a3, a0 ; RV32IDZFHMIN-NEXT: and a0, a3, a0
; RV32IDZFHMIN-NEXT: or a0, a2, a0
; RV32IDZFHMIN-NEXT: and a0, a4, a0
; RV32IDZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFHMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IDZFHMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IDZFHMIN-NEXT: addi sp, sp, 16 ; RV32IDZFHMIN-NEXT: addi sp, sp, 16
; RV32IDZFHMIN-NEXT: ret ; RV32IDZFHMIN-NEXT: ret
start: start:
%0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a) %0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
ret i64 %0 ret i64 %0
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI12_0)(a0) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: flt.s a0, fa5, fa0 ; RV32IZFH-NEXT: flt.s a0, fa5, fa0
; RV32IZFH-NEXT: neg s0, a0 ; RV32IZFH-NEXT: neg s0, a0
; RV32IZFH-NEXT: fmv.w.x fa5, zero ; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: fle.s a0, fa5, fa0 ; RV32IZFH-NEXT: fle.s a0, fa5, fa0
; RV32IZFH-NEXT: neg s1, a0 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: addi s1, a0, -1
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: and a0, s1, a0 ; RV32IZFH-NEXT: and a0, s1, a0
; RV32IZFH-NEXT: or a0, s0, a0 ; RV32IZFH-NEXT: or a0, s0, a0
; RV32IZFH-NEXT: and a1, s1, a1 ; RV32IZFH-NEXT: and a1, s1, a1
; RV32IZFH-NEXT: or a1, s0, a1 ; RV32IZFH-NEXT: or a1, s0, a1
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32IDZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI12_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI12_0)
; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI12_0)(a0) ; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IDZFH-NEXT: flt.s a0, fa5, fa0 ; RV32IDZFH-NEXT: flt.s a0, fa5, fa0
; RV32IDZFH-NEXT: neg s0, a0 ; RV32IDZFH-NEXT: neg s0, a0
; RV32IDZFH-NEXT: fmv.w.x fa5, zero ; RV32IDZFH-NEXT: fmv.w.x fa5, zero
; RV32IDZFH-NEXT: fle.s a0, fa5, fa0 ; RV32IDZFH-NEXT: fle.s a0, fa5, fa0
; RV32IDZFH-NEXT: neg s1, a0 ; RV32IDZFH-NEXT: xori a0, a0, 1
; RV32IDZFH-NEXT: addi s1, a0, -1
; RV32IDZFH-NEXT: call __fixunssfdi@plt ; RV32IDZFH-NEXT: call __fixunssfdi@plt
; RV32IDZFH-NEXT: and a0, s1, a0 ; RV32IDZFH-NEXT: and a0, s1, a0
; RV32IDZFH-NEXT: or a0, s0, a0 ; RV32IDZFH-NEXT: or a0, s0, a0
; RV32IDZFH-NEXT: and a1, s1, a1 ; RV32IDZFH-NEXT: and a1, s1, a1
; RV32IDZFH-NEXT: or a1, s0, a1 ; RV32IDZFH-NEXT: or a1, s0, a1
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_lu_h_sat: ; RV64IDZFH-LABEL: fcvt_lu_h_sat:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz ; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IDZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IDZFH-NEXT: feq.h a1, fa0, fa0
; RV64IDZFH-NEXT: seqz a1, a1 ; RV64IDZFH-NEXT: seqz a1, a1
; RV64IDZFH-NEXT: addi a1, a1, -1 ; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a1, a0 ; RV64IDZFH-NEXT: and a0, a1, a0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_lu_h_sat: ; RV32I-LABEL: fcvt_lu_h_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui s1, 391168 ; RV32I-NEXT: lui a1, 391168
; RV32I-NEXT: addi s1, s1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg s3, a0 ; RV32I-NEXT: neg s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi s4, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt ; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: and a0, s2, a0
; RV32I-NEXT: and a0, s4, a0 ; RV32I-NEXT: or a0, s1, a0
; RV32I-NEXT: or s3, s3, a0 ; RV32I-NEXT: and a1, s2, a1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: neg s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a1, a0, s2
; RV32I-NEXT: or a1, s1, a1 ; RV32I-NEXT: or a1, s1, a1
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_lu_h_sat: ; RV64I-LABEL: fcvt_lu_h_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
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; CHECK32-IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; CHECK32-IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; CHECK32-IZFHMIN-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK32-IZFHMIN-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK32-IZFHMIN-NEXT: flw fa5, %lo(.LCPI12_0)(a0) ; CHECK32-IZFHMIN-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa0, fa0 ; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa0, fa0
; CHECK32-IZFHMIN-NEXT: flt.s a0, fa5, fa0 ; CHECK32-IZFHMIN-NEXT: flt.s a0, fa5, fa0
; CHECK32-IZFHMIN-NEXT: neg s0, a0 ; CHECK32-IZFHMIN-NEXT: neg s0, a0
; CHECK32-IZFHMIN-NEXT: fmv.w.x fa5, zero ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa5, zero
; CHECK32-IZFHMIN-NEXT: fle.s a0, fa5, fa0 ; CHECK32-IZFHMIN-NEXT: fle.s a0, fa5, fa0
; CHECK32-IZFHMIN-NEXT: neg s1, a0 ; CHECK32-IZFHMIN-NEXT: xori a0, a0, 1
; CHECK32-IZFHMIN-NEXT: addi s1, a0, -1
; CHECK32-IZFHMIN-NEXT: call __fixunssfdi@plt ; CHECK32-IZFHMIN-NEXT: call __fixunssfdi@plt
; CHECK32-IZFHMIN-NEXT: and a0, s1, a0 ; CHECK32-IZFHMIN-NEXT: and a0, s1, a0
; CHECK32-IZFHMIN-NEXT: or a0, s0, a0 ; CHECK32-IZFHMIN-NEXT: or a0, s0, a0
; CHECK32-IZFHMIN-NEXT: and a1, s1, a1 ; CHECK32-IZFHMIN-NEXT: and a1, s1, a1
; CHECK32-IZFHMIN-NEXT: or a1, s0, a1 ; CHECK32-IZFHMIN-NEXT: or a1, s0, a1
; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32-IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK32-IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; CHECK32-IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0) ; RV32IZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0)
; RV32IZFH-NEXT: lui a0, 815104 ; RV32IZFH-NEXT: lui a0, 815104
; RV32IZFH-NEXT: fmv.w.x fa3, a0 ; RV32IZFH-NEXT: fmv.w.x fa3, a0
; RV32IZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV32IZFH-NEXT: fmax.s fa3, fa5, fa3
; RV32IZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV32IZFH-NEXT: fmin.s fa4, fa3, fa4
; RV32IZFH-NEXT: fcvt.w.s a0, fa4, rtz ; RV32IZFH-NEXT: fcvt.w.s a0, fa4, rtz
; RV32IZFH-NEXT: feq.s a1, fa5, fa5 ; RV32IZFH-NEXT: feq.s a1, fa5, fa5
; RV32IZFH-NEXT: seqz a1, a1 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a1, a1, -1 ; RV32IZFH-NEXT: addi a1, a1, -1
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_w_s_sat_i16: ; RV64IZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0) ; RV64IZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0)
; RV64IZFH-NEXT: lui a0, 815104 ; RV64IZFH-NEXT: lui a0, 815104
; RV64IZFH-NEXT: fmv.w.x fa3, a0 ; RV64IZFH-NEXT: fmv.w.x fa3, a0
; RV64IZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV64IZFH-NEXT: fmax.s fa3, fa5, fa3
; RV64IZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV64IZFH-NEXT: fmin.s fa4, fa3, fa4
; RV64IZFH-NEXT: fcvt.l.s a0, fa4, rtz ; RV64IZFH-NEXT: fcvt.l.s a0, fa4, rtz
; RV64IZFH-NEXT: feq.s a1, fa5, fa5 ; RV64IZFH-NEXT: feq.s a1, fa5, fa5
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: xori a1, a1, 1
; RV64IZFH-NEXT: addi a1, a1, -1 ; RV64IZFH-NEXT: addi a1, a1, -1
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i16: ; RV32IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h fa5, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IDZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0) ; RV32IDZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0)
; RV32IDZFH-NEXT: lui a0, 815104 ; RV32IDZFH-NEXT: lui a0, 815104
; RV32IDZFH-NEXT: fmv.w.x fa3, a0 ; RV32IDZFH-NEXT: fmv.w.x fa3, a0
; RV32IDZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV32IDZFH-NEXT: fmax.s fa3, fa5, fa3
; RV32IDZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV32IDZFH-NEXT: fmin.s fa4, fa3, fa4
; RV32IDZFH-NEXT: fcvt.w.s a0, fa4, rtz ; RV32IDZFH-NEXT: fcvt.w.s a0, fa4, rtz
; RV32IDZFH-NEXT: feq.s a1, fa5, fa5 ; RV32IDZFH-NEXT: feq.s a1, fa5, fa5
; RV32IDZFH-NEXT: seqz a1, a1 ; RV32IDZFH-NEXT: xori a1, a1, 1
; RV32IDZFH-NEXT: addi a1, a1, -1 ; RV32IDZFH-NEXT: addi a1, a1, -1
; RV32IDZFH-NEXT: and a0, a1, a0 ; RV32IDZFH-NEXT: and a0, a1, a0
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i16: ; RV64IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_0) ; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IDZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0) ; RV64IDZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a0)
; RV64IDZFH-NEXT: lui a0, 815104 ; RV64IDZFH-NEXT: lui a0, 815104
; RV64IDZFH-NEXT: fmv.w.x fa3, a0 ; RV64IDZFH-NEXT: fmv.w.x fa3, a0
; RV64IDZFH-NEXT: fmax.s fa3, fa5, fa3 ; RV64IDZFH-NEXT: fmax.s fa3, fa5, fa3
; RV64IDZFH-NEXT: fmin.s fa4, fa3, fa4 ; RV64IDZFH-NEXT: fmin.s fa4, fa3, fa4
; RV64IDZFH-NEXT: fcvt.l.s a0, fa4, rtz ; RV64IDZFH-NEXT: fcvt.l.s a0, fa4, rtz
; RV64IDZFH-NEXT: feq.s a1, fa5, fa5 ; RV64IDZFH-NEXT: feq.s a1, fa5, fa5
; RV64IDZFH-NEXT: seqz a1, a1 ; RV64IDZFH-NEXT: xori a1, a1, 1
; RV64IDZFH-NEXT: addi a1, a1, -1 ; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a1, a0 ; RV64IDZFH-NEXT: and a0, a1, a0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK32-IZFHMIN-NEXT: lui a0, %hi(.LCPI32_0) ; CHECK32-IZFHMIN-NEXT: lui a0, %hi(.LCPI32_0)
; CHECK32-IZFHMIN-NEXT: flw fa4, %lo(.LCPI32_0)(a0) ; CHECK32-IZFHMIN-NEXT: flw fa4, %lo(.LCPI32_0)(a0)
; CHECK32-IZFHMIN-NEXT: lui a0, 815104 ; CHECK32-IZFHMIN-NEXT: lui a0, 815104
; CHECK32-IZFHMIN-NEXT: fmv.w.x fa3, a0 ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa3, a0
; CHECK32-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3 ; CHECK32-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3
; CHECK32-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4 ; CHECK32-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa4, rtz ; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa4, rtz
; CHECK32-IZFHMIN-NEXT: feq.s a1, fa5, fa5 ; CHECK32-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK32-IZFHMIN-NEXT: seqz a1, a1 ; CHECK32-IZFHMIN-NEXT: xori a1, a1, 1
; CHECK32-IZFHMIN-NEXT: addi a1, a1, -1 ; CHECK32-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK32-IZFHMIN-NEXT: and a0, a1, a0 ; CHECK32-IZFHMIN-NEXT: and a0, a1, a0
; CHECK32-IZFHMIN-NEXT: ret ; CHECK32-IZFHMIN-NEXT: ret
; ;
; CHECK64-IZFHMIN-LABEL: fcvt_w_s_sat_i16: ; CHECK64-IZFHMIN-LABEL: fcvt_w_s_sat_i16:
; CHECK64-IZFHMIN: # %bb.0: # %start ; CHECK64-IZFHMIN: # %bb.0: # %start
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: lui a0, %hi(.LCPI32_0) ; CHECK64-IZFHMIN-NEXT: lui a0, %hi(.LCPI32_0)
; CHECK64-IZFHMIN-NEXT: flw fa4, %lo(.LCPI32_0)(a0) ; CHECK64-IZFHMIN-NEXT: flw fa4, %lo(.LCPI32_0)(a0)
; CHECK64-IZFHMIN-NEXT: lui a0, 815104 ; CHECK64-IZFHMIN-NEXT: lui a0, 815104
; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a0 ; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a0
; CHECK64-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3 ; CHECK64-IZFHMIN-NEXT: fmax.s fa3, fa5, fa3
; CHECK64-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4 ; CHECK64-IZFHMIN-NEXT: fmin.s fa4, fa3, fa4
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa4, rtz ; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa4, rtz
; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5 ; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64-IZFHMIN-NEXT: seqz a1, a1 ; CHECK64-IZFHMIN-NEXT: xori a1, a1, 1
; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1 ; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK64-IZFHMIN-NEXT: and a0, a1, a0 ; CHECK64-IZFHMIN-NEXT: and a0, a1, a0
; CHECK64-IZFHMIN-NEXT: ret ; CHECK64-IZFHMIN-NEXT: ret
start: start:
%0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a) %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
ret i16 %0 ret i16 %0
} }
▲ Show 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: lui a0, 798720 ; RV32IZFH-NEXT: lui a0, 798720
; RV32IZFH-NEXT: fmv.w.x fa4, a0 ; RV32IZFH-NEXT: fmv.w.x fa4, a0
; RV32IZFH-NEXT: fmax.s fa4, fa5, fa4 ; RV32IZFH-NEXT: fmax.s fa4, fa5, fa4
; RV32IZFH-NEXT: lui a0, 274400 ; RV32IZFH-NEXT: lui a0, 274400
; RV32IZFH-NEXT: fmv.w.x fa3, a0 ; RV32IZFH-NEXT: fmv.w.x fa3, a0
; RV32IZFH-NEXT: fmin.s fa4, fa4, fa3 ; RV32IZFH-NEXT: fmin.s fa4, fa4, fa3
; RV32IZFH-NEXT: fcvt.w.s a0, fa4, rtz ; RV32IZFH-NEXT: fcvt.w.s a0, fa4, rtz
; RV32IZFH-NEXT: feq.s a1, fa5, fa5 ; RV32IZFH-NEXT: feq.s a1, fa5, fa5
; RV32IZFH-NEXT: seqz a1, a1 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a1, a1, -1 ; RV32IZFH-NEXT: addi a1, a1, -1
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcvt_w_s_sat_i8: ; RV64IZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IZFH: # %bb.0: # %start ; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IZFH-NEXT: lui a0, 798720 ; RV64IZFH-NEXT: lui a0, 798720
; RV64IZFH-NEXT: fmv.w.x fa4, a0 ; RV64IZFH-NEXT: fmv.w.x fa4, a0
; RV64IZFH-NEXT: fmax.s fa4, fa5, fa4 ; RV64IZFH-NEXT: fmax.s fa4, fa5, fa4
; RV64IZFH-NEXT: lui a0, 274400 ; RV64IZFH-NEXT: lui a0, 274400
; RV64IZFH-NEXT: fmv.w.x fa3, a0 ; RV64IZFH-NEXT: fmv.w.x fa3, a0
; RV64IZFH-NEXT: fmin.s fa4, fa4, fa3 ; RV64IZFH-NEXT: fmin.s fa4, fa4, fa3
; RV64IZFH-NEXT: fcvt.l.s a0, fa4, rtz ; RV64IZFH-NEXT: fcvt.l.s a0, fa4, rtz
; RV64IZFH-NEXT: feq.s a1, fa5, fa5 ; RV64IZFH-NEXT: feq.s a1, fa5, fa5
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: xori a1, a1, 1
; RV64IZFH-NEXT: addi a1, a1, -1 ; RV64IZFH-NEXT: addi a1, a1, -1
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; ;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i8: ; RV32IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV32IDZFH: # %bb.0: # %start ; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h fa5, fa0 ; RV32IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV32IDZFH-NEXT: lui a0, 798720 ; RV32IDZFH-NEXT: lui a0, 798720
; RV32IDZFH-NEXT: fmv.w.x fa4, a0 ; RV32IDZFH-NEXT: fmv.w.x fa4, a0
; RV32IDZFH-NEXT: fmax.s fa4, fa5, fa4 ; RV32IDZFH-NEXT: fmax.s fa4, fa5, fa4
; RV32IDZFH-NEXT: lui a0, 274400 ; RV32IDZFH-NEXT: lui a0, 274400
; RV32IDZFH-NEXT: fmv.w.x fa3, a0 ; RV32IDZFH-NEXT: fmv.w.x fa3, a0
; RV32IDZFH-NEXT: fmin.s fa4, fa4, fa3 ; RV32IDZFH-NEXT: fmin.s fa4, fa4, fa3
; RV32IDZFH-NEXT: fcvt.w.s a0, fa4, rtz ; RV32IDZFH-NEXT: fcvt.w.s a0, fa4, rtz
; RV32IDZFH-NEXT: feq.s a1, fa5, fa5 ; RV32IDZFH-NEXT: feq.s a1, fa5, fa5
; RV32IDZFH-NEXT: seqz a1, a1 ; RV32IDZFH-NEXT: xori a1, a1, 1
; RV32IDZFH-NEXT: addi a1, a1, -1 ; RV32IDZFH-NEXT: addi a1, a1, -1
; RV32IDZFH-NEXT: and a0, a1, a0 ; RV32IDZFH-NEXT: and a0, a1, a0
; RV32IDZFH-NEXT: ret ; RV32IDZFH-NEXT: ret
; ;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i8: ; RV64IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IDZFH: # %bb.0: # %start ; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0 ; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFH-NEXT: lui a0, 798720 ; RV64IDZFH-NEXT: lui a0, 798720
; RV64IDZFH-NEXT: fmv.w.x fa4, a0 ; RV64IDZFH-NEXT: fmv.w.x fa4, a0
; RV64IDZFH-NEXT: fmax.s fa4, fa5, fa4 ; RV64IDZFH-NEXT: fmax.s fa4, fa5, fa4
; RV64IDZFH-NEXT: lui a0, 274400 ; RV64IDZFH-NEXT: lui a0, 274400
; RV64IDZFH-NEXT: fmv.w.x fa3, a0 ; RV64IDZFH-NEXT: fmv.w.x fa3, a0
; RV64IDZFH-NEXT: fmin.s fa4, fa4, fa3 ; RV64IDZFH-NEXT: fmin.s fa4, fa4, fa3
; RV64IDZFH-NEXT: fcvt.l.s a0, fa4, rtz ; RV64IDZFH-NEXT: fcvt.l.s a0, fa4, rtz
; RV64IDZFH-NEXT: feq.s a1, fa5, fa5 ; RV64IDZFH-NEXT: feq.s a1, fa5, fa5
; RV64IDZFH-NEXT: seqz a1, a1 ; RV64IDZFH-NEXT: xori a1, a1, 1
; RV64IDZFH-NEXT: addi a1, a1, -1 ; RV64IDZFH-NEXT: addi a1, a1, -1
; RV64IDZFH-NEXT: and a0, a1, a0 ; RV64IDZFH-NEXT: and a0, a1, a0
; RV64IDZFH-NEXT: ret ; RV64IDZFH-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; CHECK32-IZFHMIN-NEXT: lui a0, 798720 ; CHECK32-IZFHMIN-NEXT: lui a0, 798720
; CHECK32-IZFHMIN-NEXT: fmv.w.x fa4, a0 ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECK32-IZFHMIN-NEXT: fmax.s fa4, fa5, fa4 ; CHECK32-IZFHMIN-NEXT: fmax.s fa4, fa5, fa4
; CHECK32-IZFHMIN-NEXT: lui a0, 274400 ; CHECK32-IZFHMIN-NEXT: lui a0, 274400
; CHECK32-IZFHMIN-NEXT: fmv.w.x fa3, a0 ; CHECK32-IZFHMIN-NEXT: fmv.w.x fa3, a0
; CHECK32-IZFHMIN-NEXT: fmin.s fa4, fa4, fa3 ; CHECK32-IZFHMIN-NEXT: fmin.s fa4, fa4, fa3
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa4, rtz ; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa4, rtz
; CHECK32-IZFHMIN-NEXT: feq.s a1, fa5, fa5 ; CHECK32-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK32-IZFHMIN-NEXT: seqz a1, a1 ; CHECK32-IZFHMIN-NEXT: xori a1, a1, 1
; CHECK32-IZFHMIN-NEXT: addi a1, a1, -1 ; CHECK32-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK32-IZFHMIN-NEXT: and a0, a1, a0 ; CHECK32-IZFHMIN-NEXT: and a0, a1, a0
; CHECK32-IZFHMIN-NEXT: ret ; CHECK32-IZFHMIN-NEXT: ret
; ;
; CHECK64-IZFHMIN-LABEL: fcvt_w_s_sat_i8: ; CHECK64-IZFHMIN-LABEL: fcvt_w_s_sat_i8:
; CHECK64-IZFHMIN: # %bb.0: # %start ; CHECK64-IZFHMIN: # %bb.0: # %start
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: lui a0, 798720 ; CHECK64-IZFHMIN-NEXT: lui a0, 798720
; CHECK64-IZFHMIN-NEXT: fmv.w.x fa4, a0 ; CHECK64-IZFHMIN-NEXT: fmv.w.x fa4, a0
; CHECK64-IZFHMIN-NEXT: fmax.s fa4, fa5, fa4 ; CHECK64-IZFHMIN-NEXT: fmax.s fa4, fa5, fa4
; CHECK64-IZFHMIN-NEXT: lui a0, 274400 ; CHECK64-IZFHMIN-NEXT: lui a0, 274400
; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a0 ; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a0
; CHECK64-IZFHMIN-NEXT: fmin.s fa4, fa4, fa3 ; CHECK64-IZFHMIN-NEXT: fmin.s fa4, fa4, fa3
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa4, rtz ; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa4, rtz
; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5 ; CHECK64-IZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECK64-IZFHMIN-NEXT: seqz a1, a1 ; CHECK64-IZFHMIN-NEXT: xori a1, a1, 1
; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1 ; CHECK64-IZFHMIN-NEXT: addi a1, a1, -1
; CHECK64-IZFHMIN-NEXT: and a0, a1, a0 ; CHECK64-IZFHMIN-NEXT: and a0, a1, a0
; CHECK64-IZFHMIN-NEXT: ret ; CHECK64-IZFHMIN-NEXT: ret
start: start:
%0 = tail call i8 @llvm.fptosi.sat.i8.f16(half %a) %0 = tail call i8 @llvm.fptosi.sat.i8.f16(half %a)
ret i8 %0 ret i8 %0
} }
declare i8 @llvm.fptosi.sat.i8.f16(half) declare i8 @llvm.fptosi.sat.i8.f16(half)
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llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

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; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB1_2: ; RV32IZFH-NEXT: .LBB1_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: lui a0, 913408
; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: lui a3, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: bnez s0, .LBB1_4 ; RV32IZFH-NEXT: lui a2, 524288
; RV32IZFH-NEXT: beqz s0, .LBB1_4
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: lui a1, 524288 ; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB1_4: ; RV32IZFH-NEXT: .LBB1_4:
; RV32IZFH-NEXT: lui a2, %hi(.LCPI1_1) ; RV32IZFH-NEXT: lui a1, %hi(.LCPI1_1)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a2) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: beqz a2, .LBB1_6 ; RV32IZFH-NEXT: beqz a3, .LBB1_6
; RV32IZFH-NEXT: # %bb.5: ; RV32IZFH-NEXT: # %bb.5:
; RV32IZFH-NEXT: addi a1, a3, -1 ; RV32IZFH-NEXT: addi a2, a4, -1
; RV32IZFH-NEXT: .LBB1_6: ; RV32IZFH-NEXT: .LBB1_6:
; RV32IZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
; RV32IZFH-NEXT: seqz a3, a3 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a3, a3, -1 ; RV32IZFH-NEXT: addi a4, a1, -1
; RV32IZFH-NEXT: and a1, a3, a1 ; RV32IZFH-NEXT: and a1, a4, a2
; RV32IZFH-NEXT: neg a4, s0 ; RV32IZFH-NEXT: xori a2, s0, 1
; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: neg a2, a3
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a3, a0 ; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_floor_si64: ; RV64IZFH-LABEL: test_floor_si64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
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; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: lui a0, 913408
; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: call __fixsfdi@plt
; RV32IZFHMIN-NEXT: lui a3, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288
; RV32IZFHMIN-NEXT: bnez s0, .LBB1_4 ; RV32IZFHMIN-NEXT: lui a2, 524288
; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4
; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: # %bb.3:
; RV32IZFHMIN-NEXT: lui a1, 524288 ; RV32IZFHMIN-NEXT: mv a2, a1
; RV32IZFHMIN-NEXT: .LBB1_4: ; RV32IZFHMIN-NEXT: .LBB1_4:
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0)
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a2) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a1)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: beqz a2, .LBB1_6 ; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6
; RV32IZFHMIN-NEXT: # %bb.5: ; RV32IZFHMIN-NEXT: # %bb.5:
; RV32IZFHMIN-NEXT: addi a1, a3, -1 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
; RV32IZFHMIN-NEXT: .LBB1_6: ; RV32IZFHMIN-NEXT: .LBB1_6:
; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IZFHMIN-NEXT: seqz a3, a3 ; RV32IZFHMIN-NEXT: xori a1, a1, 1
; RV32IZFHMIN-NEXT: addi a3, a3, -1 ; RV32IZFHMIN-NEXT: addi a4, a1, -1
; RV32IZFHMIN-NEXT: and a1, a3, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2
; RV32IZFHMIN-NEXT: neg a4, s0 ; RV32IZFHMIN-NEXT: xori a2, s0, 1
; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: neg a2, a3
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: or a0, a2, a0
; RV32IZFHMIN-NEXT: and a0, a3, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_floor_si64: ; RV64IZFHMIN-LABEL: test_floor_si64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64IZFHMIN-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_floor_ui64(half %x) nounwind { define i64 @test_floor_ui64(half %x) nounwind {
; RV32IZFH-LABEL: test_floor_ui64: ; RV32IZFH-LABEL: test_floor_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
; RV32IZFH-NEXT: fabs.h fa4, fa0 ; RV32IZFH-NEXT: fabs.h fa4, fa0
; RV32IZFH-NEXT: flt.h a0, fa4, fa5 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
; RV32IZFH-NEXT: beqz a0, .LBB3_2 ; RV32IZFH-NEXT: beqz a0, .LBB3_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB3_2: ; RV32IZFH-NEXT: .LBB3_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: fle.s a0, fa5, fs0
; RV32IZFH-NEXT: neg s0, a0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: lui a2, %hi(.LCPI3_1) ; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI3_1)(a2) ; RV32IZFH-NEXT: fle.s a2, fa5, fs0
; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: lui a3, %hi(.LCPI3_1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI3_1)(a3)
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: xori a2, a2, 1
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: and a1, s0, a1 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: or a1, a2, a1 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: neg a3, a3
; RV32IZFH-NEXT: or a0, a3, a0
; RV32IZFH-NEXT: and a1, a2, a1
; RV32IZFH-NEXT: or a1, a3, a1
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_floor_ui64: ; RV64IZFH-LABEL: test_floor_ui64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: seqz a1, a1
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; RV32IZFHMIN-NEXT: beqz a0, .LBB3_2 ; RV32IZFHMIN-NEXT: beqz a0, .LBB3_2
; RV32IZFHMIN-NEXT: # %bb.1: ; RV32IZFHMIN-NEXT: # %bb.1:
; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB3_2: ; RV32IZFHMIN-NEXT: .LBB3_2:
; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
; RV32IZFHMIN-NEXT: neg s0, a0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixunssfdi@plt ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI3_0) ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a2) ; RV32IZFHMIN-NEXT: fle.s a2, fa5, fs0
; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: lui a3, %hi(.LCPI3_0)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a3)
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: xori a2, a2, 1
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: and a1, s0, a1 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: or a1, a2, a1 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: neg a3, a3
; RV32IZFHMIN-NEXT: or a0, a3, a0
; RV32IZFHMIN-NEXT: and a1, a2, a1
; RV32IZFHMIN-NEXT: or a1, a3, a1
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_floor_ui64: ; RV64IZFHMIN-LABEL: test_floor_ui64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IZFHMIN-NEXT: lui a0, 307200 ; RV64IZFHMIN-NEXT: lui a0, 307200
; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB5_2: ; RV32IZFH-NEXT: .LBB5_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: lui a0, 913408
; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: lui a3, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: bnez s0, .LBB5_4 ; RV32IZFH-NEXT: lui a2, 524288
; RV32IZFH-NEXT: beqz s0, .LBB5_4
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: lui a1, 524288 ; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB5_4: ; RV32IZFH-NEXT: .LBB5_4:
; RV32IZFH-NEXT: lui a2, %hi(.LCPI5_1) ; RV32IZFH-NEXT: lui a1, %hi(.LCPI5_1)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a2) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: beqz a2, .LBB5_6 ; RV32IZFH-NEXT: beqz a3, .LBB5_6
; RV32IZFH-NEXT: # %bb.5: ; RV32IZFH-NEXT: # %bb.5:
; RV32IZFH-NEXT: addi a1, a3, -1 ; RV32IZFH-NEXT: addi a2, a4, -1
; RV32IZFH-NEXT: .LBB5_6: ; RV32IZFH-NEXT: .LBB5_6:
; RV32IZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
; RV32IZFH-NEXT: seqz a3, a3 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a3, a3, -1 ; RV32IZFH-NEXT: addi a4, a1, -1
; RV32IZFH-NEXT: and a1, a3, a1 ; RV32IZFH-NEXT: and a1, a4, a2
; RV32IZFH-NEXT: neg a4, s0 ; RV32IZFH-NEXT: xori a2, s0, 1
; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: neg a2, a3
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a3, a0 ; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_ceil_si64: ; RV64IZFH-LABEL: test_ceil_si64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
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; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: lui a0, 913408
; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: call __fixsfdi@plt
; RV32IZFHMIN-NEXT: lui a3, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288
; RV32IZFHMIN-NEXT: bnez s0, .LBB5_4 ; RV32IZFHMIN-NEXT: lui a2, 524288
; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4
; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: # %bb.3:
; RV32IZFHMIN-NEXT: lui a1, 524288 ; RV32IZFHMIN-NEXT: mv a2, a1
; RV32IZFHMIN-NEXT: .LBB5_4: ; RV32IZFHMIN-NEXT: .LBB5_4:
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI5_0)
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a2) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a1)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: beqz a2, .LBB5_6 ; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6
; RV32IZFHMIN-NEXT: # %bb.5: ; RV32IZFHMIN-NEXT: # %bb.5:
; RV32IZFHMIN-NEXT: addi a1, a3, -1 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
; RV32IZFHMIN-NEXT: .LBB5_6: ; RV32IZFHMIN-NEXT: .LBB5_6:
; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IZFHMIN-NEXT: seqz a3, a3 ; RV32IZFHMIN-NEXT: xori a1, a1, 1
; RV32IZFHMIN-NEXT: addi a3, a3, -1 ; RV32IZFHMIN-NEXT: addi a4, a1, -1
; RV32IZFHMIN-NEXT: and a1, a3, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2
; RV32IZFHMIN-NEXT: neg a4, s0 ; RV32IZFHMIN-NEXT: xori a2, s0, 1
; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: neg a2, a3
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: or a0, a2, a0
; RV32IZFHMIN-NEXT: and a0, a3, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_ceil_si64: ; RV64IZFHMIN-LABEL: test_ceil_si64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64IZFHMIN-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_ceil_ui64(half %x) nounwind { define i64 @test_ceil_ui64(half %x) nounwind {
; RV32IZFH-LABEL: test_ceil_ui64: ; RV32IZFH-LABEL: test_ceil_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0)
; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
; RV32IZFH-NEXT: fabs.h fa4, fa0 ; RV32IZFH-NEXT: fabs.h fa4, fa0
; RV32IZFH-NEXT: flt.h a0, fa4, fa5 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
; RV32IZFH-NEXT: beqz a0, .LBB7_2 ; RV32IZFH-NEXT: beqz a0, .LBB7_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB7_2: ; RV32IZFH-NEXT: .LBB7_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: fle.s a0, fa5, fs0
; RV32IZFH-NEXT: neg s0, a0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: lui a2, %hi(.LCPI7_1) ; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI7_1)(a2) ; RV32IZFH-NEXT: fle.s a2, fa5, fs0
; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: lui a3, %hi(.LCPI7_1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI7_1)(a3)
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: xori a2, a2, 1
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: and a1, s0, a1 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: or a1, a2, a1 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: neg a3, a3
; RV32IZFH-NEXT: or a0, a3, a0
; RV32IZFH-NEXT: and a1, a2, a1
; RV32IZFH-NEXT: or a1, a3, a1
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_ceil_ui64: ; RV64IZFH-LABEL: test_ceil_ui64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: seqz a1, a1
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; RV32IZFHMIN-NEXT: beqz a0, .LBB7_2 ; RV32IZFHMIN-NEXT: beqz a0, .LBB7_2
; RV32IZFHMIN-NEXT: # %bb.1: ; RV32IZFHMIN-NEXT: # %bb.1:
; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB7_2: ; RV32IZFHMIN-NEXT: .LBB7_2:
; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
; RV32IZFHMIN-NEXT: neg s0, a0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixunssfdi@plt ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI7_0) ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI7_0)(a2) ; RV32IZFHMIN-NEXT: fle.s a2, fa5, fs0
; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: lui a3, %hi(.LCPI7_0)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI7_0)(a3)
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: xori a2, a2, 1
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: and a1, s0, a1 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: or a1, a2, a1 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: neg a3, a3
; RV32IZFHMIN-NEXT: or a0, a3, a0
; RV32IZFHMIN-NEXT: and a1, a2, a1
; RV32IZFHMIN-NEXT: or a1, a3, a1
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_ceil_ui64: ; RV64IZFHMIN-LABEL: test_ceil_ui64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IZFHMIN-NEXT: lui a0, 307200 ; RV64IZFHMIN-NEXT: lui a0, 307200
; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB9_2: ; RV32IZFH-NEXT: .LBB9_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: lui a0, 913408
; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: lui a3, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: bnez s0, .LBB9_4 ; RV32IZFH-NEXT: lui a2, 524288
; RV32IZFH-NEXT: beqz s0, .LBB9_4
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: lui a1, 524288 ; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB9_4: ; RV32IZFH-NEXT: .LBB9_4:
; RV32IZFH-NEXT: lui a2, %hi(.LCPI9_1) ; RV32IZFH-NEXT: lui a1, %hi(.LCPI9_1)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a2) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: beqz a2, .LBB9_6 ; RV32IZFH-NEXT: beqz a3, .LBB9_6
; RV32IZFH-NEXT: # %bb.5: ; RV32IZFH-NEXT: # %bb.5:
; RV32IZFH-NEXT: addi a1, a3, -1 ; RV32IZFH-NEXT: addi a2, a4, -1
; RV32IZFH-NEXT: .LBB9_6: ; RV32IZFH-NEXT: .LBB9_6:
; RV32IZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
; RV32IZFH-NEXT: seqz a3, a3 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a3, a3, -1 ; RV32IZFH-NEXT: addi a4, a1, -1
; RV32IZFH-NEXT: and a1, a3, a1 ; RV32IZFH-NEXT: and a1, a4, a2
; RV32IZFH-NEXT: neg a4, s0 ; RV32IZFH-NEXT: xori a2, s0, 1
; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: neg a2, a3
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a3, a0 ; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_trunc_si64: ; RV64IZFH-LABEL: test_trunc_si64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
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; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: lui a0, 913408
; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: call __fixsfdi@plt
; RV32IZFHMIN-NEXT: lui a3, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288
; RV32IZFHMIN-NEXT: bnez s0, .LBB9_4 ; RV32IZFHMIN-NEXT: lui a2, 524288
; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4
; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: # %bb.3:
; RV32IZFHMIN-NEXT: lui a1, 524288 ; RV32IZFHMIN-NEXT: mv a2, a1
; RV32IZFHMIN-NEXT: .LBB9_4: ; RV32IZFHMIN-NEXT: .LBB9_4:
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI9_0)
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a2) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a1)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: beqz a2, .LBB9_6 ; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6
; RV32IZFHMIN-NEXT: # %bb.5: ; RV32IZFHMIN-NEXT: # %bb.5:
; RV32IZFHMIN-NEXT: addi a1, a3, -1 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
; RV32IZFHMIN-NEXT: .LBB9_6: ; RV32IZFHMIN-NEXT: .LBB9_6:
; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IZFHMIN-NEXT: seqz a3, a3 ; RV32IZFHMIN-NEXT: xori a1, a1, 1
; RV32IZFHMIN-NEXT: addi a3, a3, -1 ; RV32IZFHMIN-NEXT: addi a4, a1, -1
; RV32IZFHMIN-NEXT: and a1, a3, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2
; RV32IZFHMIN-NEXT: neg a4, s0 ; RV32IZFHMIN-NEXT: xori a2, s0, 1
; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: neg a2, a3
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: or a0, a2, a0
; RV32IZFHMIN-NEXT: and a0, a3, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_trunc_si64: ; RV64IZFHMIN-LABEL: test_trunc_si64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64IZFHMIN-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_trunc_ui64(half %x) nounwind { define i64 @test_trunc_ui64(half %x) nounwind {
; RV32IZFH-LABEL: test_trunc_ui64: ; RV32IZFH-LABEL: test_trunc_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
; RV32IZFH-NEXT: fabs.h fa4, fa0 ; RV32IZFH-NEXT: fabs.h fa4, fa0
; RV32IZFH-NEXT: flt.h a0, fa4, fa5 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
; RV32IZFH-NEXT: beqz a0, .LBB11_2 ; RV32IZFH-NEXT: beqz a0, .LBB11_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB11_2: ; RV32IZFH-NEXT: .LBB11_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: fle.s a0, fa5, fs0
; RV32IZFH-NEXT: neg s0, a0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: lui a2, %hi(.LCPI11_1) ; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI11_1)(a2) ; RV32IZFH-NEXT: fle.s a2, fa5, fs0
; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: lui a3, %hi(.LCPI11_1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI11_1)(a3)
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: xori a2, a2, 1
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: and a1, s0, a1 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: or a1, a2, a1 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: neg a3, a3
; RV32IZFH-NEXT: or a0, a3, a0
; RV32IZFH-NEXT: and a1, a2, a1
; RV32IZFH-NEXT: or a1, a3, a1
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_trunc_ui64: ; RV64IZFH-LABEL: test_trunc_ui64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: seqz a1, a1
Show All 11 Lines
; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2 ; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2
; RV32IZFHMIN-NEXT: # %bb.1: ; RV32IZFHMIN-NEXT: # %bb.1:
; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB11_2: ; RV32IZFHMIN-NEXT: .LBB11_2:
; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
; RV32IZFHMIN-NEXT: neg s0, a0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixunssfdi@plt ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI11_0) ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI11_0)(a2) ; RV32IZFHMIN-NEXT: fle.s a2, fa5, fs0
; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: lui a3, %hi(.LCPI11_0)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI11_0)(a3)
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: xori a2, a2, 1
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: and a1, s0, a1 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: or a1, a2, a1 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: neg a3, a3
; RV32IZFHMIN-NEXT: or a0, a3, a0
; RV32IZFHMIN-NEXT: and a1, a2, a1
; RV32IZFHMIN-NEXT: or a1, a3, a1
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_trunc_ui64: ; RV64IZFHMIN-LABEL: test_trunc_ui64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IZFHMIN-NEXT: lui a0, 307200 ; RV64IZFHMIN-NEXT: lui a0, 307200
; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB13_2: ; RV32IZFH-NEXT: .LBB13_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: lui a0, 913408
; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: lui a3, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: bnez s0, .LBB13_4 ; RV32IZFH-NEXT: lui a2, 524288
; RV32IZFH-NEXT: beqz s0, .LBB13_4
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: lui a1, 524288 ; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB13_4: ; RV32IZFH-NEXT: .LBB13_4:
; RV32IZFH-NEXT: lui a2, %hi(.LCPI13_1) ; RV32IZFH-NEXT: lui a1, %hi(.LCPI13_1)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a2) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: beqz a2, .LBB13_6 ; RV32IZFH-NEXT: beqz a3, .LBB13_6
; RV32IZFH-NEXT: # %bb.5: ; RV32IZFH-NEXT: # %bb.5:
; RV32IZFH-NEXT: addi a1, a3, -1 ; RV32IZFH-NEXT: addi a2, a4, -1
; RV32IZFH-NEXT: .LBB13_6: ; RV32IZFH-NEXT: .LBB13_6:
; RV32IZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
; RV32IZFH-NEXT: seqz a3, a3 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a3, a3, -1 ; RV32IZFH-NEXT: addi a4, a1, -1
; RV32IZFH-NEXT: and a1, a3, a1 ; RV32IZFH-NEXT: and a1, a4, a2
; RV32IZFH-NEXT: neg a4, s0 ; RV32IZFH-NEXT: xori a2, s0, 1
; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: neg a2, a3
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a3, a0 ; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_round_si64: ; RV64IZFH-LABEL: test_round_si64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
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; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: lui a0, 913408
; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: call __fixsfdi@plt
; RV32IZFHMIN-NEXT: lui a3, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288
; RV32IZFHMIN-NEXT: bnez s0, .LBB13_4 ; RV32IZFHMIN-NEXT: lui a2, 524288
; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4
; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: # %bb.3:
; RV32IZFHMIN-NEXT: lui a1, 524288 ; RV32IZFHMIN-NEXT: mv a2, a1
; RV32IZFHMIN-NEXT: .LBB13_4: ; RV32IZFHMIN-NEXT: .LBB13_4:
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI13_0)
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a2) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a1)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: beqz a2, .LBB13_6 ; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6
; RV32IZFHMIN-NEXT: # %bb.5: ; RV32IZFHMIN-NEXT: # %bb.5:
; RV32IZFHMIN-NEXT: addi a1, a3, -1 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
; RV32IZFHMIN-NEXT: .LBB13_6: ; RV32IZFHMIN-NEXT: .LBB13_6:
; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IZFHMIN-NEXT: seqz a3, a3 ; RV32IZFHMIN-NEXT: xori a1, a1, 1
; RV32IZFHMIN-NEXT: addi a3, a3, -1 ; RV32IZFHMIN-NEXT: addi a4, a1, -1
; RV32IZFHMIN-NEXT: and a1, a3, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2
; RV32IZFHMIN-NEXT: neg a4, s0 ; RV32IZFHMIN-NEXT: xori a2, s0, 1
; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: neg a2, a3
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: or a0, a2, a0
; RV32IZFHMIN-NEXT: and a0, a3, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_round_si64: ; RV64IZFHMIN-LABEL: test_round_si64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64IZFHMIN-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_round_ui64(half %x) nounwind { define i64 @test_round_ui64(half %x) nounwind {
; RV32IZFH-LABEL: test_round_ui64: ; RV32IZFH-LABEL: test_round_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0)
; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
; RV32IZFH-NEXT: fabs.h fa4, fa0 ; RV32IZFH-NEXT: fabs.h fa4, fa0
; RV32IZFH-NEXT: flt.h a0, fa4, fa5 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
; RV32IZFH-NEXT: beqz a0, .LBB15_2 ; RV32IZFH-NEXT: beqz a0, .LBB15_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB15_2: ; RV32IZFH-NEXT: .LBB15_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: fle.s a0, fa5, fs0
; RV32IZFH-NEXT: neg s0, a0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: lui a2, %hi(.LCPI15_1) ; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI15_1)(a2) ; RV32IZFH-NEXT: fle.s a2, fa5, fs0
; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: lui a3, %hi(.LCPI15_1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI15_1)(a3)
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: xori a2, a2, 1
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: and a1, s0, a1 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: or a1, a2, a1 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: neg a3, a3
; RV32IZFH-NEXT: or a0, a3, a0
; RV32IZFH-NEXT: and a1, a2, a1
; RV32IZFH-NEXT: or a1, a3, a1
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_round_ui64: ; RV64IZFH-LABEL: test_round_ui64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: seqz a1, a1
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; RV32IZFHMIN-NEXT: beqz a0, .LBB15_2 ; RV32IZFHMIN-NEXT: beqz a0, .LBB15_2
; RV32IZFHMIN-NEXT: # %bb.1: ; RV32IZFHMIN-NEXT: # %bb.1:
; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB15_2: ; RV32IZFHMIN-NEXT: .LBB15_2:
; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
; RV32IZFHMIN-NEXT: neg s0, a0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixunssfdi@plt ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI15_0) ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI15_0)(a2) ; RV32IZFHMIN-NEXT: fle.s a2, fa5, fs0
; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: lui a3, %hi(.LCPI15_0)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI15_0)(a3)
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: xori a2, a2, 1
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: and a1, s0, a1 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: or a1, a2, a1 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: neg a3, a3
; RV32IZFHMIN-NEXT: or a0, a3, a0
; RV32IZFHMIN-NEXT: and a1, a2, a1
; RV32IZFHMIN-NEXT: or a1, a3, a1
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_round_ui64: ; RV64IZFHMIN-LABEL: test_round_ui64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IZFHMIN-NEXT: lui a0, 307200 ; RV64IZFHMIN-NEXT: lui a0, 307200
; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB17_2: ; RV32IZFH-NEXT: .LBB17_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: lui a0, 913408
; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixsfdi@plt ; RV32IZFH-NEXT: call __fixsfdi@plt
; RV32IZFH-NEXT: lui a3, 524288 ; RV32IZFH-NEXT: lui a4, 524288
; RV32IZFH-NEXT: bnez s0, .LBB17_4 ; RV32IZFH-NEXT: lui a2, 524288
; RV32IZFH-NEXT: beqz s0, .LBB17_4
; RV32IZFH-NEXT: # %bb.3: ; RV32IZFH-NEXT: # %bb.3:
; RV32IZFH-NEXT: lui a1, 524288 ; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB17_4: ; RV32IZFH-NEXT: .LBB17_4:
; RV32IZFH-NEXT: lui a2, %hi(.LCPI17_1) ; RV32IZFH-NEXT: lui a1, %hi(.LCPI17_1)
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a2) ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: beqz a2, .LBB17_6 ; RV32IZFH-NEXT: beqz a3, .LBB17_6
; RV32IZFH-NEXT: # %bb.5: ; RV32IZFH-NEXT: # %bb.5:
; RV32IZFH-NEXT: addi a1, a3, -1 ; RV32IZFH-NEXT: addi a2, a4, -1
; RV32IZFH-NEXT: .LBB17_6: ; RV32IZFH-NEXT: .LBB17_6:
; RV32IZFH-NEXT: feq.s a3, fs0, fs0 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
; RV32IZFH-NEXT: seqz a3, a3 ; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: addi a3, a3, -1 ; RV32IZFH-NEXT: addi a4, a1, -1
; RV32IZFH-NEXT: and a1, a3, a1 ; RV32IZFH-NEXT: and a1, a4, a2
; RV32IZFH-NEXT: neg a4, s0 ; RV32IZFH-NEXT: xori a2, s0, 1
; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: neg a2, a3
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: or a0, a2, a0
; RV32IZFH-NEXT: and a0, a3, a0 ; RV32IZFH-NEXT: and a0, a4, a0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_roundeven_si64: ; RV64IZFH-LABEL: test_roundeven_si64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
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; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: lui a0, 913408
; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixsfdi@plt ; RV32IZFHMIN-NEXT: call __fixsfdi@plt
; RV32IZFHMIN-NEXT: lui a3, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288
; RV32IZFHMIN-NEXT: bnez s0, .LBB17_4 ; RV32IZFHMIN-NEXT: lui a2, 524288
; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4
; RV32IZFHMIN-NEXT: # %bb.3: ; RV32IZFHMIN-NEXT: # %bb.3:
; RV32IZFHMIN-NEXT: lui a1, 524288 ; RV32IZFHMIN-NEXT: mv a2, a1
; RV32IZFHMIN-NEXT: .LBB17_4: ; RV32IZFHMIN-NEXT: .LBB17_4:
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI17_0)
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a2) ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a1)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: beqz a2, .LBB17_6 ; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6
; RV32IZFHMIN-NEXT: # %bb.5: ; RV32IZFHMIN-NEXT: # %bb.5:
; RV32IZFHMIN-NEXT: addi a1, a3, -1 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
; RV32IZFHMIN-NEXT: .LBB17_6: ; RV32IZFHMIN-NEXT: .LBB17_6:
; RV32IZFHMIN-NEXT: feq.s a3, fs0, fs0 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
; RV32IZFHMIN-NEXT: seqz a3, a3 ; RV32IZFHMIN-NEXT: xori a1, a1, 1
; RV32IZFHMIN-NEXT: addi a3, a3, -1 ; RV32IZFHMIN-NEXT: addi a4, a1, -1
; RV32IZFHMIN-NEXT: and a1, a3, a1 ; RV32IZFHMIN-NEXT: and a1, a4, a2
; RV32IZFHMIN-NEXT: neg a4, s0 ; RV32IZFHMIN-NEXT: xori a2, s0, 1
; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: neg a2, a3
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: or a0, a2, a0
; RV32IZFHMIN-NEXT: and a0, a3, a0 ; RV32IZFHMIN-NEXT: and a0, a4, a0
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_roundeven_si64: ; RV64IZFHMIN-LABEL: test_roundeven_si64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64IZFHMIN-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @test_roundeven_ui64(half %x) nounwind { define i64 @test_roundeven_ui64(half %x) nounwind {
; RV32IZFH-LABEL: test_roundeven_ui64: ; RV32IZFH-LABEL: test_roundeven_ui64:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0) ; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0) ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
; RV32IZFH-NEXT: fabs.h fa4, fa0 ; RV32IZFH-NEXT: fabs.h fa4, fa0
; RV32IZFH-NEXT: flt.h a0, fa4, fa5 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
; RV32IZFH-NEXT: beqz a0, .LBB19_2 ; RV32IZFH-NEXT: beqz a0, .LBB19_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
; RV32IZFH-NEXT: .LBB19_2: ; RV32IZFH-NEXT: .LBB19_2:
; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: fle.s a0, fa5, fs0
; RV32IZFH-NEXT: neg s0, a0
; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0
; RV32IZFH-NEXT: call __fixunssfdi@plt ; RV32IZFH-NEXT: call __fixunssfdi@plt
; RV32IZFH-NEXT: lui a2, %hi(.LCPI19_1) ; RV32IZFH-NEXT: fmv.w.x fa5, zero
; RV32IZFH-NEXT: flw fa5, %lo(.LCPI19_1)(a2) ; RV32IZFH-NEXT: fle.s a2, fa5, fs0
; RV32IZFH-NEXT: and a0, s0, a0 ; RV32IZFH-NEXT: lui a3, %hi(.LCPI19_1)
; RV32IZFH-NEXT: flt.s a2, fa5, fs0 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI19_1)(a3)
; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: xori a2, a2, 1
; RV32IZFH-NEXT: or a0, a2, a0 ; RV32IZFH-NEXT: addi a2, a2, -1
; RV32IZFH-NEXT: and a1, s0, a1 ; RV32IZFH-NEXT: and a0, a2, a0
; RV32IZFH-NEXT: or a1, a2, a1 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
; RV32IZFH-NEXT: neg a3, a3
; RV32IZFH-NEXT: or a0, a3, a0
; RV32IZFH-NEXT: and a1, a2, a1
; RV32IZFH-NEXT: or a1, a3, a1
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: test_roundeven_ui64: ; RV64IZFH-LABEL: test_roundeven_ui64:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: seqz a1, a1 ; RV64IZFH-NEXT: seqz a1, a1
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; RV32IZFHMIN-NEXT: beqz a0, .LBB19_2 ; RV32IZFHMIN-NEXT: beqz a0, .LBB19_2
; RV32IZFHMIN-NEXT: # %bb.1: ; RV32IZFHMIN-NEXT: # %bb.1:
; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB19_2: ; RV32IZFHMIN-NEXT: .LBB19_2:
; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
; RV32IZFHMIN-NEXT: neg s0, a0
; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
; RV32IZFHMIN-NEXT: call __fixunssfdi@plt ; RV32IZFHMIN-NEXT: call __fixunssfdi@plt
; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI19_0) ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI19_0)(a2) ; RV32IZFHMIN-NEXT: fle.s a2, fa5, fs0
; RV32IZFHMIN-NEXT: and a0, s0, a0 ; RV32IZFHMIN-NEXT: lui a3, %hi(.LCPI19_0)
; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI19_0)(a3)
; RV32IZFHMIN-NEXT: neg a2, a2 ; RV32IZFHMIN-NEXT: xori a2, a2, 1
; RV32IZFHMIN-NEXT: or a0, a2, a0 ; RV32IZFHMIN-NEXT: addi a2, a2, -1
; RV32IZFHMIN-NEXT: and a1, s0, a1 ; RV32IZFHMIN-NEXT: and a0, a2, a0
; RV32IZFHMIN-NEXT: or a1, a2, a1 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
; RV32IZFHMIN-NEXT: neg a3, a3
; RV32IZFHMIN-NEXT: or a0, a3, a0
; RV32IZFHMIN-NEXT: and a1, a2, a1
; RV32IZFHMIN-NEXT: or a1, a3, a1
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFHMIN-NEXT: addi sp, sp, 16 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret ; RV32IZFHMIN-NEXT: ret
; ;
; RV64IZFHMIN-LABEL: test_roundeven_ui64: ; RV64IZFHMIN-LABEL: test_roundeven_ui64:
; RV64IZFHMIN: # %bb.0: ; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IZFHMIN-NEXT: lui a0, 307200 ; RV64IZFHMIN-NEXT: lui a0, 307200
; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
Show All 30 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; RV32-NEXT: lui a0, %hi(.LCPI10_1) ; RV32-NEXT: lui a0, %hi(.LCPI10_1)
; RV32-NEXT: fld fa4, %lo(.LCPI10_1)(a0) ; RV32-NEXT: fld fa4, %lo(.LCPI10_1)(a0)
; RV32-NEXT: vslidedown.vi v9, v8, 1 ; RV32-NEXT: vslidedown.vi v9, v8, 1
; RV32-NEXT: vfmv.f.s fa3, v9 ; RV32-NEXT: vfmv.f.s fa3, v9
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfmv.f.s fa3, v8 ; RV32-NEXT: vfmv.f.s fa3, v8
; RV32-NEXT: fmax.d fa5, fa3, fa5 ; RV32-NEXT: fmax.d fa5, fa3, fa5
; RV32-NEXT: fmin.d fa5, fa5, fa4 ; RV32-NEXT: fmin.d fa5, fa5, fa4
; RV32-NEXT: fcvt.w.d a0, fa5, rtz ; RV32-NEXT: fcvt.w.d a0, fa5, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf8, tu, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, tu, ma
; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vse8.v v9, (a1) ; RV32-NEXT: vse8.v v9, (a1)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fp2si_v2f64_v2i8: ; RV64-LABEL: fp2si_v2f64_v2i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: lui a0, %hi(.LCPI10_0) ; RV64-NEXT: lui a0, %hi(.LCPI10_0)
; RV64-NEXT: fld fa5, %lo(.LCPI10_0)(a0) ; RV64-NEXT: fld fa5, %lo(.LCPI10_0)(a0)
; RV64-NEXT: lui a0, %hi(.LCPI10_1) ; RV64-NEXT: lui a0, %hi(.LCPI10_1)
; RV64-NEXT: fld fa4, %lo(.LCPI10_1)(a0) ; RV64-NEXT: fld fa4, %lo(.LCPI10_1)(a0)
; RV64-NEXT: vslidedown.vi v9, v8, 1 ; RV64-NEXT: vslidedown.vi v9, v8, 1
; RV64-NEXT: vfmv.f.s fa3, v9 ; RV64-NEXT: vfmv.f.s fa3, v9
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addi a2, a2, -1 ; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vmv.v.x v9, a0
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfmv.f.s fa3, v8 ; RV64-NEXT: vfmv.f.s fa3, v8
; RV64-NEXT: fmax.d fa5, fa3, fa5 ; RV64-NEXT: fmax.d fa5, fa3, fa5
; RV64-NEXT: fmin.d fa5, fa5, fa4 ; RV64-NEXT: fmin.d fa5, fa5, fa4
; RV64-NEXT: fcvt.l.d a0, fa5, rtz ; RV64-NEXT: fcvt.l.d a0, fa5, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addi a2, a2, -1 ; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf8, tu, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf8, tu, ma
; RV64-NEXT: vmv.s.x v9, a0 ; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vse8.v v9, (a1) ; RV64-NEXT: vse8.v v9, (a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <2 x double>, ptr %x %a = load <2 x double>, ptr %x
%d = call <2 x i8> @llvm.fptosi.sat.v2i8.v2f64(<2 x double> %a) %d = call <2 x i8> @llvm.fptosi.sat.v2i8.v2f64(<2 x double> %a)
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0) ; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: lui a0, %hi(.LCPI12_1) ; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: fld fa4, %lo(.LCPI12_1)(a0) ; RV32-NEXT: fld fa4, %lo(.LCPI12_1)(a0)
; RV32-NEXT: vfmv.f.s fa3, v8 ; RV32-NEXT: vfmv.f.s fa3, v8
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 8(sp) ; RV32-NEXT: sb a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma
; RV32-NEXT: vslidedown.vi v12, v8, 7 ; RV32-NEXT: vslidedown.vi v12, v8, 7
; RV32-NEXT: vfmv.f.s fa3, v12 ; RV32-NEXT: vfmv.f.s fa3, v12
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 15(sp) ; RV32-NEXT: sb a0, 15(sp)
; RV32-NEXT: vslidedown.vi v12, v8, 6 ; RV32-NEXT: vslidedown.vi v12, v8, 6
; RV32-NEXT: vfmv.f.s fa3, v12 ; RV32-NEXT: vfmv.f.s fa3, v12
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 14(sp) ; RV32-NEXT: sb a0, 14(sp)
; RV32-NEXT: vslidedown.vi v12, v8, 5 ; RV32-NEXT: vslidedown.vi v12, v8, 5
; RV32-NEXT: vfmv.f.s fa3, v12 ; RV32-NEXT: vfmv.f.s fa3, v12
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 13(sp) ; RV32-NEXT: sb a0, 13(sp)
; RV32-NEXT: vslidedown.vi v12, v8, 4 ; RV32-NEXT: vslidedown.vi v12, v8, 4
; RV32-NEXT: vfmv.f.s fa3, v12 ; RV32-NEXT: vfmv.f.s fa3, v12
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 12(sp) ; RV32-NEXT: sb a0, 12(sp)
; RV32-NEXT: vslidedown.vi v12, v8, 3 ; RV32-NEXT: vslidedown.vi v12, v8, 3
; RV32-NEXT: vfmv.f.s fa3, v12 ; RV32-NEXT: vfmv.f.s fa3, v12
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 11(sp) ; RV32-NEXT: sb a0, 11(sp)
; RV32-NEXT: vslidedown.vi v12, v8, 2 ; RV32-NEXT: vslidedown.vi v12, v8, 2
; RV32-NEXT: vfmv.f.s fa3, v12 ; RV32-NEXT: vfmv.f.s fa3, v12
; RV32-NEXT: fmax.d fa2, fa3, fa5 ; RV32-NEXT: fmax.d fa2, fa3, fa5
; RV32-NEXT: fmin.d fa2, fa2, fa4 ; RV32-NEXT: fmin.d fa2, fa2, fa4
; RV32-NEXT: fcvt.w.d a0, fa2, rtz ; RV32-NEXT: fcvt.w.d a0, fa2, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 10(sp) ; RV32-NEXT: sb a0, 10(sp)
; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: vfmv.f.s fa3, v8 ; RV32-NEXT: vfmv.f.s fa3, v8
; RV32-NEXT: fmax.d fa5, fa3, fa5 ; RV32-NEXT: fmax.d fa5, fa3, fa5
; RV32-NEXT: fmin.d fa5, fa5, fa4 ; RV32-NEXT: fmin.d fa5, fa5, fa4
; RV32-NEXT: fcvt.w.d a0, fa5, rtz ; RV32-NEXT: fcvt.w.d a0, fa5, rtz
; RV32-NEXT: feq.d a2, fa3, fa3 ; RV32-NEXT: feq.d a2, fa3, fa3
; RV32-NEXT: seqz a2, a2 ; RV32-NEXT: xori a2, a2, 1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: sb a0, 9(sp) ; RV32-NEXT: sb a0, 9(sp)
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vle8.v v8, (a0) ; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: vse8.v v8, (a1) ; RV32-NEXT: vse8.v v8, (a1)
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
Show All 9 Lines
; RV64-NEXT: fld fa5, %lo(.LCPI12_0)(a0) ; RV64-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV64-NEXT: lui a0, %hi(.LCPI12_1) ; RV64-NEXT: lui a0, %hi(.LCPI12_1)
; RV64-NEXT: fld fa4, %lo(.LCPI12_1)(a0) ; RV64-NEXT: fld fa4, %lo(.LCPI12_1)(a0)
; RV64-NEXT: vfmv.f.s fa3, v8 ; RV64-NEXT: vfmv.f.s fa3, v8
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 8(sp) ; RV64-NEXT: sb a0, 8(sp)
; RV64-NEXT: vsetivli zero, 1, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m4, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 7 ; RV64-NEXT: vslidedown.vi v12, v8, 7
; RV64-NEXT: vfmv.f.s fa3, v12 ; RV64-NEXT: vfmv.f.s fa3, v12
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 15(sp) ; RV64-NEXT: sb a0, 15(sp)
; RV64-NEXT: vslidedown.vi v12, v8, 6 ; RV64-NEXT: vslidedown.vi v12, v8, 6
; RV64-NEXT: vfmv.f.s fa3, v12 ; RV64-NEXT: vfmv.f.s fa3, v12
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 14(sp) ; RV64-NEXT: sb a0, 14(sp)
; RV64-NEXT: vslidedown.vi v12, v8, 5 ; RV64-NEXT: vslidedown.vi v12, v8, 5
; RV64-NEXT: vfmv.f.s fa3, v12 ; RV64-NEXT: vfmv.f.s fa3, v12
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 13(sp) ; RV64-NEXT: sb a0, 13(sp)
; RV64-NEXT: vslidedown.vi v12, v8, 4 ; RV64-NEXT: vslidedown.vi v12, v8, 4
; RV64-NEXT: vfmv.f.s fa3, v12 ; RV64-NEXT: vfmv.f.s fa3, v12
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 12(sp) ; RV64-NEXT: sb a0, 12(sp)
; RV64-NEXT: vslidedown.vi v12, v8, 3 ; RV64-NEXT: vslidedown.vi v12, v8, 3
; RV64-NEXT: vfmv.f.s fa3, v12 ; RV64-NEXT: vfmv.f.s fa3, v12
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 11(sp) ; RV64-NEXT: sb a0, 11(sp)
; RV64-NEXT: vslidedown.vi v12, v8, 2 ; RV64-NEXT: vslidedown.vi v12, v8, 2
; RV64-NEXT: vfmv.f.s fa3, v12 ; RV64-NEXT: vfmv.f.s fa3, v12
; RV64-NEXT: fmax.d fa2, fa3, fa5 ; RV64-NEXT: fmax.d fa2, fa3, fa5
; RV64-NEXT: fmin.d fa2, fa2, fa4 ; RV64-NEXT: fmin.d fa2, fa2, fa4
; RV64-NEXT: fcvt.l.d a0, fa2, rtz ; RV64-NEXT: fcvt.l.d a0, fa2, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 10(sp) ; RV64-NEXT: sb a0, 10(sp)
; RV64-NEXT: vslidedown.vi v8, v8, 1 ; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: vfmv.f.s fa3, v8 ; RV64-NEXT: vfmv.f.s fa3, v8
; RV64-NEXT: fmax.d fa5, fa3, fa5 ; RV64-NEXT: fmax.d fa5, fa3, fa5
; RV64-NEXT: fmin.d fa5, fa5, fa4 ; RV64-NEXT: fmin.d fa5, fa5, fa4
; RV64-NEXT: fcvt.l.d a0, fa5, rtz ; RV64-NEXT: fcvt.l.d a0, fa5, rtz
; RV64-NEXT: feq.d a2, fa3, fa3 ; RV64-NEXT: feq.d a2, fa3, fa3
; RV64-NEXT: seqz a2, a2 ; RV64-NEXT: xori a2, a2, 1
; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a0, a2, a0 ; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: sb a0, 9(sp) ; RV64-NEXT: sb a0, 9(sp)
; RV64-NEXT: addi a0, sp, 8 ; RV64-NEXT: addi a0, sp, 8
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vle8.v v8, (a0) ; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vse8.v v8, (a1) ; RV64-NEXT: vse8.v v8, (a1)
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 179 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll

Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_signed_v2f64_v2i32: ; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI9_0 ; CHECK-NEXT: vldr d0, .LCPI9_0
; CHECK-NEXT: vmov r9, r8, d9 ; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r11, r10, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: str.w r11, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: str.w r10, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI9_1
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: vmov r5, r3, d0
; CHECK-NEXT: str r3, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: str r5, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: vldr d0, .LCPI9_1
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r0, #-2147483648
; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r0, #-2147483648 ; CHECK-NEXT: movne.w r11, #-2147483648
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: ldr r5, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r11, #-2147483648
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r2, r7 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r3, r6 ; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r11, #-2147483648 ; CHECK-NEXT: mvnne r11, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: vmov r10, r7, d8
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #1
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0 ; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: ldrd r2, r3, [sp, #20] @ 8-byte Folded Reload ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r5, #-1
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-2147483648
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r5, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #20] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r10, #-1
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r5, r11
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: vmov q0[3], q0[1], r4, r2
; CHECK-NEXT: vmov q0[2], q0[0], r11, r0 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vmov q0[3], q0[1], r10, r5
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI9_0: ; CHECK-NEXT: .LCPI9_0:
; CHECK-NEXT: .long 4290772992 @ double 2147483647
; CHECK-NEXT: .long 1105199103
; CHECK-NEXT: .LCPI9_1:
; CHECK-NEXT: .long 0 @ double -2147483648 ; CHECK-NEXT: .long 0 @ double -2147483648
; CHECK-NEXT: .long 3252682752 ; CHECK-NEXT: .long 3252682752
; CHECK-NEXT: .LCPI9_1:
; CHECK-NEXT: .long 4290772992 @ double 2147483647
; CHECK-NEXT: .long 1105199103
%x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) { define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) {
; CHECK-LABEL: test_signed_v3f64_v3i32: ; CHECK-LABEL: test_signed_v3f64_v3i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
▲ Show 20 Lines • Show All 2,255 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_signed_v2f64_v2i8: ; CHECK-LABEL: test_signed_v2f64_v2i8:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI33_0 ; CHECK-NEXT: vldr d0, .LCPI33_0
; CHECK-NEXT: vmov r9, r8, d9 ; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r11, r10, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: str.w r11, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: str.w r10, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI33_1
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: vmov r5, r3, d0
; CHECK-NEXT: str r3, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: str r5, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: vldr d0, .LCPI33_1
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: mvneq r0, #127
; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #127 ; CHECK-NEXT: mvnne r11, #127
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: ldr r5, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: mvneq r11, #127
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r2, r7 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r3, r6 ; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #127 ; CHECK-NEXT: movne.w r11, #127
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: vmov r10, r7, d8
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #1
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0 ; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: ldrd r2, r3, [sp, #20] @ 8-byte Folded Reload ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r5, #-1
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r5, #127
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #127
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #20] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r10, #-1
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r5, r11
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: vmov q0[3], q0[1], r4, r2
; CHECK-NEXT: vmov q0[2], q0[0], r11, r0 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vmov q0[3], q0[1], r10, r5
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI33_0: ; CHECK-NEXT: .LCPI33_0:
; CHECK-NEXT: .long 0 @ double 127
; CHECK-NEXT: .long 1080016896
; CHECK-NEXT: .LCPI33_1:
; CHECK-NEXT: .long 0 @ double -128 ; CHECK-NEXT: .long 0 @ double -128
; CHECK-NEXT: .long 3227516928 ; CHECK-NEXT: .long 3227516928
; CHECK-NEXT: .LCPI33_1:
; CHECK-NEXT: .long 0 @ double 127
; CHECK-NEXT: .long 1080016896
%x = call <2 x i8> @llvm.fptosi.sat.v2f64.v2i8(<2 x double> %f) %x = call <2 x i8> @llvm.fptosi.sat.v2f64.v2i8(<2 x double> %f)
ret <2 x i8> %x ret <2 x i8> %x
} }
define arm_aapcs_vfpcc <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i13: ; CHECK-LABEL: test_signed_v2f64_v2i13:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI34_0 ; CHECK-NEXT: vldr d0, .LCPI34_0
; CHECK-NEXT: vmov r10, r11, d9 ; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r8, r5, d0
; CHECK-NEXT: str.w r8, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: str r5, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI34_1
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: strd r3, r2, [sp, #16] @ 8-byte Folded Spill ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: vldr d0, .LCPI34_1
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r1, #-1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0 ; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r5 ; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldrd r5, r2, [sp, #16] @ 8-byte Folded Reload
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r8, #-1
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r4, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: vmov r10, r7, d8
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: itt eq ; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: movweq r9, #61440 ; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: movteq r9, #65535 ; CHECK-NEXT: it ne
; CHECK-NEXT: ldrd r2, r3, [sp, #24] @ 8-byte Folded Reload ; CHECK-NEXT: movne.w r8, #1
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: itt eq
; CHECK-NEXT: movweq r0, #61440
; CHECK-NEXT: movteq r0, #65535
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r0, #4095 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #24] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r9, #4095 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r5, #61440
; CHECK-NEXT: movtne r5, #65535
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r11, #61440
; CHECK-NEXT: movtne r11, #65535
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r11, #4095
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r5, #4095
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #0 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r9, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r5, r11
; CHECK-NEXT: vmov q0[3], q0[1], r8, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r4, r0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI34_0: ; CHECK-NEXT: .LCPI34_0:
; CHECK-NEXT: .long 0 @ double 4095
; CHECK-NEXT: .long 1085275648
; CHECK-NEXT: .LCPI34_1:
; CHECK-NEXT: .long 0 @ double -4096 ; CHECK-NEXT: .long 0 @ double -4096
; CHECK-NEXT: .long 3232759808 ; CHECK-NEXT: .long 3232759808
; CHECK-NEXT: .LCPI34_1:
; CHECK-NEXT: .long 0 @ double 4095
; CHECK-NEXT: .long 1085275648
%x = call <2 x i13> @llvm.fptosi.sat.v2f64.v2i13(<2 x double> %f) %x = call <2 x i13> @llvm.fptosi.sat.v2f64.v2i13(<2 x double> %f)
ret <2 x i13> %x ret <2 x i13> %x
} }
define arm_aapcs_vfpcc <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i16: ; CHECK-LABEL: test_signed_v2f64_v2i16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI35_0 ; CHECK-NEXT: vldr d0, .LCPI35_0
; CHECK-NEXT: vmov r10, r11, d9 ; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r8, r5, d0
; CHECK-NEXT: str.w r8, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: str r5, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI35_1
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: strd r3, r2, [sp, #16] @ 8-byte Folded Spill ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: vldr d0, .LCPI35_1
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r1, #-1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0 ; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r5 ; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldrd r5, r2, [sp, #16] @ 8-byte Folded Reload
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r8, #-1
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r4, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: vmov r10, r7, d8
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: itt eq ; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: movweq r9, #32768 ; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: movteq r9, #65535 ; CHECK-NEXT: it ne
; CHECK-NEXT: ldrd r2, r3, [sp, #24] @ 8-byte Folded Reload ; CHECK-NEXT: movne.w r8, #1
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: itt eq
; CHECK-NEXT: movweq r0, #32768
; CHECK-NEXT: movteq r0, #65535
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r0, #32767 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #24] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r9, #32767 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r5, #32768
; CHECK-NEXT: movtne r5, #65535
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r11, #32768
; CHECK-NEXT: movtne r11, #65535
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r11, #32767
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r5, #32767
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #0 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r9, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r5, r11
; CHECK-NEXT: vmov q0[3], q0[1], r8, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r4, r0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI35_0: ; CHECK-NEXT: .LCPI35_0:
; CHECK-NEXT: .long 0 @ double 32767
; CHECK-NEXT: .long 1088421824
; CHECK-NEXT: .LCPI35_1:
; CHECK-NEXT: .long 0 @ double -32768 ; CHECK-NEXT: .long 0 @ double -32768
; CHECK-NEXT: .long 3235905536 ; CHECK-NEXT: .long 3235905536
; CHECK-NEXT: .LCPI35_1:
; CHECK-NEXT: .long 0 @ double 32767
; CHECK-NEXT: .long 1088421824
%x = call <2 x i16> @llvm.fptosi.sat.v2f64.v2i16(<2 x double> %f) %x = call <2 x i16> @llvm.fptosi.sat.v2f64.v2i16(<2 x double> %f)
ret <2 x i16> %x ret <2 x i16> %x
} }
define arm_aapcs_vfpcc <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i19: ; CHECK-LABEL: test_signed_v2f64_v2i19:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #48 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #48 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI36_0 ; CHECK-NEXT: vldr d0, .LCPI36_0
; CHECK-NEXT: vmov r6, r5, d9 ; CHECK-NEXT: vmov r7, r6, d9
; CHECK-NEXT: vmov r8, r3, d0
; CHECK-NEXT: str r3, [sp, #36] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: str.w r8, [sp, #44] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI36_1
; CHECK-NEXT: mov r10, r0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: strd r2, r3, [sp, #16] @ 8-byte Folded Spill
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: str r0, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: cmp.w r11, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r1, #-1
; CHECK-NEXT: cmp.w r10, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: str r5, [sp, #40] @ 4-byte Spill
; CHECK-NEXT: vmov r7, r9, d8
; CHECK-NEXT: mov r5, r6
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: str r4, [sp, #32] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: ldr r4, [sp, #36] @ 4-byte Reload
; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r6, r9
; CHECK-NEXT: str.w r9, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: ldr.w r9, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: ldr.w r8, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r2, r9 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r11, r0 ; CHECK-NEXT: vldr d0, .LCPI36_1
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload ; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r6, r5 ; CHECK-NEXT: vmov r8, r0, d8
; CHECK-NEXT: mov r10, r1 ; CHECK-NEXT: vmov r11, r10, d0
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: clz r0, r4
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: ittt ne
; CHECK-NEXT: movwne r9, #0
; CHECK-NEXT: movtne r9, #65532
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: itt eq ; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: movweq r11, #0 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: movteq r11, #65532 ; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: mov r3, r4 ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: itt ne ; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r11, #65535 ; CHECK-NEXT: movwne r9, #65535
; CHECK-NEXT: movtne r11, #3 ; CHECK-NEXT: movtne r9, #3
; CHECK-NEXT: str r5, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: it ne
; CHECK-NEXT: ldr r5, [sp, #40] @ 4-byte Reload ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: ldr r2, [sp, #44] @ 4-byte Reload ; CHECK-NEXT: ldr r4, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: mov r6, r8
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r4, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r4, #0
; CHECK-NEXT: movteq r4, #65532
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r11, r4
; CHECK-NEXT: lsr.w r10, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: cmp.w r10, #0
; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: itt ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: movtne r4, #65532
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: itt ne ; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r4, #65535 ; CHECK-NEXT: movwne r4, #65535
; CHECK-NEXT: movtne r4, #3 ; CHECK-NEXT: movtne r4, #3
; CHECK-NEXT: ldr r5, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: cmp.w r10, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: ldr r2, [sp, #44] @ 4-byte Reload
; CHECK-NEXT: ldr r3, [sp, #36] @ 4-byte Reload
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r10, #-1
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne.w r7, #-1
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #40] @ 4-byte Reload
; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r0, [sp, #32] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r11, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r9
; CHECK-NEXT: vmov q0[3], q0[1], r10, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r7, r0
; CHECK-NEXT: add sp, #48 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI36_0: ; CHECK-NEXT: .LCPI36_0:
; CHECK-NEXT: .long 0 @ double 262143
; CHECK-NEXT: .long 1091567608
; CHECK-NEXT: .LCPI36_1:
; CHECK-NEXT: .long 0 @ double -262144 ; CHECK-NEXT: .long 0 @ double -262144
; CHECK-NEXT: .long 3239051264 ; CHECK-NEXT: .long 3239051264
; CHECK-NEXT: .LCPI36_1:
; CHECK-NEXT: .long 0 @ double 262143
; CHECK-NEXT: .long 1091567608
%x = call <2 x i19> @llvm.fptosi.sat.v2f64.v2i19(<2 x double> %f) %x = call <2 x i19> @llvm.fptosi.sat.v2f64.v2i19(<2 x double> %f)
ret <2 x i19> %x ret <2 x i19> %x
} }
define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32_duplicate: ; CHECK-LABEL: test_signed_v2f64_v2i32_duplicate:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI37_0 ; CHECK-NEXT: vldr d0, .LCPI37_0
; CHECK-NEXT: vmov r9, r8, d9 ; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r11, r10, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: str.w r11, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: str.w r10, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI37_1
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: vmov r5, r3, d0
; CHECK-NEXT: str r3, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: str r5, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: vldr d0, .LCPI37_1
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r0, #-2147483648
; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r0, #-2147483648 ; CHECK-NEXT: movne.w r11, #-2147483648
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: ldr r5, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r11, #-2147483648
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r2, r7 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r3, r6 ; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r11, #-2147483648 ; CHECK-NEXT: mvnne r11, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: vmov r10, r7, d8
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #1
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0 ; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: ldrd r2, r3, [sp, #20] @ 8-byte Folded Reload ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r5, #-1
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-2147483648
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r5, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #20] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r10, #-1
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r5, r11
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: vmov q0[3], q0[1], r4, r2
; CHECK-NEXT: vmov q0[2], q0[0], r11, r0 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vmov q0[3], q0[1], r10, r5
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI37_0: ; CHECK-NEXT: .LCPI37_0:
; CHECK-NEXT: .long 4290772992 @ double 2147483647
; CHECK-NEXT: .long 1105199103
; CHECK-NEXT: .LCPI37_1:
; CHECK-NEXT: .long 0 @ double -2147483648 ; CHECK-NEXT: .long 0 @ double -2147483648
; CHECK-NEXT: .long 3252682752 ; CHECK-NEXT: .long 3252682752
; CHECK-NEXT: .LCPI37_1:
; CHECK-NEXT: .long 4290772992 @ double 2147483647
; CHECK-NEXT: .long 1105199103
%x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define arm_aapcs_vfpcc <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i50: ; CHECK-LABEL: test_signed_v2f64_v2i50:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI38_0 ; CHECK-NEXT: vldr d0, .LCPI38_0
; CHECK-NEXT: vmov r8, r5, d9 ; CHECK-NEXT: vmov r7, r6, d9
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: str r2, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI38_1
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: vmov r10, r9, d0
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r11, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: cmp.w r11, #0 ; CHECK-NEXT: vldr d0, .LCPI38_1
; CHECK-NEXT: str r1, [sp, #28] @ 4-byte Spill ; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: csel r0, r0, r11, ne ; CHECK-NEXT: vmov r8, r0, d8
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: vmov r11, r10, d0
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: clz r0, r4
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: itt ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: movtne r1, #65534
; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1 ; CHECK-NEXT: movne.w r9, #0
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: vmov r6, r7, d8
; CHECK-NEXT: mov r11, r5
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne r4, #1
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: it ne
; CHECK-NEXT: ldr r5, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: movne.w r9, #-1
; CHECK-NEXT: mov r1, r7 ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: ldr r4, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: itt eq
; CHECK-NEXT: movweq r10, #0
; CHECK-NEXT: movteq r10, #65534
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: itt ne ; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r10, #65535 ; CHECK-NEXT: movwne r5, #65535
; CHECK-NEXT: movtne r10, #1 ; CHECK-NEXT: movtne r5, #1
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: ldr.w r9, [sp, #4] @ 4-byte Reload ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mov r1, r11 ; CHECK-NEXT: it ne
; CHECK-NEXT: mov r5, r11 ; CHECK-NEXT: movne.w r9, #0
; CHECK-NEXT: ldr.w r11, [sp, #8] @ 4-byte Reload ; CHECK-NEXT: ldr r4, [sp] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: mov r2, r11 ; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r0, #0
; CHECK-NEXT: movteq r0, #65534
; CHECK-NEXT: ldr r1, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r0, #65535
; CHECK-NEXT: movtne r0, #1
; CHECK-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: str r0, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: csel r4, r1, r0, ne
; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1 ; CHECK-NEXT: movne r5, #1
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r3, r5 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r11, r4
; CHECK-NEXT: lsr.w r10, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: cmp.w r10, #0
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: movtne r7, #65534
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r7, #65535
; CHECK-NEXT: movtne r7, #1
; CHECK-NEXT: cmp.w r10, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldr r5, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: vmov q0[2], q0[0], r4, r0 ; CHECK-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vmov q0[3], q0[1], r10, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r9
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: vmov q0[3], q0[1], r7, r1
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI38_0: ; CHECK-NEXT: .LCPI38_0:
; CHECK-NEXT: .long 4294967280 @ double 562949953421311
; CHECK-NEXT: .long 1124073471
; CHECK-NEXT: .LCPI38_1:
; CHECK-NEXT: .long 0 @ double -562949953421312 ; CHECK-NEXT: .long 0 @ double -562949953421312
; CHECK-NEXT: .long 3271557120 ; CHECK-NEXT: .long 3271557120
; CHECK-NEXT: .LCPI38_1:
; CHECK-NEXT: .long 4294967280 @ double 562949953421311
; CHECK-NEXT: .long 1124073471
%x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f) %x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f)
ret <2 x i50> %x ret <2 x i50> %x
} }
define arm_aapcs_vfpcc <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i64: ; CHECK-LABEL: test_signed_v2f64_v2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI39_0 ; CHECK-NEXT: vldr d0, .LCPI39_0
; CHECK-NEXT: vmov r8, r5, d9 ; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r11, r3, d0
; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: str.w r11, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI39_1
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: str r2, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r10, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vldr d0, .LCPI39_1
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: cmp.w r10, #0 ; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: csel r0, r0, r10, ne
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5 ; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: str r4, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: ldr.w r10, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: cmp.w r11, #0
; CHECK-NEXT: mov r9, r1
; CHECK-NEXT: csel r11, r0, r11, ne
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: it ne
; CHECK-NEXT: mov r3, r6 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #-1 ; CHECK-NEXT: movne.w r11, #-1
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: vmov r10, r7, d8
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #1
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r11, #0 ; CHECK-NEXT: movne.w r11, #0
; CHECK-NEXT: ldrd r2, r3, [sp, #24] @ 8-byte Folded Reload ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r0, #-2147483648
; CHECK-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r0, #-2147483648 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: mov r10, r0 ; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: ldrd r2, r3, [sp, #24] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r9, #-2147483648
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r7
; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r9, #-2147483648 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r5, r11
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-2147483648
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r2, #-2147483648
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r2, #0
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-2147483648
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r4, #-2147483648
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #0 ; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: vmov q0[3], q0[1], r4, r2
; CHECK-NEXT: vmov q0[2], q0[0], r11, r0 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vmov q0[3], q0[1], r9, r10
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI39_0: ; CHECK-NEXT: .LCPI39_0:
; CHECK-NEXT: .long 4294967295 @ double 9.2233720368547748E+18
; CHECK-NEXT: .long 1138753535
; CHECK-NEXT: .LCPI39_1:
; CHECK-NEXT: .long 0 @ double -9.2233720368547758E+18 ; CHECK-NEXT: .long 0 @ double -9.2233720368547758E+18
; CHECK-NEXT: .long 3286237184 ; CHECK-NEXT: .long 3286237184
; CHECK-NEXT: .LCPI39_1:
; CHECK-NEXT: .long 4294967295 @ double 9.2233720368547748E+18
; CHECK-NEXT: .long 1138753535
%x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f) %x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define arm_aapcs_vfpcc <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i100: ; CHECK-LABEL: test_signed_v2f64_v2i100:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
▲ Show 20 Lines • Show All 2,725 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll

Show First 20 Lines • Show All 322 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_unsigned_v2f64_v2i32: ; CHECK-LABEL: test_unsigned_v2f64_v2i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI9_0 ; CHECK-NEXT: vldr d0, .LCPI9_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI9_1
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: vmov r2, r11, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: vldr d0, .LCPI9_1
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: csel r0, r0, r8, ne ; CHECK-NEXT: vmov r9, r8, d0
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vmov r11, r4, d8
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #-1 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r7, #1
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: it ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r10
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI9_0: ; CHECK-NEXT: .LCPI9_0:
; CHECK-NEXT: .long 4292870144 @ double 4294967295
; CHECK-NEXT: .long 1106247679
; CHECK-NEXT: .LCPI9_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NEXT: .LCPI9_1:
; CHECK-NEXT: .long 4292870144 @ double 4294967295
; CHECK-NEXT: .long 1106247679
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) { define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) {
; CHECK-LABEL: test_unsigned_v3f64_v3i32: ; CHECK-LABEL: test_unsigned_v3f64_v3i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
▲ Show 20 Lines • Show All 1,772 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_unsigned_v2f64_v2i8: ; CHECK-LABEL: test_unsigned_v2f64_v2i8:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI33_0 ; CHECK-NEXT: vldr d0, .LCPI33_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI33_1
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: vmov r2, r11, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: vldr d0, .LCPI33_1
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: csel r0, r0, r8, ne ; CHECK-NEXT: vmov r9, r8, d0
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vmov r11, r4, d8
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #255 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #255 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #255
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r7, #1
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: it ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: movne r0, #255
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r10
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI33_0: ; CHECK-NEXT: .LCPI33_0:
; CHECK-NEXT: .long 0 @ double 255
; CHECK-NEXT: .long 1081073664
; CHECK-NEXT: .LCPI33_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NEXT: .LCPI33_1:
; CHECK-NEXT: .long 0 @ double 255
; CHECK-NEXT: .long 1081073664
%x = call <2 x i8> @llvm.fptoui.sat.v2f64.v2i8(<2 x double> %f) %x = call <2 x i8> @llvm.fptoui.sat.v2f64.v2i8(<2 x double> %f)
ret <2 x i8> %x ret <2 x i8> %x
} }
define arm_aapcs_vfpcc <2 x i13> @test_unsigned_v2f64_v2i13(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i13> @test_unsigned_v2f64_v2i13(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i13: ; CHECK-LABEL: test_unsigned_v2f64_v2i13:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI34_0 ; CHECK-NEXT: vldr d0, .LCPI34_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI34_1
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: vmov r2, r11, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: vldr d0, .LCPI34_1
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: csel r0, r0, r8, ne ; CHECK-NEXT: vmov r9, r8, d0
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vmov r11, r4, d8
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r0, #8191 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r9, #8191 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r5, #8191
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r7, #1
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: it ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: movwne r0, #8191
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r10
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI34_0: ; CHECK-NEXT: .LCPI34_0:
; CHECK-NEXT: .long 0 @ double 8191
; CHECK-NEXT: .long 1086324480
; CHECK-NEXT: .LCPI34_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NEXT: .LCPI34_1:
; CHECK-NEXT: .long 0 @ double 8191
; CHECK-NEXT: .long 1086324480
%x = call <2 x i13> @llvm.fptoui.sat.v2f64.v2i13(<2 x double> %f) %x = call <2 x i13> @llvm.fptoui.sat.v2f64.v2i13(<2 x double> %f)
ret <2 x i13> %x ret <2 x i13> %x
} }
define arm_aapcs_vfpcc <2 x i16> @test_unsigned_v2f64_v2i16(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i16> @test_unsigned_v2f64_v2i16(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i16: ; CHECK-LABEL: test_unsigned_v2f64_v2i16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI35_0 ; CHECK-NEXT: vldr d0, .LCPI35_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI35_1
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: vmov r2, r11, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: vldr d0, .LCPI35_1
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: csel r0, r0, r8, ne ; CHECK-NEXT: vmov r9, r8, d0
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vmov r11, r4, d8
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r0, #65535 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r9, #65535 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r5, #65535
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r7, #1
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: it ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: movwne r0, #65535
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r10
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI35_0: ; CHECK-NEXT: .LCPI35_0:
; CHECK-NEXT: .long 0 @ double 65535
; CHECK-NEXT: .long 1089470432
; CHECK-NEXT: .LCPI35_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NEXT: .LCPI35_1:
; CHECK-NEXT: .long 0 @ double 65535
; CHECK-NEXT: .long 1089470432
%x = call <2 x i16> @llvm.fptoui.sat.v2f64.v2i16(<2 x double> %f) %x = call <2 x i16> @llvm.fptoui.sat.v2f64.v2i16(<2 x double> %f)
ret <2 x i16> %x ret <2 x i16> %x
} }
define arm_aapcs_vfpcc <2 x i19> @test_unsigned_v2f64_v2i19(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i19> @test_unsigned_v2f64_v2i19(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i19: ; CHECK-LABEL: test_unsigned_v2f64_v2i19:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI36_0 ; CHECK-NEXT: vldr d0, .LCPI36_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r11, r10, d8
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI36_1 ; CHECK-NEXT: vldr d0, .LCPI36_1
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: vmov r2, r11, d0 ; CHECK-NEXT: vmov r5, r7, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill ; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: vmov r8, r6, d9
; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #1
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; CHECK-NEXT: csel r0, r0, r8, ne
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r0, #65535
; CHECK-NEXT: movtne r0, #7
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill ; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r9, #0 ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r9, #65535
; CHECK-NEXT: movtne r9, #7
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r5, #65535
; CHECK-NEXT: movtne r5, #7
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: itt ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: movwne r0, #65535
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: movtne r0, #7
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r7
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI36_0: ; CHECK-NEXT: .LCPI36_0:
; CHECK-NEXT: .long 0 @ double 524287 ; CHECK-NEXT: .long 0 @ double 524287
; CHECK-NEXT: .long 1092616188 ; CHECK-NEXT: .long 1092616188
; CHECK-NEXT: .LCPI36_1: ; CHECK-NEXT: .LCPI36_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
%x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f) %x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f)
ret <2 x i19> %x ret <2 x i19> %x
} }
define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i32_duplicate: ; CHECK-LABEL: test_unsigned_v2f64_v2i32_duplicate:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI37_0 ; CHECK-NEXT: vldr d0, .LCPI37_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI37_1
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: vmov r2, r11, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: vldr d0, .LCPI37_1
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: csel r0, r0, r8, ne ; CHECK-NEXT: vmov r9, r8, d0
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vmov r11, r4, d8
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #-1 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: movne r7, #1
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0 ; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: it ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r10
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI37_0: ; CHECK-NEXT: .LCPI37_0:
; CHECK-NEXT: .long 4292870144 @ double 4294967295
; CHECK-NEXT: .long 1106247679
; CHECK-NEXT: .LCPI37_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NEXT: .LCPI37_1:
; CHECK-NEXT: .long 4292870144 @ double 4294967295
; CHECK-NEXT: .long 1106247679
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define arm_aapcs_vfpcc <2 x i50> @test_unsigned_v2f64_v2i50(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i50> @test_unsigned_v2f64_v2i50(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i50: ; CHECK-LABEL: test_unsigned_v2f64_v2i50:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI38_0 ; CHECK-NEXT: vldr d0, .LCPI38_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r11, r10, d8
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r2, r3, [sp, #8] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI38_1 ; CHECK-NEXT: vldr d0, .LCPI38_1
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: vmov r2, r11, d0 ; CHECK-NEXT: vmov r5, r7, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill ; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: vmov r8, r6, d9
; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #1
; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: csel r0, r1, r8, ne
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r0, #65535
; CHECK-NEXT: movtne r0, #3
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r2, r5
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: lsr.w r9, r0, #5
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill ; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: cmp.w r9, #0 ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: csel r9, r1, r9, ne
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r9, #65535
; CHECK-NEXT: movtne r9, #3
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1 ; CHECK-NEXT: movne r7, #0
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r2, r3, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r7, #65535
; CHECK-NEXT: movtne r7, #3
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r1, #65535
; CHECK-NEXT: movtne r1, #3
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1 ; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: vmov q0[3], q0[1], r1, r7
; CHECK-NEXT: vmov q0[3], q0[1], r9, r0 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI38_0: ; CHECK-NEXT: .LCPI38_0:
; CHECK-NEXT: .long 4294967288 @ double 1125899906842623 ; CHECK-NEXT: .long 4294967288 @ double 1125899906842623
; CHECK-NEXT: .long 1125122047 ; CHECK-NEXT: .long 1125122047
; CHECK-NEXT: .LCPI38_1: ; CHECK-NEXT: .LCPI38_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
%x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f) %x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f)
ret <2 x i50> %x ret <2 x i50> %x
} }
define arm_aapcs_vfpcc <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i64: ; CHECK-LABEL: test_unsigned_v2f64_v2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI39_0 ; CHECK-NEXT: vldr d0, .LCPI39_0
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vldr d0, .LCPI39_1
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: vmov r2, r11, d0
; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov r7, r6, d8 ; CHECK-NEXT: vldr d0, .LCPI39_1
; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: csel r0, r0, r8, ne ; CHECK-NEXT: vmov r9, r8, d0
; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: vmov r11, r4, d8
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1 ; CHECK-NEXT: movne r5, #0
; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill ; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: mov r8, r9
; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r3, r11
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: csel r9, r0, r9, ne
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r9, #-1 ; CHECK-NEXT: movne r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: ldr.w r11, [sp, #28] @ 4-byte Reload ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: ldr.w r10, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r5, r1, r0, ne
; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1 ; CHECK-NEXT: movne r7, #1
; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r3, r2, [sp, #4] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: csel r0, r1, r0, ne ; CHECK-NEXT: lsrs r4, r0, #5
; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1 ; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload ; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vmov q0[2], q0[0], r9, r1 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r0, r5 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r10, #-1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: vmov q0[3], q0[1], r1, r10
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI39_0: ; CHECK-NEXT: .LCPI39_0:
; CHECK-NEXT: .long 4294967295 @ double 1.844674407370955E+19
; CHECK-NEXT: .long 1139802111
; CHECK-NEXT: .LCPI39_1:
; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 @ double 0
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NEXT: .LCPI39_1:
; CHECK-NEXT: .long 4294967295 @ double 1.844674407370955E+19
; CHECK-NEXT: .long 1139802111
%x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f) %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x ret <2 x i64> %x
} }
define arm_aapcs_vfpcc <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) { define arm_aapcs_vfpcc <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i100: ; CHECK-LABEL: test_unsigned_v2f64_v2i100:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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llvm/test/CodeGen/X86/fptosi-sat-scalar.ll

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; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movl $61440, %ecx # imm = 0xF000
; X86-X87-NEXT: jb .LBB2_2 ; X86-X87-NEXT: jb .LBB2_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB2_2: ; X86-X87-NEXT: .LBB2_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movl $32768, %ecx # imm = 0x8000
; X86-X87-NEXT: jb .LBB3_2 ; X86-X87-NEXT: jb .LBB3_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB3_2: ; X86-X87-NEXT: .LBB3_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 931 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movl $61440, %ecx # imm = 0xF000
; X86-X87-NEXT: jb .LBB12_2 ; X86-X87-NEXT: jb .LBB12_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB12_2: ; X86-X87-NEXT: .LBB12_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movl $32768, %ecx # imm = 0x8000
; X86-X87-NEXT: jb .LBB13_2 ; X86-X87-NEXT: jb .LBB13_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB13_2: ; X86-X87-NEXT: .LBB13_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 976 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movl $61440, %ecx # imm = 0xF000
; X86-X87-NEXT: jb .LBB22_2 ; X86-X87-NEXT: jb .LBB22_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB22_2: ; X86-X87-NEXT: .LBB22_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movl $32768, %ecx # imm = 0x8000
; X86-X87-NEXT: jb .LBB23_2 ; X86-X87-NEXT: jb .LBB23_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB23_2: ; X86-X87-NEXT: .LBB23_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 1,114 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movl $61440, %ecx # imm = 0xF000
; X86-X87-NEXT: jb .LBB32_2 ; X86-X87-NEXT: jb .LBB32_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB32_2: ; X86-X87-NEXT: .LBB32_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
Show All 24 Lines
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movw $-4096, %ax # imm = 0xF000 ; X86-SSE-NEXT: movl $61440, %ecx # imm = 0xF000
; X86-SSE-NEXT: jb .LBB32_2 ; X86-SSE-NEXT: cmovael %eax, %ecx
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB32_2:
; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $4095, %ecx # imm = 0xFFF ; X86-SSE-NEXT: movl $4095, %edx # imm = 0xFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %ecx, %edx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %edx, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax ; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: addl $8, %esp ; X86-SSE-NEXT: addl $8, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i13_f80: ; X64-LABEL: test_signed_i13_f80:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: fldt {{[0-9]+}}(%rsp) ; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fnstcw -{{[0-9]+}}(%rsp) ; X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax ; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: orl $3072, %eax # imm = 0xC00 ; X64-NEXT: orl $3072, %eax # imm = 0xC00
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp) ; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp) ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: fists -{{[0-9]+}}(%rsp) ; X64-NEXT: fists -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp) ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip) ; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1) ; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st ; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1) ; X64-NEXT: fstp %st(1)
; X64-NEXT: movw $-4096, %ax # imm = 0xF000 ; X64-NEXT: movl $61440, %ecx # imm = 0xF000
; X64-NEXT: jb .LBB32_2 ; X64-NEXT: cmovael %eax, %ecx
; X64-NEXT: # %bb.1:
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: .LBB32_2:
; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip) ; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1) ; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st ; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1) ; X64-NEXT: fstp %st(1)
; X64-NEXT: movl $4095, %ecx # imm = 0xFFF ; X64-NEXT: movl $4095, %edx # imm = 0xFFF
; X64-NEXT: cmovbel %eax, %ecx ; X64-NEXT: cmovbel %ecx, %edx
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: fucompi %st(0), %st ; X64-NEXT: fucompi %st(0), %st
; X64-NEXT: cmovnpl %ecx, %eax ; X64-NEXT: cmovnpl %edx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq ; X64-NEXT: retq
%x = call i13 @llvm.fptosi.sat.i13.f80(x86_fp80 %f) %x = call i13 @llvm.fptosi.sat.i13.f80(x86_fp80 %f)
ret i13 %x ret i13 %x
} }
define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind { define i16 @test_signed_i16_f80(x86_fp80 %f) nounwind {
; X86-X87-LABEL: test_signed_i16_f80: ; X86-X87-LABEL: test_signed_i16_f80:
Show All 9 Lines
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movl $32768, %ecx # imm = 0x8000
; X86-X87-NEXT: jb .LBB33_2 ; X86-X87-NEXT: jb .LBB33_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB33_2: ; X86-X87-NEXT: .LBB33_2:
; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
Show All 24 Lines
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movw $-32768, %ax # imm = 0x8000 ; X86-SSE-NEXT: movl $32768, %ecx # imm = 0x8000
; X86-SSE-NEXT: jb .LBB33_2 ; X86-SSE-NEXT: cmovael %eax, %ecx
; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB33_2:
; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-SSE-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $32767, %ecx # imm = 0x7FFF ; X86-SSE-NEXT: movl $32767, %edx # imm = 0x7FFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %ecx, %edx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %edx, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax ; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: addl $8, %esp ; X86-SSE-NEXT: addl $8, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i16_f80: ; X64-LABEL: test_signed_i16_f80:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: fldt {{[0-9]+}}(%rsp) ; X64-NEXT: fldt {{[0-9]+}}(%rsp)
; X64-NEXT: fnstcw -{{[0-9]+}}(%rsp) ; X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax ; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: orl $3072, %eax # imm = 0xC00 ; X64-NEXT: orl $3072, %eax # imm = 0xC00
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp) ; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp) ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: fists -{{[0-9]+}}(%rsp) ; X64-NEXT: fists -{{[0-9]+}}(%rsp)
; X64-NEXT: fldcw -{{[0-9]+}}(%rsp) ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip) ; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1) ; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st ; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1) ; X64-NEXT: fstp %st(1)
; X64-NEXT: movw $-32768, %ax # imm = 0x8000 ; X64-NEXT: movl $32768, %ecx # imm = 0x8000
; X64-NEXT: jb .LBB33_2 ; X64-NEXT: cmovael %eax, %ecx
; X64-NEXT: # %bb.1:
; X64-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-NEXT: .LBB33_2:
; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip) ; X64-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; X64-NEXT: fxch %st(1) ; X64-NEXT: fxch %st(1)
; X64-NEXT: fucomi %st(1), %st ; X64-NEXT: fucomi %st(1), %st
; X64-NEXT: fstp %st(1) ; X64-NEXT: fstp %st(1)
; X64-NEXT: movl $32767, %ecx # imm = 0x7FFF ; X64-NEXT: movl $32767, %edx # imm = 0x7FFF
; X64-NEXT: cmovbel %eax, %ecx ; X64-NEXT: cmovbel %ecx, %edx
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: fucompi %st(0), %st ; X64-NEXT: fucompi %st(0), %st
; X64-NEXT: cmovnpl %ecx, %eax ; X64-NEXT: cmovnpl %edx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq ; X64-NEXT: retq
%x = call i16 @llvm.fptosi.sat.i16.f80(x86_fp80 %f) %x = call i16 @llvm.fptosi.sat.i16.f80(x86_fp80 %f)
ret i16 %x ret i16 %x
} }
define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind { define i19 @test_signed_i19_f80(x86_fp80 %f) nounwind {
; X86-X87-LABEL: test_signed_i19_f80: ; X86-X87-LABEL: test_signed_i19_f80:
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