[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops

[luke]

Summary

If we have a load/store with an illegal fixed length vector result type that
needs widened, e.g. x:v6i32 = load p
Instead of just widening it to: x:v8i32 = load p
We can widen it to the equivalent VP operation and set the EVL to the
exact number of elements needed: x:v8i32 = vp_load a, b, mask=true, evl=6
Provided that the target supports vp_load/vp_store on the widened type.

Scalable vectors are already widened this way where possible, so this
largely reuses the same logic.

[frasercrmck]

Sorry, dropped the ball on this. The code looks good to me.

I wonder if someone with a better sense of architectural performance can say this is likely to be faster? Fetching/writing less memory must be good, right? On top of that we're doing fewer vector extracts so fewer instructions in general.

[craig.topper]

I also dropped the ball on this. Will try to review for real after I sleep.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

6266

Can we use SelectionDAG::getElementCount?

[luke]

No worries, I've also dropped the ball on this too. I've left some comments on the child patch D148523 from the last time I looked at it, and the gist is that I don't think that patch makes as much sense as this one anymore.

[luke]

Rebase and use SelectionDAG::getElementCount

[luke]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

65

We lose this optimisation because we're no longer scalarizing the vector loads and stores. Can we add a combine for (store p, (insertelt x, (load p))?

[craig.topper]

LGTM

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
   if (!LD->getMemoryVT().isByteSized()) {
     SDValue Value, NewChain;
     std::tie(Value, NewChain) = TLI.scalarizeVectorLoad(LD, DAG);
     ReplaceValueWith(SDValue(LD, 0), Value);
     ReplaceValueWith(SDValue(LD, 1), NewChain);
     return SDValue();
   }
 
-  SDValue Result;
-  SmallVector<SDValue, 16> LdChain;  // Chain for the series of load
-  if (ExtType != ISD::NON_EXTLOAD)
-    Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
-  else
-    Result = GenWidenVectorLoads(LdChain, LD);
-
-  if (Result) {
-    // If we generate a single load, we can use that for the chain.  Otherwise,
-    // build a factor node to remember the multiple loads are independent and
-    // chain to that.
-    SDValue NewChain;
-    if (LdChain.size() == 1)
-      NewChain = LdChain[0];
-    else
-      NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
-
-    // Modified the chain - switch anything that used the old chain to use
-    // the new one.
-    ReplaceValueWith(SDValue(N, 1), NewChain);
-
-    return Result;
-  }
-
   // Generate a vector-predicated load if it is custom/legal on the target. To
   // avoid possible recursion, only do this if the widened mask type is legal.
   // FIXME: Not all targets may support EVL in VP_LOAD. These will have been
   // removed from the IR by the ExpandVectorPredication pass but we're
   // reintroducing them here.
   EVT LdVT = LD->getMemoryVT();
   EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), LdVT);
   EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
                                     WideVT.getVectorElementCount());
-  if (ExtType == ISD::NON_EXTLOAD && WideVT.isScalableVector() &&
+  if (ExtType == ISD::NON_EXTLOAD &&
       TLI.isOperationLegalOrCustom(ISD::VP_LOAD, WideVT) &&
       TLI.isTypeLegal(WideMaskVT)) {
     SDLoc DL(N);
     SDValue Mask = DAG.getAllOnesConstant(DL, WideMaskVT);
     MVT EVLVT = TLI.getVPExplicitVectorLengthTy();
     unsigned NumVTElts = LdVT.getVectorMinNumElements();
-    SDValue EVL =
-        DAG.getVScale(DL, EVLVT, APInt(EVLVT.getScalarSizeInBits(), NumVTElts));
+    SDValue EVL;
+    if (LdVT.isScalableVector())
+      EVL = DAG.getVScale(DL, EVLVT,
+                          APInt(EVLVT.getScalarSizeInBits(), NumVTElts));
+    else
+      EVL = DAG.getConstant(NumVTElts, DL, EVLVT);
     const auto *MMO = LD->getMemOperand();
     SDValue NewLoad =
         DAG.getLoadVP(WideVT, DL, LD->getChain(), LD->getBasePtr(), Mask, EVL,
                       MMO->getPointerInfo(), MMO->getAlign(), MMO->getFlags(),
                       MMO->getAAInfo());
 
     // Modified the chain - switch anything that used the old chain to use
     // the new one.
     ReplaceValueWith(SDValue(N, 1), NewLoad.getValue(1));
 
     return NewLoad;
   }
 
+  SDValue Result;
+  SmallVector<SDValue, 16> LdChain; // Chain for the series of load
+  if (ExtType != ISD::NON_EXTLOAD)
+    Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
+  else
+    Result = GenWidenVectorLoads(LdChain, LD);
+
+  if (Result) {
+    // If we generate a single load, we can use that for the chain.  Otherwise,
+    // build a factor node to remember the multiple loads are independent and
+    // chain to that.
+    SDValue NewChain;
+    if (LdChain.size() == 1)
+      NewChain = LdChain[0];
+    else
+      NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
+
+    // Modified the chain - switch anything that used the old chain to use
+    // the new one.
+    ReplaceValueWith(SDValue(N, 1), NewChain);
+
+    return Result;
+  }
+
   report_fatal_error("Unable to widen vector load");
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_VP_LOAD(VPLoadSDNode *N) {
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue Mask = N->getMask();
   SDValue EVL = N->getVectorLength();
   ISD::LoadExtType ExtType = N->getExtensionType();
SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
   StoreSDNode *ST = cast<StoreSDNode>(N);
 
   if (!ST->getMemoryVT().getScalarType().isByteSized())
     return TLI.scalarizeVectorStore(ST, DAG);
 
   if (ST->isTruncatingStore())
     return TLI.scalarizeVectorStore(ST, DAG);
 
-  SmallVector<SDValue, 16> StChain;
-  if (GenWidenVectorStores(StChain, ST)) {
-    if (StChain.size() == 1)
-      return StChain[0];
-
-    return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
-  }
-
   // Generate a vector-predicated store if it is custom/legal on the target.
   // To avoid possible recursion, only do this if the widened mask type is
   // legal.
   // FIXME: Not all targets may support EVL in VP_STORE. These will have been
   // removed from the IR by the ExpandVectorPredication pass but we're
   // reintroducing them here.
   SDValue StVal = ST->getValue();
   EVT StVT = StVal.getValueType();
   EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), StVT);
   EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
                                     WideVT.getVectorElementCount());
-  if (WideVT.isScalableVector() &&
-      TLI.isOperationLegalOrCustom(ISD::VP_STORE, WideVT) &&
+
+  if (TLI.isOperationLegalOrCustom(ISD::VP_STORE, WideVT) &&
       TLI.isTypeLegal(WideMaskVT)) {
     // Widen the value.
     SDLoc DL(N);
     StVal = GetWidenedVector(StVal);
     SDValue Mask = DAG.getAllOnesConstant(DL, WideMaskVT);
     MVT EVLVT = TLI.getVPExplicitVectorLengthTy();
     unsigned NumVTElts = StVT.getVectorMinNumElements();
-    SDValue EVL =
-        DAG.getVScale(DL, EVLVT, APInt(EVLVT.getScalarSizeInBits(), NumVTElts));
+    SDValue EVL;
+    if (StVT.isScalableVector())
+      EVL = DAG.getVScale(DL, EVLVT,
+                          APInt(EVLVT.getScalarSizeInBits(), NumVTElts));
+    else
+      EVL = DAG.getConstant(NumVTElts, DL, EVLVT);
     return DAG.getStoreVP(ST->getChain(), DL, StVal, ST->getBasePtr(),
                           DAG.getUNDEF(ST->getBasePtr().getValueType()), Mask,
-                          EVL, StVal.getValueType(), ST->getMemOperand(),
+                          EVL, StVT, ST->getMemOperand(),
                           ST->getAddressingMode());
   }
 
+  SmallVector<SDValue, 16> StChain;
+  if (GenWidenVectorStores(StChain, ST)) {
+    if (StChain.size() == 1)
+      return StChain[0];
+
+    return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
+  }
+
   report_fatal_error("Unable to widen vector store");
 }
 
 SDValue DAGTypeLegalizer::WidenVecOp_VP_STORE(SDNode *N, unsigned OpNo) {
   assert((OpNo == 1 || OpNo == 3) &&
          "Can widen only data or mask operand of vp_store");
   VPStoreSDNode *ST = cast<VPStoreSDNode>(N);
   SDValue Mask = ST->getMask();

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false)
   store <8 x i16> %b, ptr %x
   ret void
 }
 declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
 
 define void @abs_v6i16(ptr %x) {
-; LMULMAX1-RV32-LABEL: abs_v6i16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vrsub.vi v9, v8, 0
-; LMULMAX1-RV32-NEXT:    vmax.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: abs_v6i16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vrsub.vi v9, v8, 0
-; LMULMAX1-RV64-NEXT:    vmax.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: abs_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vrsub.vi v9, v8, 0
+; CHECK-NEXT:    vmax.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = call <6 x i16> @llvm.abs.v6i16(<6 x i16> %a, i1 false)
   store <6 x i16> %b, ptr %x
   ret void
 }
 declare <6 x i16> @llvm.abs.v6i16(<6 x i16>, i1)
 
 define void @abs_v4i32(ptr %x) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

 
 ; This uses a non-power of 2 type so that it isn't an MVT to catch an
 ; incorrect use of getSimpleValueType().
 ; NOTE: Type legalization is bitcasting to vXi32 and doing 2 independent
 ; slidedowns and extracts.
 define i64 @extractelt_v3i64(ptr %x) nounwind {
 ; RV32-LABEL: extractelt_v3i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT:    vle32.v v8, (a0)
+; RV32-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
+; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
 ; RV32-NEXT:    vslidedown.vi v10, v8, 4
 ; RV32-NEXT:    vmv.x.s a0, v10
 ; RV32-NEXT:    vslidedown.vi v8, v8, 5
 ; RV32-NEXT:    vmv.x.s a1, v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v3i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
 ; RV64-NEXT:    vslidedown.vi v8, v8, 2
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %a = load <3 x i64>, ptr %x
   %b = extractelement <3 x i64> %a, i32 2
   ret i64 %b

 
 ; This uses a non-power of 2 type so that it isn't an MVT to catch an
 ; incorrect use of getSimpleValueType_idx(, i32 zeroext %idx).
 ; NOTE: Type legalization is bitcasting to vXi32 and doing 2 independent
 ; slidedowns and extracts.
 define i64 @extractelt_v3i64_idx(ptr %x, i32 zeroext %idx) nounwind {
 ; RV32-LABEL: extractelt_v3i64_idx:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
 ; RV32-NEXT:    vle64.v v8, (a0)
+; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV32-NEXT:    vadd.vv v8, v8, v8
 ; RV32-NEXT:    add a1, a1, a1
 ; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
 ; RV32-NEXT:    vslidedown.vx v10, v8, a1
 ; RV32-NEXT:    vmv.x.s a0, v10
 ; RV32-NEXT:    addi a1, a1, 1
 ; RV32-NEXT:    vslidedown.vx v8, v8, a1
 ; RV32-NEXT:    vmv.x.s a1, v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v3i64_idx:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
 ; RV64-NEXT:    vle64.v v8, (a0)
+; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV64-NEXT:    vadd.vv v8, v8, v8
 ; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
 ; RV64-NEXT:    vslidedown.vx v8, v8, a1
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
   %a = load <3 x i64>, ptr %x
   %b = add <3 x i64> %a, %a
   %c = extractelement <3 x i64> %b, i32 %idx

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = load <8 x half>, ptr %y
   %c = fadd <8 x half> %a, %b
   store <8 x half> %c, ptr %x
   ret void
 }
 
 define void @fadd_v6f16(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: fadd_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfadd.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fadd_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfadd.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fadd_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = fadd <6 x half> %a, %b
   store <6 x half> %c, ptr %x
   ret void
 }
 
 define void @fadd_v4f32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = load <8 x half>, ptr %y
   %c = fsub <8 x half> %a, %b
   store <8 x half> %c, ptr %x
   ret void
 }
 
 define void @fsub_v6f16(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: fsub_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfsub.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fsub_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfsub.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fsub_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfsub.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = fsub <6 x half> %a, %b
   store <6 x half> %c, ptr %x
   ret void
 }
 
 define void @fsub_v4f32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = load <8 x half>, ptr %y
   %c = fmul <8 x half> %a, %b
   store <8 x half> %c, ptr %x
   ret void
 }
 
 define void @fmul_v6f16(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: fmul_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfmul.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmul_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfmul.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmul_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmul.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = fmul <6 x half> %a, %b
   store <6 x half> %c, ptr %x
   ret void
 }
 
 define void @fmul_v4f32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = load <8 x half>, ptr %y
   %c = fdiv <8 x half> %a, %b
   store <8 x half> %c, ptr %x
   ret void
 }
 
 define void @fdiv_v6f16(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: fdiv_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfdiv.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fdiv_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfdiv.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fdiv_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfdiv.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = fdiv <6 x half> %a, %b
   store <6 x half> %c, ptr %x
   ret void
 }
 
 define void @fdiv_v4f32(ptr %x, ptr %y) {

 ; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = fneg <8 x half> %a
   store <8 x half> %b, ptr %x
   ret void
 }
 
 define void @fneg_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: fneg_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfneg.v v8, v8
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fneg_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfneg.v v8, v8
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fneg_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfneg.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = fneg <6 x half> %a
   store <6 x half> %b, ptr %x
   ret void
 }
 
 define void @fneg_v4f32(ptr %x) {
 ; CHECK-LABEL: fneg_v4f32:
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
   ret void
 }
 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
 
 define void @fabs_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: fabs_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfabs.v v8, v8
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fabs_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfabs.v v8, v8
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fabs_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.fabs.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x
   ret void
 }
 declare <6 x half> @llvm.fabs.v6f16(<6 x half>)
 
 define void @fabs_v4f32(ptr %x) {
; CHECK-NEXT:    ret
   %b = load <8 x half>, ptr %y
   %c = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)
   store <8 x half> %c, ptr %x
   ret void
 }
 declare <8 x half> @llvm.copysign.v8f16(<8 x half>, <8 x half>)
 
 define void @copysign_v6f16(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: copysign_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfsgnj.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: copysign_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfsgnj.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: copysign_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfsgnj.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = call <6 x half> @llvm.copysign.v6f16(<6 x half> %a, <6 x half> %b)
   store <6 x half> %c, ptr %x
   ret void
 }
 declare <6 x half> @llvm.copysign.v6f16(<6 x half>, <6 x half>)
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %c)
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @copysign_vf_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: copysign_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfsgnj.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: copysign_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfsgnj.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: copysign_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfsgnj.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = call <6 x half> @llvm.copysign.v6f16(<6 x half> %a, <6 x half> %c)
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = load <8 x half>, ptr %y
   %c = fneg <8 x half> %b
   %d = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %c)
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @copysign_neg_v6f16(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: copysign_neg_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfsgnjn.vv v8, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: copysign_neg_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfsgnjn.vv v8, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: copysign_neg_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfsgnjn.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = fneg <6 x half> %b
   %d = call <6 x half> @llvm.copysign.v6f16(<6 x half> %a, <6 x half> %c)
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %d = fptrunc <4 x float> %c to <4 x half>
   %e = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %d)
   store <4 x half> %e, ptr %x
   ret void
 }
 declare <4 x half> @llvm.copysign.v4f16(<4 x half>, <4 x half>)
 
 define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
-; LMULMAX1-RV32-LABEL: copysign_neg_trunc_v3f16_v3f32:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vle32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a0)
-; LMULMAX1-RV32-NEXT:    vfncvt.f.f.w v10, v8
-; LMULMAX1-RV32-NEXT:    vfsgnjn.vv v8, v9, v10
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 4
-; LMULMAX1-RV32-NEXT:    vse16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: copysign_neg_trunc_v3f16_v3f32:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV64-NEXT:    vle32.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfncvt.f.f.w v10, v9
-; LMULMAX1-RV64-NEXT:    vfsgnjn.vv v8, v8, v10
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a1, a0, 4
-; LMULMAX1-RV64-NEXT:    vse16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: copysign_neg_trunc_v3f16_v3f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 3, e16, mf2, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vle16.v v9, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vfncvt.f.f.w v10, v8
+; CHECK-NEXT:    vfsgnjn.vv v8, v9, v10
+; CHECK-NEXT:    vsetivli zero, 3, e16, mf2, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <3 x half>, ptr %x
   %b = load <3 x float>, ptr %y
   %c = fneg <3 x float> %b
   %d = fptrunc <3 x float> %c to <3 x half>
   %e = call <3 x half> @llvm.copysign.v3f16(<3 x half> %a, <3 x half> %d)
   store <3 x half> %e, ptr %x
   ret void
 }
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
   ret void
 }
 declare <8 x half> @llvm.sqrt.v8f16(<8 x half>)
 
 define void @sqrt_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: sqrt_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfsqrt.v v8, v8
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: sqrt_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfsqrt.v v8, v8
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: sqrt_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfsqrt.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.sqrt.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x
   ret void
 }
 declare <6 x half> @llvm.sqrt.v6f16(<6 x half>)
 
 define void @sqrt_v4f32(ptr %x) {
; CHECK-NEXT:    ret
   %c = load <8 x half>, ptr %z
   %d = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)
   store <8 x half> %d, ptr %x
   ret void
 }
 declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
 
 define void @fma_v6f16(ptr %x, ptr %y, ptr %z) {
-; LMULMAX1-RV32-LABEL: fma_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV32-NEXT:    vfmacc.vv v10, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v10, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fma_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV64-NEXT:    vfmacc.vv v10, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v10, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fma_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vle16.v v10, (a2)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmacc.vv v10, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v10, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = load <6 x half>, ptr %z
   %d = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %c)
   store <6 x half> %d, ptr %x
   ret void
 }
 declare <6 x half> @llvm.fma.v6f16(<6 x half>, <6 x half>, <6 x half>)
; CHECK-NEXT:    ret
   %c = load <8 x half>, ptr %z
   %neg = fneg <8 x half> %c
   %d = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %neg)
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fmsub_v6f16(ptr %x, ptr %y, ptr %z) {
-; LMULMAX1-RV32-LABEL: fmsub_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV32-NEXT:    vfmsac.vv v10, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v10, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmsub_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV64-NEXT:    vfmsac.vv v10, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v10, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmsub_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vle16.v v10, (a2)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmsac.vv v10, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v10, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = load <6 x half>, ptr %z
   %neg = fneg <6 x half> %c
   %d = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %neg)
   store <6 x half> %d, ptr %x
   ret void
 }
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fadd <8 x half> %a, %c
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fadd_vf_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fadd_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfadd.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fadd_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfadd.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fadd_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfadd.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fadd <6 x half> %a, %c
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fadd <8 x half> %c, %a
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fadd_fv_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fadd_fv_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfadd.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fadd_fv_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfadd.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fadd_fv_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfadd.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fadd <6 x half> %c, %a
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fsub <8 x half> %a, %c
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fsub_vf_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fsub_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfsub.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fsub_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfsub.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fsub_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfsub.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fsub <6 x half> %a, %c
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fsub <8 x half> %c, %a
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fsub_fv_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fsub_fv_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfrsub.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fsub_fv_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfrsub.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fsub_fv_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fsub <6 x half> %c, %a
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fmul <8 x half> %a, %c
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fmul_vf_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fmul_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfmul.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmul_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfmul.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmul_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmul.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fmul <6 x half> %a, %c
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fmul <8 x half> %c, %a
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fmul_fv_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fmul_fv_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfmul.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmul_fv_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfmul.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmul_fv_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmul.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fmul <6 x half> %c, %a
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fdiv <8 x half> %a, %c
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fdiv_vf_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fdiv_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfdiv.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fdiv_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfdiv.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fdiv_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfdiv.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fdiv <6 x half> %a, %c
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <8 x half> poison, half %y, i32 0
   %c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
   %d = fdiv <8 x half> %c, %a
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fdiv_fv_v6f16(ptr %x, half %y) {
-; LMULMAX1-RV32-LABEL: fdiv_fv_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vfrdiv.vf v8, v8, fa0
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fdiv_fv_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vfrdiv.vf v8, v8, fa0
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fdiv_fv_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfrdiv.vf v8, v8, fa0
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = insertelement <6 x half> poison, half %y, i32 0
   %c = shufflevector <6 x half> %b, <6 x half> poison, <6 x i32> zeroinitializer
   %d = fdiv <6 x half> %c, %a
   store <6 x half> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %c = insertelement <8 x half> poison, half %z, i32 0
   %d = shufflevector <8 x half> %c, <8 x half> poison, <8 x i32> zeroinitializer
   %e = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %d, <8 x half> %b)
   store <8 x half> %e, ptr %x
   ret void
 }
 
 define void @fma_vf_v6f16(ptr %x, ptr %y, half %z) {
-; LMULMAX1-RV32-LABEL: fma_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfmacc.vf v9, fa0, v8
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v9, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v9, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fma_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfmacc.vf v9, fa0, v8
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v9, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v9, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fma_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmacc.vf v9, fa0, v8
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v9, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = insertelement <6 x half> poison, half %z, i32 0
   %d = shufflevector <6 x half> %c, <6 x half> poison, <6 x i32> zeroinitializer
   %e = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %d, <6 x half> %b)
   store <6 x half> %e, ptr %x
   ret void
 }
; CHECK-NEXT:    ret
   %c = insertelement <8 x half> poison, half %z, i32 0
   %d = shufflevector <8 x half> %c, <8 x half> poison, <8 x i32> zeroinitializer
   %e = call <8 x half> @llvm.fma.v8f16(<8 x half> %d, <8 x half> %a, <8 x half> %b)
   store <8 x half> %e, ptr %x
   ret void
 }
 
 define void @fma_fv_v6f16(ptr %x, ptr %y, half %z) {
-; LMULMAX1-RV32-LABEL: fma_fv_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfmacc.vf v9, fa0, v8
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v9, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v9, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fma_fv_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfmacc.vf v9, fa0, v8
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v9, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v9, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fma_fv_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmacc.vf v9, fa0, v8
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v9, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = insertelement <6 x half> poison, half %z, i32 0
   %d = shufflevector <6 x half> %c, <6 x half> poison, <6 x i32> zeroinitializer
   %e = call <6 x half> @llvm.fma.v6f16(<6 x half> %d, <6 x half> %a, <6 x half> %b)
   store <6 x half> %e, ptr %x
   ret void
 }
; CHECK-NEXT:    ret
   %d = shufflevector <8 x half> %c, <8 x half> poison, <8 x i32> zeroinitializer
   %neg = fneg <8 x half> %b
   %e = call <8 x half> @llvm.fma.v8f16(<8 x half> %a, <8 x half> %d, <8 x half> %neg)
   store <8 x half> %e, ptr %x
   ret void
 }
 
 define void @fmsub_vf_v6f16(ptr %x, ptr %y, half %z) {
-; LMULMAX1-RV32-LABEL: fmsub_vf_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vfmsac.vf v9, fa0, v8
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v9, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v9, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmsub_vf_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vfmsac.vf v9, fa0, v8
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v9, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v9, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmsub_vf_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmsac.vf v9, fa0, v8
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v9, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = insertelement <6 x half> poison, half %z, i32 0
   %d = shufflevector <6 x half> %c, <6 x half> poison, <6 x i32> zeroinitializer
   %neg = fneg <6 x half> %b
   %e = call <6 x half> @llvm.fma.v6f16(<6 x half> %a, <6 x half> %d, <6 x half> %neg)
   store <6 x half> %e, ptr %x
   ret void
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
   ret void
 }
 declare <8 x half> @llvm.trunc.v8f16(<8 x half>)
 
 define void @trunc_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: trunc_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    lui a1, %hi(.LCPI116_0)
-; LMULMAX1-RV32-NEXT:    flh fa5, %lo(.LCPI116_0)(a1)
-; LMULMAX1-RV32-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV32-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV32-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: trunc_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    lui a1, %hi(.LCPI116_0)
-; LMULMAX1-RV64-NEXT:    flh fa5, %lo(.LCPI116_0)(a1)
-; LMULMAX1-RV64-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV64-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV64-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: trunc_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    lui a1, %hi(.LCPI116_0)
+; CHECK-NEXT:    flh fa5, %lo(.LCPI116_0)(a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v9, v8
+; CHECK-NEXT:    vmflt.vf v0, v9, fa5
+; CHECK-NEXT:    vfcvt.rtz.x.f.v v9, v8, v0.t
+; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.trunc.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x
   ret void
 }
 declare <6 x half> @llvm.trunc.v6f16(<6 x half>)
 
 define void @trunc_v4f32(ptr %x) {
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
   ret void
 }
 declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
 
 define void @ceil_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: ceil_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    lui a1, %hi(.LCPI120_0)
-; LMULMAX1-RV32-NEXT:    flh fa5, %lo(.LCPI120_0)(a1)
-; LMULMAX1-RV32-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV32-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV32-NEXT:    fsrmi a1, 3
-; LMULMAX1-RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    fsrm a1
-; LMULMAX1-RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: ceil_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    lui a1, %hi(.LCPI120_0)
-; LMULMAX1-RV64-NEXT:    flh fa5, %lo(.LCPI120_0)(a1)
-; LMULMAX1-RV64-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV64-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV64-NEXT:    fsrmi a1, 3
-; LMULMAX1-RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    fsrm a1
-; LMULMAX1-RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: ceil_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    lui a1, %hi(.LCPI120_0)
+; CHECK-NEXT:    flh fa5, %lo(.LCPI120_0)(a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v9, v8
+; CHECK-NEXT:    vmflt.vf v0, v9, fa5
+; CHECK-NEXT:    fsrmi a1, 3
+; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT:    fsrm a1
+; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.ceil.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x
   ret void
 }
 declare <6 x half> @llvm.ceil.v6f16(<6 x half>)
 
 define void @ceil_v4f32(ptr %x) {
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
   ret void
 }
 declare <8 x half> @llvm.floor.v8f16(<8 x half>)
 
 define void @floor_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: floor_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    lui a1, %hi(.LCPI124_0)
-; LMULMAX1-RV32-NEXT:    flh fa5, %lo(.LCPI124_0)(a1)
-; LMULMAX1-RV32-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV32-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV32-NEXT:    fsrmi a1, 2
-; LMULMAX1-RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    fsrm a1
-; LMULMAX1-RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: floor_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    lui a1, %hi(.LCPI124_0)
-; LMULMAX1-RV64-NEXT:    flh fa5, %lo(.LCPI124_0)(a1)
-; LMULMAX1-RV64-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV64-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV64-NEXT:    fsrmi a1, 2
-; LMULMAX1-RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    fsrm a1
-; LMULMAX1-RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: floor_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    lui a1, %hi(.LCPI124_0)
+; CHECK-NEXT:    flh fa5, %lo(.LCPI124_0)(a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v9, v8
+; CHECK-NEXT:    vmflt.vf v0, v9, fa5
+; CHECK-NEXT:    fsrmi a1, 2
+; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT:    fsrm a1
+; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.floor.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x
   ret void
 }
 declare <6 x half> @llvm.floor.v6f16(<6 x half>)
 
 define void @floor_v4f32(ptr %x) {
; CHECK-NEXT:    ret
   %a = load <8 x half>, ptr %x
   %b = call <8 x half> @llvm.round.v8f16(<8 x half> %a)
   store <8 x half> %b, ptr %x
   ret void
 }
 declare <8 x half> @llvm.round.v8f16(<8 x half>)
 
 define void @round_v6f16(ptr %x) {
-; LMULMAX1-RV32-LABEL: round_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    lui a1, %hi(.LCPI128_0)
-; LMULMAX1-RV32-NEXT:    flh fa5, %lo(.LCPI128_0)(a1)
-; LMULMAX1-RV32-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV32-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV32-NEXT:    fsrmi a1, 4
-; LMULMAX1-RV32-NEXT:    vfcvt.x.f.v v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    fsrm a1
-; LMULMAX1-RV32-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV32-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: round_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    lui a1, %hi(.LCPI128_0)
-; LMULMAX1-RV64-NEXT:    flh fa5, %lo(.LCPI128_0)(a1)
-; LMULMAX1-RV64-NEXT:    vfabs.v v9, v8
-; LMULMAX1-RV64-NEXT:    vmflt.vf v0, v9, fa5
-; LMULMAX1-RV64-NEXT:    fsrmi a1, 4
-; LMULMAX1-RV64-NEXT:    vfcvt.x.f.v v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    fsrm a1
-; LMULMAX1-RV64-NEXT:    vfcvt.f.x.v v9, v9, v0.t
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
-; LMULMAX1-RV64-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v8, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: round_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    lui a1, %hi(.LCPI128_0)
+; CHECK-NEXT:    flh fa5, %lo(.LCPI128_0)(a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v9, v8
+; CHECK-NEXT:    vmflt.vf v0, v9, fa5
+; CHECK-NEXT:    fsrmi a1, 4
+; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT:    fsrm a1
+; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = call <6 x half> @llvm.round.v6f16(<6 x half> %a)
   store <6 x half> %b, ptr %x
   ret void
 }
 declare <6 x half> @llvm.round.v6f16(<6 x half>)
 
 define void @round_v4f32(ptr %x) {
; CHECK-NEXT:    ret
   %c = load <8 x half>, ptr %z
   %d = call <8 x half> @llvm.fmuladd.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)
   store <8 x half> %d, ptr %x
   ret void
 }
 declare <8 x half> @llvm.fmuladd.v8f16(<8 x half>, <8 x half>, <8 x half>)
 
 define void @fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
-; LMULMAX1-RV32-LABEL: fmuladd_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV32-NEXT:    vfmacc.vv v10, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v10, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmuladd_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV64-NEXT:    vfmacc.vv v10, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v10, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmuladd_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vle16.v v10, (a2)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmacc.vv v10, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v10, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = load <6 x half>, ptr %z
   %d = call <6 x half> @llvm.fmuladd.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %c)
   store <6 x half> %d, ptr %x
   ret void
 }
 declare <6 x half> @llvm.fmuladd.v6f16(<6 x half>, <6 x half>, <6 x half>)
; CHECK-NEXT:    ret
   %c = load <8 x half>, ptr %z
   %neg = fneg <8 x half> %c
   %d = call <8 x half> @llvm.fmuladd.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %neg)
   store <8 x half> %d, ptr %x
   ret void
 }
 
 define void @fmsub_fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
-; LMULMAX1-RV32-LABEL: fmsub_fmuladd_v6f16:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV32-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV32-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV32-NEXT:    vfmsac.vv v10, v8, v9
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV32-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV32-NEXT:    addi a1, a0, 8
-; LMULMAX1-RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; LMULMAX1-RV32-NEXT:    vse16.v v10, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: fmsub_fmuladd_v6f16:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle16.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vle16.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vle16.v v10, (a2)
-; LMULMAX1-RV64-NEXT:    vfmsac.vv v10, v8, v9
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vse64.v v10, (a0)
-; LMULMAX1-RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vslidedown.vi v8, v10, 2
-; LMULMAX1-RV64-NEXT:    addi a0, a0, 8
-; LMULMAX1-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: fmsub_fmuladd_v6f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vle16.v v10, (a2)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vfmsac.vv v10, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v10, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x half>, ptr %x
   %b = load <6 x half>, ptr %y
   %c = load <6 x half>, ptr %z
   %neg = fneg <6 x half> %c
   %d = call <6 x half> @llvm.fmuladd.v6f16(<6 x half> %a, <6 x half> %b, <6 x half> %neg)
   store <6 x half> %d, ptr %x
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

 ; CHECK-NEXT:    vand.vi v8, v9, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
   %z = fptoui <2 x float> %x to <2 x i1>
   ret <2 x i1> %z
 }
 
 define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
-; LMULMAX8RV32-LABEL: fp2si_v3f32_v3i32:
-; LMULMAX8RV32:       # %bb.0:
-; LMULMAX8RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV32-NEXT:    vfcvt.rtz.x.f.v v8, v8
-; LMULMAX8RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV32-NEXT:    addi a0, a1, 8
-; LMULMAX8RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX8RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX8RV32-NEXT:    ret
-;
-; LMULMAX8RV64-LABEL: fp2si_v3f32_v3i32:
-; LMULMAX8RV64:       # %bb.0:
-; LMULMAX8RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV64-NEXT:    vfcvt.rtz.x.f.v v8, v8
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV64-NEXT:    addi a0, a1, 8
-; LMULMAX8RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX8RV64-NEXT:    ret
-;
-; LMULMAX1RV32-LABEL: fp2si_v3f32_v3i32:
-; LMULMAX1RV32:       # %bb.0:
-; LMULMAX1RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV32-NEXT:    vfcvt.rtz.x.f.v v8, v8
-; LMULMAX1RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV32-NEXT:    addi a0, a1, 8
-; LMULMAX1RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX1RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1RV32-NEXT:    ret
-;
-; LMULMAX1RV64-LABEL: fp2si_v3f32_v3i32:
-; LMULMAX1RV64:       # %bb.0:
-; LMULMAX1RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV64-NEXT:    vfcvt.rtz.x.f.v v8, v8
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV64-NEXT:    addi a0, a1, 8
-; LMULMAX1RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX1RV64-NEXT:    ret
+; CHECK-LABEL: fp2si_v3f32_v3i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfcvt.rtz.x.f.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vse32.v v8, (a1)
+; CHECK-NEXT:    ret
   %a = load <3 x float>, ptr %x
   %d = fptosi <3 x float> %a to <3 x i32>
   store <3 x i32> %d, ptr %y
   ret void
 }
 
 define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
-; LMULMAX8RV32-LABEL: fp2ui_v3f32_v3i32:
-; LMULMAX8RV32:       # %bb.0:
-; LMULMAX8RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV32-NEXT:    vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX8RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV32-NEXT:    addi a0, a1, 8
-; LMULMAX8RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX8RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX8RV32-NEXT:    ret
-;
-; LMULMAX8RV64-LABEL: fp2ui_v3f32_v3i32:
-; LMULMAX8RV64:       # %bb.0:
-; LMULMAX8RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV64-NEXT:    vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV64-NEXT:    addi a0, a1, 8
-; LMULMAX8RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX8RV64-NEXT:    ret
-;
-; LMULMAX1RV32-LABEL: fp2ui_v3f32_v3i32:
-; LMULMAX1RV32:       # %bb.0:
-; LMULMAX1RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV32-NEXT:    vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX1RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV32-NEXT:    addi a0, a1, 8
-; LMULMAX1RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX1RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1RV32-NEXT:    ret
-;
-; LMULMAX1RV64-LABEL: fp2ui_v3f32_v3i32:
-; LMULMAX1RV64:       # %bb.0:
-; LMULMAX1RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV64-NEXT:    vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV64-NEXT:    addi a0, a1, 8
-; LMULMAX1RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX1RV64-NEXT:    ret
+; CHECK-LABEL: fp2ui_v3f32_v3i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vse32.v v8, (a1)
+; CHECK-NEXT:    ret
   %a = load <3 x float>, ptr %x
   %d = fptoui <3 x float> %a to <3 x i32>
   store <3 x i32> %d, ptr %y
   ret void
 }
 
 define <3 x i1> @fp2si_v3f32_v3i1(<3 x float> %x) {
 ; CHECK-LABEL: fp2si_v3f32_v3i1:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

 ; CHECK-NEXT:    vmerge.vim v9, v8, 1, v0
 ; CHECK-NEXT:    vfwcvt.f.xu.v v8, v9
 ; CHECK-NEXT:    ret
   %z = uitofp <2 x i1> %x to <2 x float>
   ret <2 x float> %z
 }
 
 define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
-; LMULMAX8RV32-LABEL: si2fp_v3i32_v3f32:
-; LMULMAX8RV32:       # %bb.0:
-; LMULMAX8RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV32-NEXT:    vfcvt.f.x.v v8, v8
-; LMULMAX8RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV32-NEXT:    addi a0, a1, 8
-; LMULMAX8RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX8RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX8RV32-NEXT:    ret
-;
-; LMULMAX8RV64-LABEL: si2fp_v3i32_v3f32:
-; LMULMAX8RV64:       # %bb.0:
-; LMULMAX8RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV64-NEXT:    vfcvt.f.x.v v8, v8
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV64-NEXT:    addi a0, a1, 8
-; LMULMAX8RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX8RV64-NEXT:    ret
-;
-; LMULMAX1RV32-LABEL: si2fp_v3i32_v3f32:
-; LMULMAX1RV32:       # %bb.0:
-; LMULMAX1RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV32-NEXT:    vfcvt.f.x.v v8, v8
-; LMULMAX1RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV32-NEXT:    addi a0, a1, 8
-; LMULMAX1RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX1RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1RV32-NEXT:    ret
-;
-; LMULMAX1RV64-LABEL: si2fp_v3i32_v3f32:
-; LMULMAX1RV64:       # %bb.0:
-; LMULMAX1RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV64-NEXT:    vfcvt.f.x.v v8, v8
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV64-NEXT:    addi a0, a1, 8
-; LMULMAX1RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX1RV64-NEXT:    ret
+; CHECK-LABEL: si2fp_v3i32_v3f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfcvt.f.x.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vse32.v v8, (a1)
+; CHECK-NEXT:    ret
   %a = load <3 x i32>, ptr %x
   %d = sitofp <3 x i32> %a to <3 x float>
   store <3 x float> %d, ptr %y
   ret void
 }
 
 define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
-; LMULMAX8RV32-LABEL: ui2fp_v3i32_v3f32:
-; LMULMAX8RV32:       # %bb.0:
-; LMULMAX8RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV32-NEXT:    vfcvt.f.xu.v v8, v8
-; LMULMAX8RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV32-NEXT:    addi a0, a1, 8
-; LMULMAX8RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX8RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX8RV32-NEXT:    ret
-;
-; LMULMAX8RV64-LABEL: ui2fp_v3i32_v3f32:
-; LMULMAX8RV64:       # %bb.0:
-; LMULMAX8RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX8RV64-NEXT:    vfcvt.f.xu.v v8, v8
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX8RV64-NEXT:    addi a0, a1, 8
-; LMULMAX8RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX8RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX8RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX8RV64-NEXT:    ret
-;
-; LMULMAX1RV32-LABEL: ui2fp_v3i32_v3f32:
-; LMULMAX1RV32:       # %bb.0:
-; LMULMAX1RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV32-NEXT:    vfcvt.f.xu.v v8, v8
-; LMULMAX1RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV32-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV32-NEXT:    addi a0, a1, 8
-; LMULMAX1RV32-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX1RV32-NEXT:    vse32.v v8, (a1)
-; LMULMAX1RV32-NEXT:    ret
-;
-; LMULMAX1RV64-LABEL: ui2fp_v3i32_v3f32:
-; LMULMAX1RV64:       # %bb.0:
-; LMULMAX1RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX1RV64-NEXT:    vfcvt.f.xu.v v8, v8
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vslidedown.vi v9, v8, 2
-; LMULMAX1RV64-NEXT:    addi a0, a1, 8
-; LMULMAX1RV64-NEXT:    vse32.v v9, (a0)
-; LMULMAX1RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; LMULMAX1RV64-NEXT:    vse64.v v8, (a1)
-; LMULMAX1RV64-NEXT:    ret
+; CHECK-LABEL: ui2fp_v3i32_v3f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfcvt.f.xu.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 3, e32, m1, ta, ma
+; CHECK-NEXT:    vse32.v v8, (a1)
+; CHECK-NEXT:    ret
   %a = load <3 x i32>, ptr %x
   %d = uitofp <3 x i32> %a to <3 x float>
   store <3 x float> %d, ptr %y
   ret void
 }
 
 define <3 x float> @si2fp_v3i1_v3f32(<3 x i1> %x) {
 ; CHECK-LABEL: si2fp_v3i1_v3f32:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

 
 ; This uses a non-power of 2 type so that it isn't an MVT.
 ; The align keeps the type legalizer from using a 256 bit load so we must split
 ; it. This some operations that weren't support for scalable vectors when
 ; this test was written.
 define void @insertelt_v3i64(ptr %x, i64 %y) {
 ; RV32-LABEL: insertelt_v3i64:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
 ; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    lw a3, 16(a0)
-; RV32-NEXT:    addi a4, a0, 20
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT:    vlse32.v v10, (a4), zero
-; RV32-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV32-NEXT:    vmv.s.x v10, a3
-; RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 2
 ; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
 ; RV32-NEXT:    vslide1down.vx v10, v8, a1
 ; RV32-NEXT:    vslide1down.vx v10, v10, a2
 ; RV32-NEXT:    vsetivli zero, 3, e64, m2, tu, ma
 ; RV32-NEXT:    vslideup.vi v8, v10, 2
-; RV32-NEXT:    sw a1, 16(a0)
-; RV32-NEXT:    sw a2, 20(a0)
-; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV32-NEXT:    vse64.v v8, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v3i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    sd a1, 16(a0)
+; RV64-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
+; RV64-NEXT:    vle64.v v8, (a0)
+; RV64-NEXT:    vmv.s.x v10, a1
+; RV64-NEXT:    vsetvli zero, zero, e64, m2, tu, ma
+; RV64-NEXT:    vslideup.vi v8, v10, 2
+; RV64-NEXT:    vse64.v v8, (a0)
 ; RV64-NEXT:    ret
   %a = load <3 x i64>, ptr %x, align 8
   %b = insertelement <3 x i64> %a, i64 %y, i32 2
   store <3 x i64> %b, ptr %x
   ret void
 }
 
 define void @insertelt_v16i8(ptr %x, i8 %y) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

 ; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; RV64-NEXT:    vse8.v v8, (a0)
 ; RV64-NEXT:    ret
   store <16 x i8> <i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1, i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1>, ptr %x
   ret void
 }
 
 define void @buildvec_seq_v9i8(ptr %x) {
-; RV32-LABEL: buildvec_seq_v9i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    li a1, 3
-; RV32-NEXT:    sb a1, 8(a0)
-; RV32-NEXT:    li a1, 73
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT:    vmv.s.x v0, a1
-; RV32-NEXT:    vmv.v.i v9, 2
-; RV32-NEXT:    li a1, 36
-; RV32-NEXT:    vmv.s.x v8, a1
-; RV32-NEXT:    vmerge.vim v9, v9, 1, v0
-; RV32-NEXT:    vmv1r.v v0, v8
-; RV32-NEXT:    vmerge.vim v8, v9, 3, v0
-; RV32-NEXT:    vse8.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: buildvec_seq_v9i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a1, %hi(.LCPI26_0)
-; RV64-NEXT:    ld a1, %lo(.LCPI26_0)(a1)
-; RV64-NEXT:    li a2, 3
-; RV64-NEXT:    sb a2, 8(a0)
-; RV64-NEXT:    sd a1, 0(a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: buildvec_seq_v9i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 73
+; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.s.x v0, a1
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 3
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    li a1, 146
+; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.s.x v0, a1
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmerge.vim v8, v8, 2, v0
+; CHECK-NEXT:    vsetivli zero, 9, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    ret
   store <9 x i8> <i8 1, i8 2, i8 3, i8 1, i8 2, i8 3, i8 1, i8 2, i8 3>, ptr %x
   ret void
 }
 
 define void @buildvec_seq_v4i16_v2i32(ptr %x) {
 ; CHECK-LABEL: buildvec_seq_v4i16_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, -127

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = add <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @add_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: add_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: add_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: add_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = add <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @add_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = sub <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @sub_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: sub_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vsub.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: sub_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vsub.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: sub_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsub.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = sub <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @sub_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = mul <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @mul_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: mul_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vmul.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: mul_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vmul.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: mul_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmul.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = mul <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @mul_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = and <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @and_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: and_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vand.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: and_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vand.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: and_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vand.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = and <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @and_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = or <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @or_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: or_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vor.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: or_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vor.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: or_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vor.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = or <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @or_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = xor <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @xor_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: xor_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vxor.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: xor_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vxor.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: xor_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vxor.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = xor <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @xor_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = lshr <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @lshr_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: lshr_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vsrl.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: lshr_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vsrl.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: lshr_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = lshr <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @lshr_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = ashr <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @ashr_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: ashr_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vsra.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: ashr_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vsra.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: ashr_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsra.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = ashr <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @ashr_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = shl <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @shl_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: shl_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vsll.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: shl_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vsll.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: shl_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = shl <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @shl_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = sdiv <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @sdiv_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: sdiv_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a1)
-; RV32-NEXT:    vle16.v v9, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    vslidedown.vi v11, v9, 4
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vdiv.vv v10, v11, v10
-; RV32-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v11, v10, 4
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vdiv.vv v8, v9, v8
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v8, v11, 2
-; RV32-NEXT:    addi a0, a0, 8
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: sdiv_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a1)
-; RV64-NEXT:    vle16.v v9, (a0)
-; RV64-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 4
-; RV64-NEXT:    vslidedown.vi v11, v9, 4
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vdiv.vv v10, v11, v10
-; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-NEXT:    vdiv.vv v8, v9, v8
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vslideup.vi v8, v10, 4
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: sdiv_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v9, (a0)
+; CHECK-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v10, v8, 4
+; CHECK-NEXT:    vslidedown.vi v11, v9, 4
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vdiv.vv v10, v11, v10
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vdiv.vv v8, v9, v8
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v10, 4
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = sdiv <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @sdiv_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = srem <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @srem_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: srem_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a1)
-; RV32-NEXT:    vle16.v v9, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    vslidedown.vi v11, v9, 4
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vrem.vv v10, v11, v10
-; RV32-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v11, v10, 4
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vrem.vv v8, v9, v8
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v8, v11, 2
-; RV32-NEXT:    addi a0, a0, 8
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: srem_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a1)
-; RV64-NEXT:    vle16.v v9, (a0)
-; RV64-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 4
-; RV64-NEXT:    vslidedown.vi v11, v9, 4
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vrem.vv v10, v11, v10
-; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-NEXT:    vrem.vv v8, v9, v8
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vslideup.vi v8, v10, 4
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: srem_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v9, (a0)
+; CHECK-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v10, v8, 4
+; CHECK-NEXT:    vslidedown.vi v11, v9, 4
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vrem.vv v10, v11, v10
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v9, v8
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v10, 4
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = srem <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @srem_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = udiv <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @udiv_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: udiv_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a1)
-; RV32-NEXT:    vle16.v v9, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    vslidedown.vi v11, v9, 4
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vdivu.vv v10, v11, v10
-; RV32-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v11, v10, 4
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vdivu.vv v8, v9, v8
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v8, v11, 2
-; RV32-NEXT:    addi a0, a0, 8
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: udiv_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a1)
-; RV64-NEXT:    vle16.v v9, (a0)
-; RV64-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 4
-; RV64-NEXT:    vslidedown.vi v11, v9, 4
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vdivu.vv v10, v11, v10
-; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-NEXT:    vdivu.vv v8, v9, v8
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vslideup.vi v8, v10, 4
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: udiv_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v9, (a0)
+; CHECK-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v10, v8, 4
+; CHECK-NEXT:    vslidedown.vi v11, v9, 4
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vdivu.vv v10, v11, v10
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vdivu.vv v8, v9, v8
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v10, 4
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = udiv <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @udiv_v4i32(ptr %x, ptr %y) {
; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = load <8 x i16>, ptr %y
   %c = urem <8 x i16> %a, %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @urem_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: urem_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a1)
-; RV32-NEXT:    vle16.v v9, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    vslidedown.vi v11, v9, 4
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vremu.vv v10, v11, v10
-; RV32-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v11, v10, 4
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vremu.vv v8, v9, v8
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v8, v11, 2
-; RV32-NEXT:    addi a0, a0, 8
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: urem_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a1)
-; RV64-NEXT:    vle16.v v9, (a0)
-; RV64-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 4
-; RV64-NEXT:    vslidedown.vi v11, v9, 4
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vremu.vv v10, v11, v10
-; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-NEXT:    vremu.vv v8, v9, v8
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vslideup.vi v8, v10, 4
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: urem_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v9, (a0)
+; CHECK-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v10, v8, 4
+; CHECK-NEXT:    vslidedown.vi v11, v9, 4
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vremu.vv v10, v11, v10
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vremu.vv v8, v9, v8
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v10, 4
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %c = urem <6 x i16> %a, %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
 define void @urem_v4i32(ptr %x, ptr %y) {

 ; CHECK-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
   store <8 x i16> %b, ptr %x
   ret void
 }
 
 define void @mulhu_v6i16(ptr %x) {
-; RV32-LABEL: mulhu_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 4
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vid.v v10
-; RV32-NEXT:    vadd.vi v10, v10, 12
-; RV32-NEXT:    vdivu.vv v9, v9, v10
-; RV32-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v10, v9, 4
-; RV32-NEXT:    lui a1, %hi(.LCPI67_0)
-; RV32-NEXT:    addi a1, a1, %lo(.LCPI67_0)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vdivu.vv v8, v8, v9
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v8, v10, 2
-; RV32-NEXT:    addi a0, a0, 8
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: mulhu_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    lui a1, %hi(.LCPI67_0)
-; RV64-NEXT:    addi a1, a1, %lo(.LCPI67_0)
-; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vdivu.vv v9, v8, v9
-; RV64-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 4
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vid.v v10
-; RV64-NEXT:    vadd.vi v10, v10, 12
-; RV64-NEXT:    vdivu.vv v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vslideup.vi v9, v8, 4
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v9, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v9, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: mulhu_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    lui a1, %hi(.LCPI67_0)
+; CHECK-NEXT:    addi a1, a1, %lo(.LCPI67_0)
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vdivu.vv v9, v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v8, v8, 4
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vid.v v10
+; CHECK-NEXT:    vadd.vi v10, v10, 12
+; CHECK-NEXT:    vdivu.vv v8, v8, v10
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v9, v8, 4
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v9, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = udiv <6 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13>
   store <6 x i16> %b, ptr %x
   ret void
 }
 
 define void @mulhu_v4i32(ptr %x) {
 ; CHECK-LABEL: mulhu_v4i32:

 ; RV64-NEXT:    ret
   %a = load <8 x i16>, ptr %x
   %b = sdiv <8 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7>
   store <8 x i16> %b, ptr %x
   ret void
 }
 
 define void @mulhs_v6i16(ptr %x) {
-; RV32-LABEL: mulhs_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.v.i v9, 7
-; RV32-NEXT:    vid.v v10
-; RV32-NEXT:    li a1, -14
-; RV32-NEXT:    vmadd.vx v10, a1, v9
-; RV32-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 4
-; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV32-NEXT:    vdiv.vv v9, v9, v10
-; RV32-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
-; RV32-NEXT:    vslideup.vi v10, v9, 4
-; RV32-NEXT:    li a1, 6
-; RV32-NEXT:    vmv.s.x v0, a1
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vmv.v.i v9, -7
-; RV32-NEXT:    vmerge.vim v9, v9, 7, v0
-; RV32-NEXT:    vdiv.vv v8, v8, v9
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v8, v10, 2
-; RV32-NEXT:    addi a0, a0, 8
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: mulhs_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.v.i v9, 7
-; RV64-NEXT:    vid.v v10
-; RV64-NEXT:    li a1, -14
-; RV64-NEXT:    vmadd.vx v10, a1, v9
-; RV64-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v9, v8, 4
-; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; RV64-NEXT:    vdiv.vv v9, v9, v10
-; RV64-NEXT:    li a1, 6
-; RV64-NEXT:    vmv.s.x v0, a1
-; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV64-NEXT:    vmv.v.i v10, -7
-; RV64-NEXT:    vmerge.vim v10, v10, 7, v0
-; RV64-NEXT:    vdiv.vv v8, v8, v10
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vslideup.vi v8, v9, 4
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: mulhs_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vmv.v.i v9, 7
+; CHECK-NEXT:    vid.v v10
+; CHECK-NEXT:    li a1, -14
+; CHECK-NEXT:    vmadd.vx v10, a1, v9
+; CHECK-NEXT:    vsetivli zero, 2, e16, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 4
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vdiv.vv v9, v9, v10
+; CHECK-NEXT:    li a1, 6
+; CHECK-NEXT:    vmv.s.x v0, a1
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v10, -7
+; CHECK-NEXT:    vmerge.vim v10, v10, 7, v0
+; CHECK-NEXT:    vdiv.vv v8, v8, v10
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vi v8, v9, 4
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = sdiv <6 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7>
   store <6 x i16> %b, ptr %x
   ret void
 }
 
 define void @mulhs_v4i32(ptr %x) {
 ; RV32-LABEL: mulhs_v4i32:
; CHECK-NEXT:    ret
   %b = load <8 x i16>, ptr %y
   %cc = icmp slt <8 x i16> %a, %b
   %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @smin_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: smin_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vmin.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: smin_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vmin.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: smin_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmin.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %cc = icmp slt <6 x i16> %a, %b
   %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %a, <8 x i16> %c)
   store <8 x i16> %d, ptr %x
   ret void
 }
 declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>)
 
 define void @smin_vx_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: smin_vx_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmin.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: smin_vx_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmin.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: smin_vx_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmin.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.smin.v6i16(<6 x i16> %a, <6 x i16> %c)
   store <6 x i16> %d, ptr %x
   ret void
 }
 declare <6 x i16> @llvm.smin.v6i16(<6 x i16>, <6 x i16>)
; CHECK-NEXT:    ret
   %b = insertelement <8 x i16> poison, i16 %y, i32 0
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %c, <8 x i16> %a)
   store <8 x i16> %d, ptr %x
   ret void
 }
 
 define void @smin_xv_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: smin_xv_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmin.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: smin_xv_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmin.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: smin_xv_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmin.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.smin.v6i16(<6 x i16> %c, <6 x i16> %a)
   store <6 x i16> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = load <8 x i16>, ptr %y
   %cc = icmp sgt <8 x i16> %a, %b
   %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @smax_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: smax_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vmax.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: smax_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vmax.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: smax_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmax.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %cc = icmp sgt <6 x i16> %a, %b
   %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %c)
   store <8 x i16> %d, ptr %x
   ret void
 }
 declare <8 x i16> @llvm.smax.v8i16(<8 x i16>, <8 x i16>)
 
 define void @smax_vx_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: smax_vx_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmax.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: smax_vx_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmax.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: smax_vx_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmax.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.smax.v6i16(<6 x i16> %a, <6 x i16> %c)
   store <6 x i16> %d, ptr %x
   ret void
 }
 declare <6 x i16> @llvm.smax.v6i16(<6 x i16>, <6 x i16>)
; CHECK-NEXT:    ret
   %b = insertelement <8 x i16> poison, i16 %y, i32 0
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %c, <8 x i16> %a)
   store <8 x i16> %d, ptr %x
   ret void
 }
 
 define void @smax_xv_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: smax_xv_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmax.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: smax_xv_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmax.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: smax_xv_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmax.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.smax.v6i16(<6 x i16> %c, <6 x i16> %a)
   store <6 x i16> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = load <8 x i16>, ptr %y
   %cc = icmp ult <8 x i16> %a, %b
   %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @umin_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: umin_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vminu.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: umin_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vminu.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: umin_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vminu.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %cc = icmp ult <6 x i16> %a, %b
   %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %c)
   store <8 x i16> %d, ptr %x
   ret void
 }
 declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)
 
 define void @umin_vx_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: umin_vx_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vminu.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: umin_vx_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vminu.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: umin_vx_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vminu.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.umin.v6i16(<6 x i16> %a, <6 x i16> %c)
   store <6 x i16> %d, ptr %x
   ret void
 }
 declare <6 x i16> @llvm.umin.v6i16(<6 x i16>, <6 x i16>)
; CHECK-NEXT:    ret
   %b = insertelement <8 x i16> poison, i16 %y, i32 0
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %c, <8 x i16> %a)
   store <8 x i16> %d, ptr %x
   ret void
 }
 
 define void @umin_xv_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: umin_xv_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vminu.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: umin_xv_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vminu.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: umin_xv_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vminu.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.umin.v6i16(<6 x i16> %c, <6 x i16> %a)
   store <6 x i16> %d, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = load <8 x i16>, ptr %y
   %cc = icmp ugt <8 x i16> %a, %b
   %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b
   store <8 x i16> %c, ptr %x
   ret void
 }
 
 define void @umax_v6i16(ptr %x, ptr %y) {
-; RV32-LABEL: umax_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vle16.v v9, (a1)
-; RV32-NEXT:    vmaxu.vv v8, v8, v9
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: umax_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vle16.v v9, (a1)
-; RV64-NEXT:    vmaxu.vv v8, v8, v9
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: umax_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vle16.v v9, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmaxu.vv v8, v8, v9
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = load <6 x i16>, ptr %y
   %cc = icmp ugt <6 x i16> %a, %b
   %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b
   store <6 x i16> %c, ptr %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %c)
   store <8 x i16> %d, ptr %x
   ret void
 }
 declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>)
 
 define void @umax_vx_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: umax_vx_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmaxu.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: umax_vx_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmaxu.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: umax_vx_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmaxu.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.umax.v6i16(<6 x i16> %a, <6 x i16> %c)
   store <6 x i16> %d, ptr %x
   ret void
 }
 declare <6 x i16> @llvm.umax.v6i16(<6 x i16>, <6 x i16>)
; CHECK-NEXT:    ret
   %b = insertelement <8 x i16> poison, i16 %y, i32 0
   %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
   %d = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %c, <8 x i16> %a)
   store <8 x i16> %d, ptr %x
   ret void
 }
 
 define void @umax_xv_v6i16(ptr %x, i16 %y) {
-; RV32-LABEL: umax_xv_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmaxu.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: umax_xv_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmaxu.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: umax_xv_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vmaxu.vx v8, v8, a1
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   %a = load <6 x i16>, ptr %x
   %b = insertelement <6 x i16> poison, i16 %y, i32 0
   %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer
   %d = call <6 x i16> @llvm.umax.v6i16(<6 x i16> %c, <6 x i16> %a)
   store <6 x i16> %d, ptr %x
   ret void
 }
 
; LMULMAX1-RV64-NEXT:    ret
   %a = load <8 x i32>, ptr %x
   %b = load <8 x i32>, ptr %y
   %c = add <8 x i32> %a, %b
   store <8 x i32> %c, ptr %x
   ret void
 }
 
 define void @add_v6i32(ptr %x, ptr %y) {
-; LMULMAX2-RV32-LABEL: add_v6i32:
-; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-RV32-NEXT:    vle32.v v8, (a0)
-; LMULMAX2-RV32-NEXT:    vle32.v v10, (a1)
-; LMULMAX2-RV32-NEXT:    vadd.vv v8, v8, v10
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; LMULMAX2-RV32-NEXT:    vslidedown.vi v10, v8, 4
-; LMULMAX2-RV32-NEXT:    addi a1, a0, 16
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT:    vse32.v v10, (a1)
-; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX2-RV32-NEXT:    vse32.v v8, (a0)
-; LMULMAX2-RV32-NEXT:    ret
-;
-; LMULMAX2-RV64-LABEL: add_v6i32:
-; LMULMAX2-RV64:       # %bb.0:
-; LMULMAX2-RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-RV64-NEXT:    vle32.v v8, (a0)
-; LMULMAX2-RV64-NEXT:    vle32.v v10, (a1)
-; LMULMAX2-RV64-NEXT:    vadd.vv v8, v8, v10
-; LMULMAX2-RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; LMULMAX2-RV64-NEXT:    vslidedown.vi v10, v8, 2
-; LMULMAX2-RV64-NEXT:    addi a1, a0, 16
-; LMULMAX2-RV64-NEXT:    vse64.v v10, (a1)
-; LMULMAX2-RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX2-RV64-NEXT:    vse32.v v8, (a0)
-; LMULMAX2-RV64-NEXT:    ret
+; LMULMAX2-LABEL: add_v6i32:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
+; LMULMAX2-NEXT:    vle32.v v8, (a0)
+; LMULMAX2-NEXT:    vle32.v v10, (a1)
+; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; LMULMAX2-NEXT:    vadd.vv v8, v8, v10
+; LMULMAX2-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
+; LMULMAX2-NEXT:    vse32.v v8, (a0)
+; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: add_v6i32:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi a2, a0, 16
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; LMULMAX1-RV32-NEXT:    vle32.v v8, (a0)
 ; LMULMAX1-RV32-NEXT:    vle32.v v9, (a1)
 ; LMULMAX1-RV32-NEXT:    vle32.v v10, (a2)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,m -O2 | FileCheck -check-prefixes=CHECK,RV32 %s
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,m -O2 | FileCheck -check-prefixes=CHECK,RV64 %s
 
 ; ------------------------------------------------------------------------------
 ; Loads
 ; ------------------------------------------------------------------------------
 
 ; FIXME: This should be widened to a vlseg2 of <4 x i32> with VL set to 3
 define {<3 x i32>, <3 x i32>} @load_factor2_v3(ptr %ptr) {
 ; CHECK-LABEL: load_factor2_v3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; CHECK-NEXT:    vle32.v v10, (a0)
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    vadd.vv v9, v8, v8
 ; CHECK-NEXT:    vrgather.vv v8, v10, v9
 ; CHECK-NEXT:    li a0, 4
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m2, ta, ma

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
 
 define <5 x i8> @load_v5i8(ptr %p) {
-; RV32-LABEL: load_v5i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT:    vle8.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: load_v5i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: load_v5i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    ret
   %x = load <5 x i8>, ptr %p
   ret <5 x i8> %x
 }
 
 define <5 x i8> @load_v5i8_align1(ptr %p) {
-; RV32-LABEL: load_v5i8_align1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lbu a1, 1(a0)
-; RV32-NEXT:    lbu a2, 0(a0)
-; RV32-NEXT:    lbu a3, 2(a0)
-; RV32-NEXT:    lbu a4, 3(a0)
-; RV32-NEXT:    slli a1, a1, 8
-; RV32-NEXT:    or a1, a1, a2
-; RV32-NEXT:    slli a3, a3, 16
-; RV32-NEXT:    slli a4, a4, 24
-; RV32-NEXT:    or a3, a4, a3
-; RV32-NEXT:    or a1, a3, a1
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.s.x v8, a1
-; RV32-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 1
-; RV32-NEXT:    vslidedown.vi v10, v8, 2
-; RV32-NEXT:    vslidedown.vi v11, v8, 3
-; RV32-NEXT:    lb a0, 4(a0)
-; RV32-NEXT:    addi a1, sp, 8
-; RV32-NEXT:    vse8.v v8, (a1)
-; RV32-NEXT:    addi a2, sp, 11
-; RV32-NEXT:    vse8.v v11, (a2)
-; RV32-NEXT:    addi a2, sp, 10
-; RV32-NEXT:    vse8.v v10, (a2)
-; RV32-NEXT:    addi a2, sp, 9
-; RV32-NEXT:    vse8.v v9, (a2)
-; RV32-NEXT:    sb a0, 12(sp)
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT:    vle8.v v8, (a1)
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: load_v5i8_align1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    addi sp, sp, -16
-; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    lbu a1, 1(a0)
-; RV64-NEXT:    lbu a2, 0(a0)
-; RV64-NEXT:    lbu a3, 2(a0)
-; RV64-NEXT:    lb a4, 3(a0)
-; RV64-NEXT:    slli a1, a1, 8
-; RV64-NEXT:    or a1, a1, a2
-; RV64-NEXT:    slli a3, a3, 16
-; RV64-NEXT:    slli a4, a4, 24
-; RV64-NEXT:    or a3, a4, a3
-; RV64-NEXT:    or a1, a3, a1
-; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT:    vmv.s.x v8, a1
-; RV64-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma
-; RV64-NEXT:    vslidedown.vi v9, v8, 1
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    vslidedown.vi v11, v8, 3
-; RV64-NEXT:    lb a0, 4(a0)
-; RV64-NEXT:    addi a1, sp, 8
-; RV64-NEXT:    vse8.v v8, (a1)
-; RV64-NEXT:    addi a2, sp, 11
-; RV64-NEXT:    vse8.v v11, (a2)
-; RV64-NEXT:    addi a2, sp, 10
-; RV64-NEXT:    vse8.v v10, (a2)
-; RV64-NEXT:    addi a2, sp, 9
-; RV64-NEXT:    vse8.v v9, (a2)
-; RV64-NEXT:    sb a0, 12(sp)
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-NEXT:    vle8.v v8, (a1)
-; RV64-NEXT:    addi sp, sp, 16
-; RV64-NEXT:    ret
+; CHECK-LABEL: load_v5i8_align1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    ret
   %x = load <5 x i8>, ptr %p, align 1
   ret <5 x i8> %x
 }
 
 define <6 x i8> @load_v6i8(ptr %p) {
-; RV32-LABEL: load_v6i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT:    vle8.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: load_v6i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: load_v6i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    ret
   %x = load <6 x i8>, ptr %p
   ret <6 x i8> %x
 }
 
 define <12 x i8> @load_v12i8(ptr %p) {
 ; CHECK-LABEL: load_v12i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 12, e8, m1, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    ret
   %x = load <12 x i8>, ptr %p
   ret <12 x i8> %x
 }
 
 define <6 x i16> @load_v6i16(ptr %p) {
 ; CHECK-LABEL: load_v6i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
 ; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    ret
   %x = load <6 x i16>, ptr %p
   ret <6 x i16> %x
 }
 
 define <6 x half> @load_v6f16(ptr %p) {
 ; RV32-LABEL: load_v6f16:

 ; RV64-NEXT:    ret
   %x = load <6 x half>, ptr %p
   ret <6 x half> %x
 }
 
 define <6 x float> @load_v6f32(ptr %p) {
 ; CHECK-LABEL: load_v6f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %x = load <6 x float>, ptr %p
   ret <6 x float> %x
 }
 
 define <6 x double> @load_v6f64(ptr %p) {
 ; CHECK-LABEL: load_v6f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT:    vsetivli zero, 6, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    ret
   %x = load <6 x double>, ptr %p
   ret <6 x double> %x
 }
 
 define <6 x i1> @load_v6i1(ptr %p) {
 ; RV32-LABEL: load_v6i1:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
 
 define void @store_v5i8(ptr %p, <5 x i8> %v) {
 ; CHECK-LABEL: store_v5i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma
-; CHECK-NEXT:    vslidedown.vi v9, v8, 4
-; CHECK-NEXT:    addi a1, a0, 4
-; CHECK-NEXT:    vse8.v v9, (a1)
-; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <5 x i8> %v, ptr %p
   ret void
 }
 
 define void @store_v5i8_align1(ptr %p, <5 x i8> %v) {
 ; CHECK-LABEL: store_v5i8_align1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma
-; CHECK-NEXT:    vslidedown.vi v9, v8, 4
-; CHECK-NEXT:    addi a1, a0, 4
-; CHECK-NEXT:    vse8.v v9, (a1)
-; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; CHECK-NEXT:    vmv.x.s a1, v8
-; CHECK-NEXT:    sb a1, 0(a0)
-; CHECK-NEXT:    srli a2, a1, 24
-; CHECK-NEXT:    sb a2, 3(a0)
-; CHECK-NEXT:    srli a2, a1, 16
-; CHECK-NEXT:    sb a2, 2(a0)
-; CHECK-NEXT:    srli a1, a1, 8
-; CHECK-NEXT:    sb a1, 1(a0)
+; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <5 x i8> %v, ptr %p, align 1
   ret void
 }
 
 
 define void @store_v6i8(ptr %p, <6 x i8> %v) {
 ; CHECK-LABEL: store_v6i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT:    vse32.v v8, (a0)
-; CHECK-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
-; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    addi a0, a0, 4
-; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 6, e8, mf2, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <6 x i8> %v, ptr %p
   ret void
 }
 
 define void @store_v12i8(ptr %p, <12 x i8> %v) {
-; RV32-LABEL: store_v12i8:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT:    vse8.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: store_v12i8:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: store_v12i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 12, e8, m1, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    ret
   store <12 x i8> %v, ptr %p
   ret void
 }
 
 define void @store_v6i16(ptr %p, <6 x i16> %v) {
-; RV32-LABEL: store_v6i16:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v8, 2
-; RV32-NEXT:    addi a1, a0, 8
-; RV32-NEXT:    vse32.v v9, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: store_v6i16:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
-; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
-; RV64-NEXT:    vslidedown.vi v8, v8, 2
-; RV64-NEXT:    addi a0, a0, 8
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: store_v6i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
+; CHECK-NEXT:    vse16.v v8, (a0)
+; CHECK-NEXT:    ret
   store <6 x i16> %v, ptr %p
   ret void
 }
 
 define void @store_v6f16(ptr %p, <6 x half> %v) {
 ; RV32-LABEL: store_v6f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16

 ; RV64-NEXT:    addi a0, a0, 8
 ; RV64-NEXT:    vse32.v v8, (a0)
 ; RV64-NEXT:    ret
   store <6 x half> %v, ptr %p
   ret void
 }
 
 define void @store_v6f32(ptr %p, <6 x float> %v) {
-; RV32-LABEL: store_v6f32:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a1, a0, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a1)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: store_v6f32:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a1, a0, 16
-; RV64-NEXT:    vse64.v v10, (a1)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; RV64-NEXT:    vse32.v v8, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: store_v6f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
   store <6 x float> %v, ptr %p
   ret void
 }
 
 define void @store_v6f64(ptr %p, <6 x double> %v) {
 ; CHECK-LABEL: store_v6f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e64, m4, ta, ma
-; CHECK-NEXT:    vslidedown.vi v12, v8, 4
-; CHECK-NEXT:    addi a1, a0, 32
-; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT:    vse64.v v12, (a1)
-; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT:    vsetivli zero, 6, e64, m4, ta, ma
 ; CHECK-NEXT:    vse64.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <6 x double> %v, ptr %p
   ret void
 }
 
 define void @store_v6i1(ptr %p, <6 x i1> %v) {
 ; CHECK-LABEL: store_v6i1:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64
 
 define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
 ; RV32-LABEL: vselect_vv_v6i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    lbu a2, 0(a2)
-; RV32-NEXT:    vle32.v v8, (a1)
-; RV32-NEXT:    srli a1, a2, 5
-; RV32-NEXT:    sb a1, 13(sp)
-; RV32-NEXT:    andi a1, a2, 1
-; RV32-NEXT:    sb a1, 8(sp)
-; RV32-NEXT:    slli a1, a2, 27
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    sb a1, 12(sp)
-; RV32-NEXT:    slli a1, a2, 28
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    sb a1, 11(sp)
-; RV32-NEXT:    slli a1, a2, 29
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    sb a1, 10(sp)
+; RV32-NEXT:    vle32.v v8, (a0)
+; RV32-NEXT:    vle32.v v10, (a1)
+; RV32-NEXT:    srli a0, a2, 5
+; RV32-NEXT:    sb a0, 13(sp)
+; RV32-NEXT:    andi a0, a2, 1
+; RV32-NEXT:    sb a0, 8(sp)
+; RV32-NEXT:    slli a0, a2, 27
+; RV32-NEXT:    srli a0, a0, 31
+; RV32-NEXT:    sb a0, 12(sp)
+; RV32-NEXT:    slli a0, a2, 28
+; RV32-NEXT:    srli a0, a0, 31
+; RV32-NEXT:    sb a0, 11(sp)
+; RV32-NEXT:    slli a0, a2, 29
+; RV32-NEXT:    srli a0, a0, 31
+; RV32-NEXT:    sb a0, 10(sp)
 ; RV32-NEXT:    slli a2, a2, 30
 ; RV32-NEXT:    srli a2, a2, 31
 ; RV32-NEXT:    sb a2, 9(sp)
-; RV32-NEXT:    addi a1, sp, 8
-; RV32-NEXT:    vle8.v v10, (a1)
-; RV32-NEXT:    vand.vi v10, v10, 1
-; RV32-NEXT:    vmsne.vi v0, v10, 0
-; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32-NEXT:    vle32.v v8, (a0), v0.t
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a0, a3, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a0)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vle8.v v12, (a0)
+; RV32-NEXT:    vand.vi v12, v12, 1
+; RV32-NEXT:    vmsne.vi v0, v12, 0
+; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT:    vmerge.vvm v8, v10, v8, v0
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a3)
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vselect_vv_v6i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    lbu a2, 0(a2)
-; RV64-NEXT:    vle32.v v8, (a1)
-; RV64-NEXT:    srli a1, a2, 5
-; RV64-NEXT:    sb a1, 13(sp)
-; RV64-NEXT:    andi a1, a2, 1
-; RV64-NEXT:    sb a1, 8(sp)
-; RV64-NEXT:    slli a1, a2, 59
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    sb a1, 12(sp)
-; RV64-NEXT:    slli a1, a2, 60
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    sb a1, 11(sp)
-; RV64-NEXT:    slli a1, a2, 61
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    sb a1, 10(sp)
+; RV64-NEXT:    vle32.v v8, (a0)
+; RV64-NEXT:    vle32.v v10, (a1)
+; RV64-NEXT:    srli a0, a2, 5
+; RV64-NEXT:    sb a0, 13(sp)
+; RV64-NEXT:    andi a0, a2, 1
+; RV64-NEXT:    sb a0, 8(sp)
+; RV64-NEXT:    slli a0, a2, 59
+; RV64-NEXT:    srli a0, a0, 63
+; RV64-NEXT:    sb a0, 12(sp)
+; RV64-NEXT:    slli a0, a2, 60
+; RV64-NEXT:    srli a0, a0, 63
+; RV64-NEXT:    sb a0, 11(sp)
+; RV64-NEXT:    slli a0, a2, 61
+; RV64-NEXT:    srli a0, a0, 63
+; RV64-NEXT:    sb a0, 10(sp)
 ; RV64-NEXT:    slli a2, a2, 62
 ; RV64-NEXT:    srli a2, a2, 63
 ; RV64-NEXT:    sb a2, 9(sp)
-; RV64-NEXT:    addi a1, sp, 8
-; RV64-NEXT:    vle8.v v10, (a1)
-; RV64-NEXT:    vand.vi v10, v10, 1
-; RV64-NEXT:    vmsne.vi v0, v10, 0
-; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT:    vle32.v v8, (a0), v0.t
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a0, a3, 16
-; RV64-NEXT:    vse64.v v10, (a0)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    addi a0, sp, 8
+; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vle8.v v12, (a0)
+; RV64-NEXT:    vand.vi v12, v12, 1
+; RV64-NEXT:    vmsne.vi v0, v12, 0
+; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT:    vmerge.vvm v8, v10, v8, v0
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a3)
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %va = load <6 x i32>, ptr %a
   %vb = load <6 x i32>, ptr %b
   %vcc = load <6 x i1>, ptr %cc
   %vsel = select <6 x i1> %vcc, <6 x i32> %va, <6 x i32> %vb
   store <6 x i32> %vsel, ptr %z
   ret void
 }
 
 define void @vselect_vx_v6i32(i32 %a, ptr %b, ptr %cc, ptr %z) {
 ; RV32-LABEL: vselect_vx_v6i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    lbu a2, 0(a2)
 ; RV32-NEXT:    vle32.v v8, (a1)
 ; RV32-NEXT:    srli a1, a2, 5
 ; RV32-NEXT:    sb a1, 13(sp)
 ; RV32-NEXT:    andi a1, a2, 1
 ; RV32-NEXT:    sb a1, 8(sp)
 ; RV32-NEXT:    slli a1, a2, 27
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 12(sp)
 ; RV32-NEXT:    slli a1, a2, 28
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 11(sp)
 ; RV32-NEXT:    slli a1, a2, 29
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 10(sp)
 ; RV32-NEXT:    slli a2, a2, 30
 ; RV32-NEXT:    srli a2, a2, 31
 ; RV32-NEXT:    sb a2, 9(sp)
 ; RV32-NEXT:    addi a1, sp, 8
+; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-NEXT:    vle8.v v10, (a1)
 ; RV32-NEXT:    vand.vi v10, v10, 1
 ; RV32-NEXT:    vmsne.vi v0, v10, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32-NEXT:    vmerge.vxm v8, v8, a0, v0
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a0, a3, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a0)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a3)
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vselect_vx_v6i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    lbu a2, 0(a2)
 ; RV64-NEXT:    vle32.v v8, (a1)
 ; RV64-NEXT:    srli a1, a2, 5
 ; RV64-NEXT:    sb a1, 13(sp)
 ; RV64-NEXT:    andi a1, a2, 1
 ; RV64-NEXT:    sb a1, 8(sp)
 ; RV64-NEXT:    slli a1, a2, 59
 ; RV64-NEXT:    srli a1, a1, 63
 ; RV64-NEXT:    sb a1, 12(sp)
 ; RV64-NEXT:    slli a1, a2, 60
 ; RV64-NEXT:    srli a1, a1, 63
 ; RV64-NEXT:    sb a1, 11(sp)
 ; RV64-NEXT:    slli a1, a2, 61
 ; RV64-NEXT:    srli a1, a1, 63
 ; RV64-NEXT:    sb a1, 10(sp)
 ; RV64-NEXT:    slli a2, a2, 62
 ; RV64-NEXT:    srli a2, a2, 63
 ; RV64-NEXT:    sb a2, 9(sp)
 ; RV64-NEXT:    addi a1, sp, 8
+; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-NEXT:    vle8.v v10, (a1)
 ; RV64-NEXT:    vand.vi v10, v10, 1
 ; RV64-NEXT:    vmsne.vi v0, v10, 0
 ; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vmerge.vxm v8, v8, a0, v0
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a0, a3, 16
-; RV64-NEXT:    vse64.v v10, (a0)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a3)
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %vb = load <6 x i32>, ptr %b
   %ahead = insertelement <6 x i32> poison, i32 %a, i32 0
   %va = shufflevector <6 x i32> %ahead, <6 x i32> poison, <6 x i32> zeroinitializer
   %vcc = load <6 x i1>, ptr %cc
   %vsel = select <6 x i1> %vcc, <6 x i32> %va, <6 x i32> %vb
   store <6 x i32> %vsel, ptr %z
   ret void
 }
 
 define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) {
 ; RV32-LABEL: vselect_vi_v6i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    lbu a1, 0(a1)
 ; RV32-NEXT:    vle32.v v8, (a0)
 ; RV32-NEXT:    srli a0, a1, 5
 ; RV32-NEXT:    sb a0, 13(sp)
 ; RV32-NEXT:    andi a0, a1, 1
 ; RV32-NEXT:    sb a0, 8(sp)
 ; RV32-NEXT:    slli a0, a1, 27
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 12(sp)
 ; RV32-NEXT:    slli a0, a1, 28
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 11(sp)
 ; RV32-NEXT:    slli a0, a1, 29
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 10(sp)
 ; RV32-NEXT:    slli a1, a1, 30
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 9(sp)
 ; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-NEXT:    vle8.v v10, (a0)
 ; RV32-NEXT:    vand.vi v10, v10, 1
 ; RV32-NEXT:    vmsne.vi v0, v10, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32-NEXT:    vmerge.vim v8, v8, -1, v0
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a0, a2, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a0)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a2)
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vselect_vi_v6i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    lbu a1, 0(a1)
 ; RV64-NEXT:    vle32.v v8, (a0)
 ; RV64-NEXT:    srli a0, a1, 5
 ; RV64-NEXT:    sb a0, 13(sp)
 ; RV64-NEXT:    andi a0, a1, 1
 ; RV64-NEXT:    sb a0, 8(sp)
 ; RV64-NEXT:    slli a0, a1, 59
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 12(sp)
 ; RV64-NEXT:    slli a0, a1, 60
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 11(sp)
 ; RV64-NEXT:    slli a0, a1, 61
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 10(sp)
 ; RV64-NEXT:    slli a1, a1, 62
 ; RV64-NEXT:    srli a1, a1, 63
 ; RV64-NEXT:    sb a1, 9(sp)
 ; RV64-NEXT:    addi a0, sp, 8
+; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-NEXT:    vle8.v v10, (a0)
 ; RV64-NEXT:    vand.vi v10, v10, 1
 ; RV64-NEXT:    vmsne.vi v0, v10, 0
 ; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vmerge.vim v8, v8, -1, v0
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a0, a2, 16
-; RV64-NEXT:    vse64.v v10, (a0)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a2)
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %vb = load <6 x i32>, ptr %b
   %a = insertelement <6 x i32> poison, i32 -1, i32 0
   %va = shufflevector <6 x i32> %a, <6 x i32> poison, <6 x i32> zeroinitializer
   %vcc = load <6 x i1>, ptr %cc
   %vsel = select <6 x i1> %vcc, <6 x i32> %va, <6 x i32> %vb
   store <6 x i32> %vsel, ptr %z
   ret void
 }
 
 
 define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
 ; RV32-LABEL: vselect_vv_v6f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    lbu a2, 0(a2)
-; RV32-NEXT:    vle32.v v8, (a1)
-; RV32-NEXT:    srli a1, a2, 5
-; RV32-NEXT:    sb a1, 13(sp)
-; RV32-NEXT:    andi a1, a2, 1
-; RV32-NEXT:    sb a1, 8(sp)
-; RV32-NEXT:    slli a1, a2, 27
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    sb a1, 12(sp)
-; RV32-NEXT:    slli a1, a2, 28
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    sb a1, 11(sp)
-; RV32-NEXT:    slli a1, a2, 29
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    sb a1, 10(sp)
+; RV32-NEXT:    vle32.v v8, (a0)
+; RV32-NEXT:    vle32.v v10, (a1)
+; RV32-NEXT:    srli a0, a2, 5
+; RV32-NEXT:    sb a0, 13(sp)
+; RV32-NEXT:    andi a0, a2, 1
+; RV32-NEXT:    sb a0, 8(sp)
+; RV32-NEXT:    slli a0, a2, 27
+; RV32-NEXT:    srli a0, a0, 31
+; RV32-NEXT:    sb a0, 12(sp)
+; RV32-NEXT:    slli a0, a2, 28
+; RV32-NEXT:    srli a0, a0, 31
+; RV32-NEXT:    sb a0, 11(sp)
+; RV32-NEXT:    slli a0, a2, 29
+; RV32-NEXT:    srli a0, a0, 31
+; RV32-NEXT:    sb a0, 10(sp)
 ; RV32-NEXT:    slli a2, a2, 30
 ; RV32-NEXT:    srli a2, a2, 31
 ; RV32-NEXT:    sb a2, 9(sp)
-; RV32-NEXT:    addi a1, sp, 8
-; RV32-NEXT:    vle8.v v10, (a1)
-; RV32-NEXT:    vand.vi v10, v10, 1
-; RV32-NEXT:    vmsne.vi v0, v10, 0
-; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV32-NEXT:    vle32.v v8, (a0), v0.t
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a0, a3, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a0)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vle8.v v12, (a0)
+; RV32-NEXT:    vand.vi v12, v12, 1
+; RV32-NEXT:    vmsne.vi v0, v12, 0
+; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT:    vmerge.vvm v8, v10, v8, v0
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a3)
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vselect_vv_v6f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    lbu a2, 0(a2)
-; RV64-NEXT:    vle32.v v8, (a1)
-; RV64-NEXT:    srli a1, a2, 5
-; RV64-NEXT:    sb a1, 13(sp)
-; RV64-NEXT:    andi a1, a2, 1
-; RV64-NEXT:    sb a1, 8(sp)
-; RV64-NEXT:    slli a1, a2, 59
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    sb a1, 12(sp)
-; RV64-NEXT:    slli a1, a2, 60
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    sb a1, 11(sp)
-; RV64-NEXT:    slli a1, a2, 61
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    sb a1, 10(sp)
+; RV64-NEXT:    vle32.v v8, (a0)
+; RV64-NEXT:    vle32.v v10, (a1)
+; RV64-NEXT:    srli a0, a2, 5
+; RV64-NEXT:    sb a0, 13(sp)
+; RV64-NEXT:    andi a0, a2, 1
+; RV64-NEXT:    sb a0, 8(sp)
+; RV64-NEXT:    slli a0, a2, 59
+; RV64-NEXT:    srli a0, a0, 63
+; RV64-NEXT:    sb a0, 12(sp)
+; RV64-NEXT:    slli a0, a2, 60
+; RV64-NEXT:    srli a0, a0, 63
+; RV64-NEXT:    sb a0, 11(sp)
+; RV64-NEXT:    slli a0, a2, 61
+; RV64-NEXT:    srli a0, a0, 63
+; RV64-NEXT:    sb a0, 10(sp)
 ; RV64-NEXT:    slli a2, a2, 62
 ; RV64-NEXT:    srli a2, a2, 63
 ; RV64-NEXT:    sb a2, 9(sp)
-; RV64-NEXT:    addi a1, sp, 8
-; RV64-NEXT:    vle8.v v10, (a1)
-; RV64-NEXT:    vand.vi v10, v10, 1
-; RV64-NEXT:    vmsne.vi v0, v10, 0
-; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
-; RV64-NEXT:    vle32.v v8, (a0), v0.t
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a0, a3, 16
-; RV64-NEXT:    vse64.v v10, (a0)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    addi a0, sp, 8
+; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vle8.v v12, (a0)
+; RV64-NEXT:    vand.vi v12, v12, 1
+; RV64-NEXT:    vmsne.vi v0, v12, 0
+; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT:    vmerge.vvm v8, v10, v8, v0
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a3)
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %va = load <6 x float>, ptr %a
   %vb = load <6 x float>, ptr %b
   %vcc = load <6 x i1>, ptr %cc
   %vsel = select <6 x i1> %vcc, <6 x float> %va, <6 x float> %vb
   store <6 x float> %vsel, ptr %z
   ret void
 }
 
 define void @vselect_vx_v6f32(float %a, ptr %b, ptr %cc, ptr %z) {
 ; RV32-LABEL: vselect_vx_v6f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    lbu a1, 0(a1)
 ; RV32-NEXT:    vle32.v v8, (a0)
 ; RV32-NEXT:    srli a0, a1, 5
 ; RV32-NEXT:    sb a0, 13(sp)
 ; RV32-NEXT:    andi a0, a1, 1
 ; RV32-NEXT:    sb a0, 8(sp)
 ; RV32-NEXT:    slli a0, a1, 27
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 12(sp)
 ; RV32-NEXT:    slli a0, a1, 28
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 11(sp)
 ; RV32-NEXT:    slli a0, a1, 29
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 10(sp)
 ; RV32-NEXT:    slli a1, a1, 30
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 9(sp)
 ; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-NEXT:    vle8.v v10, (a0)
 ; RV32-NEXT:    vand.vi v10, v10, 1
 ; RV32-NEXT:    vmsne.vi v0, v10, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32-NEXT:    vfmerge.vfm v8, v8, fa0, v0
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a0, a2, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a0)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a2)
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vselect_vx_v6f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    lbu a1, 0(a1)
 ; RV64-NEXT:    vle32.v v8, (a0)
 ; RV64-NEXT:    srli a0, a1, 5
 ; RV64-NEXT:    sb a0, 13(sp)
 ; RV64-NEXT:    andi a0, a1, 1
 ; RV64-NEXT:    sb a0, 8(sp)
 ; RV64-NEXT:    slli a0, a1, 59
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 12(sp)
 ; RV64-NEXT:    slli a0, a1, 60
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 11(sp)
 ; RV64-NEXT:    slli a0, a1, 61
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 10(sp)
 ; RV64-NEXT:    slli a1, a1, 62
 ; RV64-NEXT:    srli a1, a1, 63
 ; RV64-NEXT:    sb a1, 9(sp)
 ; RV64-NEXT:    addi a0, sp, 8
+; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-NEXT:    vle8.v v10, (a0)
 ; RV64-NEXT:    vand.vi v10, v10, 1
 ; RV64-NEXT:    vmsne.vi v0, v10, 0
 ; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vfmerge.vfm v8, v8, fa0, v0
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a0, a2, 16
-; RV64-NEXT:    vse64.v v10, (a0)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a2)
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %vb = load <6 x float>, ptr %b
   %ahead = insertelement <6 x float> poison, float %a, i32 0
   %va = shufflevector <6 x float> %ahead, <6 x float> poison, <6 x i32> zeroinitializer
   %vcc = load <6 x i1>, ptr %cc
   %vsel = select <6 x i1> %vcc, <6 x float> %va, <6 x float> %vb
   store <6 x float> %vsel, ptr %z
   ret void
 }
 
 define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) {
 ; RV32-LABEL: vselect_vfpzero_v6f32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    lbu a1, 0(a1)
 ; RV32-NEXT:    vle32.v v8, (a0)
 ; RV32-NEXT:    srli a0, a1, 5
 ; RV32-NEXT:    sb a0, 13(sp)
 ; RV32-NEXT:    andi a0, a1, 1
 ; RV32-NEXT:    sb a0, 8(sp)
 ; RV32-NEXT:    slli a0, a1, 27
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 12(sp)
 ; RV32-NEXT:    slli a0, a1, 28
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 11(sp)
 ; RV32-NEXT:    slli a0, a1, 29
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    sb a0, 10(sp)
 ; RV32-NEXT:    slli a1, a1, 30
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 9(sp)
 ; RV32-NEXT:    addi a0, sp, 8
+; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV32-NEXT:    vle8.v v10, (a0)
 ; RV32-NEXT:    vand.vi v10, v10, 1
 ; RV32-NEXT:    vmsne.vi v0, v10, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV32-NEXT:    vmerge.vim v8, v8, 0, v0
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslidedown.vi v10, v8, 4
-; RV32-NEXT:    addi a0, a2, 16
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vse32.v v10, (a0)
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a2)
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vselect_vfpzero_v6f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
-; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    lbu a1, 0(a1)
 ; RV64-NEXT:    vle32.v v8, (a0)
 ; RV64-NEXT:    srli a0, a1, 5
 ; RV64-NEXT:    sb a0, 13(sp)
 ; RV64-NEXT:    andi a0, a1, 1
 ; RV64-NEXT:    sb a0, 8(sp)
 ; RV64-NEXT:    slli a0, a1, 59
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 12(sp)
 ; RV64-NEXT:    slli a0, a1, 60
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 11(sp)
 ; RV64-NEXT:    slli a0, a1, 61
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 10(sp)
 ; RV64-NEXT:    slli a1, a1, 62
 ; RV64-NEXT:    srli a1, a1, 63
 ; RV64-NEXT:    sb a1, 9(sp)
 ; RV64-NEXT:    addi a0, sp, 8
+; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
 ; RV64-NEXT:    vle8.v v10, (a0)
 ; RV64-NEXT:    vand.vi v10, v10, 1
 ; RV64-NEXT:    vmsne.vi v0, v10, 0
 ; RV64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
 ; RV64-NEXT:    vmerge.vim v8, v8, 0, v0
-; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
-; RV64-NEXT:    vslidedown.vi v10, v8, 2
-; RV64-NEXT:    addi a0, a2, 16
-; RV64-NEXT:    vse64.v v10, (a0)
-; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a2)
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
   %vb = load <6 x float>, ptr %b
   %a = insertelement <6 x float> poison, float 0.0, i32 0
   %va = shufflevector <6 x float> %a, <6 x float> poison, <6 x i32> zeroinitializer
   %vcc = load <6 x i1>, ptr %cc
   %vsel = select <6 x i1> %vcc, <6 x float> %va, <6 x float> %vb