[AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

[foad]

Summary

This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

[critson]

I assume D129208 is the test case for this, so it does not need any new tests?

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

109

Presumably this is just fixing an error in the original comment, i.e. NFC?

303

I take it we cannot simply move the first LIS->shrinkToUses(SelLI); after the if because the IsDead query depends on it?

[foad]

I assume D129208 is the test case for this, so it does not need any new tests?

Yes that is my thinking. To test it in isolation I would need to tweak the RUN line in test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir to run another pass after si-optimize-exec-masking-pre-ra which depends on LiveIntervals having been preserved. I suppose I could try that, but it would become redundant again after D129208 lands.

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

109

Right. I've committed it separately now: b2e98c18cc8abf2c1cc6a7f85c8708550cc8fd28

303

Yes. On a related note, instead of rolling our own IsDead test I wondered if we should use the form of shrinkToUses which returns a vector of dead instructions. I tried that but it was causing other CodeGen differences not strictly related to this bug fix so I gave up.

Going even further, perhaps we should be using something like LiveRangeEdit::eliminateDeadDefs which already has the logic to iterate calling shrinkToUses.

[foad]

Rebase.

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
       return true;
   }
 
   return false;
 }
 
 // Optimize sequence
 //    %sel = V_CNDMASK_B32_e64 0, 1, %cc
 //    %cmp = V_CMP_NE_U32 1, %sel
 //    $vcc = S_AND_B64 $exec, %cmp
 //    S_CBRANCH_VCC[N]Z
 // =>
 //    $vcc = S_ANDN2_B64 $exec, %cc
 //    S_CBRANCH_VCC[N]Z
 //
 // It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
 // rebuildSetCC(). We start with S_CBRANCH to avoid exhaustive search, but
if ((CmpLI && CmpLI->Query(AndIdx.getRegSlot()).isKill()) ||
     bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill();
     LIS->shrinkToUses(SelLI);
     bool IsDead = SelLI->Query(SelIdx.getRegSlot()).isDeadDef();
     if (MRI->use_nodbg_empty(SelReg) && (IsKill || IsDead)) {
       LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
 
       LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
       LIS->RemoveMachineInstrFromMaps(*Sel);
+      bool ShrinkSel = Sel->getOperand(0).readsReg();
       Sel->eraseFromParent();
+      if (ShrinkSel) {
+        // The result of the V_CNDMASK was a subreg def which counted as a read
+        // from the other parts of the reg. Shrink their live ranges.
+        LIS->shrinkToUses(SelLI);
+      }
     }
   }
 
   return true;
 }
 
 // Optimize sequence
 //    %dst = S_OR_SAVEEXEC %src