[LiveIntervals] Split live intervals on any dead def

[dfukalov]

Summary

Each dead def of the same virtual register is required to be split into multiple
virtual registers with separate live intervals to avoid MachineVerifier error.

Partially fixes https://github.com/llvm/llvm-project/issues/56050 and
https://github.com/llvm/llvm-project/issues/56051

[foad]

Thanks for working on this! Sorry I don't know this code well enough to do a proper review.

[foad]

Fixes https://github.com/llvm/llvm-project/issues/56050 and
https://github.com/llvm/llvm-project/issues/56051

It does not fix all the problems. With just D129208 I get:

Failed Tests (6):
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
  LLVM :: CodeGen/AMDGPU/spill-before-exec.mir
  LLVM :: CodeGen/Hexagon/expand-condsets-def-undef.mir
  LLVM :: CodeGen/Hexagon/expand-condsets-rm-reg.mir
  LLVM :: CodeGen/Hexagon/expand-condsets-same-inputs.mir

With D129208 + D130477 I get:

Failed Tests (3):
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
  LLVM :: CodeGen/Hexagon/expand-condsets-def-undef.mir

[dfukalov]

With D129208 + D130477 I get:

Failed Tests (3):
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
  LLVM :: CodeGen/Hexagon/expand-condsets-def-undef.mir

Yes, I was too optimistic: the patch fixes "Multiple connected components in live interval" issues in AMDGPU/* tests but reveals next issue related to incorrect updates of ranges.
Regarding Hexagon/expand-condsets-def-undef.mir test issue - it is steel about multiple connected components.

Investigating these cases further.

[dfukalov]

Ping...

llvm/lib/CodeGen/LiveIntervals.cpp

bool LiveIntervals::shrinkToUses(LiveInterval *li,
   bool CanSeparate = computeDeadValues(*li, dead);
   LLVM_DEBUG(dbgs() << "Shrunk: " << *li << '\n');
   return CanSeparate;
 }
 
 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
                                       SmallVectorImpl<MachineInstr*> *dead) {
   bool MayHaveSplitComponents = false;
-  bool HaveDeadDef = false;
 
   for (VNInfo *VNI : LI.valnos) {
     if (VNI->isUnused())
       continue;
     SlotIndex Def = VNI->def;
     LiveRange::iterator I = LI.FindSegmentContaining(Def);
     assert(I != LI.end() && "Missing segment for VNI");
 
for (VNInfo *VNI : LI.valnos) {
 
     if (I->end != Def.getDeadSlot())
       continue;
     if (VNI->isPHIDef()) {
       // This is a dead PHI. Remove it.
       VNI->markUnused();
       LI.removeSegment(I);
       LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
-      MayHaveSplitComponents = true;
     } else {
       // This is a dead def. Make sure the instruction knows.
       MachineInstr *MI = getInstructionFromIndex(Def);
       assert(MI && "No instruction defining live value");
       MI->addRegisterDead(LI.reg(), TRI);
-      if (HaveDeadDef)
-        MayHaveSplitComponents = true;
-      HaveDeadDef = true;
 
       if (dead && MI->allDefsAreDead()) {
         LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
         dead->push_back(MI);
       }
     }
+    MayHaveSplitComponents = true;
   }
   return MayHaveSplitComponents;
 }
 
 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, Register Reg) {
   LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n');
   assert(Register::isVirtualRegister(Reg) &&
          "Can only shrink virtual registers");

llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir

body:             |
 
   bb.2:
     S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_redef_cmp
 # GCN:      %0:sgpr_32 = IMPLICIT_DEF
 # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
-# GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
+# GCN-NEXT: dead %3:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 # GCN-NEXT: %2:sgpr_32 = COPY $sgpr0
 # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3_redef_cmp
 body:             |
   bb.0:
     %0:sgpr_32 = IMPLICIT_DEF
bb.1:
     S_BRANCH %bb.2
 
   bb.2:
     S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_redef_sel
 # GCN:      %0:sgpr_32 = IMPLICIT_DEF
-# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
+# GCN-NEXT: dead %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
 # GCN-NEXT: %1:vgpr_32 = COPY $vgpr0
 # GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3_redef_sel
 body:             |
   bb.0:

llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

bb.1:
     S_BRANCH %bb.2
 
   bb.2:
     S_ENDPGM 0
 ...
 
 # GCN: name: negated_cond_vop3_redef_sel
 # GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
-# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
+# GCN-NEXT: dead %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec
 # GCN-NEXT: %1:vgpr_32 = COPY $vgpr0
 # GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
 # GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
 ---
 name:            negated_cond_vop3_redef_sel
 body:             |
   bb.0:

llvm/test/CodeGen/ARM/cortex-a57-misched-mla.mir

 # REQUIRES: asserts
 # RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
 
 # CHECK-LABEL: ********** MI Scheduling **********
 # CHECK:       %[[RES:[0-9]+]]:rgpr = t2MLA
 # CHECK-NEXT:  # preds left
 # CHECK-NEXT:  # succs left
 # CHECK-NEXT:  # rdefs left
 # CHECK-NEXT:  Latency : 3
 # CHECK-NEXT:  Depth
 # CHECK-NEXT:  Height
 # CHECK-NEXT:  Predecessors:
 # CHECK-NEXT:    SU({{.*}}): Data Latency=1 Reg=
-# CHECK-NEXT:    SU({{.*}}): Out  Latency=
 # CHECK-NEXT:    SU({{.*}}): Data Latency=1 Reg=
 # CHECK-NEXT:  Successors:
 # CHECK-NEXT:    SU([[SMLA_SU:[0-9]+]]): Data Latency=1 Reg=%[[RES]]
 # CHECK-NEXT:  Pressure Diff
 # CHECK-NEXT:  Single Issue : false;
 # CHECK-NEXT:  SU([[SMLA_SU]]): {{.*}} = t2SMLAL %{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr(tied-def 0), %[[RES]]:rgpr(tied-def 1), 14, $noreg
 
 name:            test_smlal_forwarding