Avoid generating instructions like this:
str za[w12, 0], [x0, #15, mul vl]
Because the index into ZA and the immediate of the addressing mode
should match up, e.g.
str za[w12, 15], [x0, #15, mul vl]
Differential D147136
[AArch64][SME] Fix broken intrinsics for ZA STR (vector) sdesmalen on Mar 29 2023, 3:53 AM. Authored by
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Event TimelineComment Actions Hi @sdesmalen, really sorry to do this, but following @rsandifo-arm's comment on D127317 I realised this patch is still incorrect because in @str_with_off_15mulvl it should really look like: mov w12, #-15 str za[w12, 15], [x0, #15, mul vl] sine the vector select value passed in to the intrinsic was 0. We therefore need to ensure the vector select value in str is also 0. Comment Actions @sdesmalen for now I've decided to disable the AddedComplexity = 2 patterns (see D147433). |