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ABataev
fhahn
sdesmalen
david-arm

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rG20d0f80dd356: [test] A test case for D146958

Summary

This commit introduces a test for the change introduced by the
[SCEV] Do not plant SCEV checks unnecessarily commit,
D146958.

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Repository: rG LLVM Github Monorepo

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pawosm01 created this revision.Mar 27 2023, 8:15 AM

Herald added a project: Restricted Project. · View Herald TranscriptMar 27 2023, 8:15 AM

pawosm01 requested review of this revision.Mar 27 2023, 8:15 AM

Herald added a project: Restricted Project. · View Herald TranscriptMar 27 2023, 8:15 AM

Herald added subscribers: llvm-commits, • pcwang-thead. · View Herald Transcript

pawosm01 retitled this revision from [test] A test case for D146839 to [test] A test case for D146958.Mar 27 2023, 8:16 AM

pawosm01 mentioned this in D146958: [SCEV] Do not plant SCEV checks unnecessarily.

fhahn added a subscriber: fhahn.Mar 27 2023, 9:10 AM

fhahn added inline comments.

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
8	`entry`?
11	Is this load needed or can the value directly be passed as argument?
15	Please shorten the block names and try to make them more descriptive, this will make the test easier to read. E.g. IIUC this could be something like `loop1.header`.
18	Is this branch needed here?
21	Is this load needed or can the value directly be passed as argument?
26	this could be `loop2.header`.
31	is this branch needed?
33	This could be `loop3.header`. Is a 3 level loop nest needed for the test? Would a 2 level loop nest be sufficient?
46	`loop2.latch`?
51	`loop1.latch`
56	`exit`?

Harbormaster completed remote builds in B222030: Diff 508671.Mar 27 2023, 11:09 AM

Failed as expected.

@fhahn Thanks for your comments. If you don't mind, I will address them in the post-review changes of D146958 in coming day(s).

pawosm01 marked an inline comment as done.Mar 28 2023, 6:58 AM

pawosm01 added inline comments.

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
31	Yes

Test updated as per the reviewer request.

pawosm01 marked 10 inline comments as done.Mar 28 2023, 7:00 AM

pawosm01 added a reviewer: fhahn.

Herald added a subscriber: StephenFan. · View Herald TranscriptMar 28 2023, 7:00 AM

Harbormaster completed remote builds in B222236: Diff 508996.Mar 28 2023, 7:48 AM

seems I had a wrong understanding of the reviewer's intent.

Harbormaster completed remote builds in B223595: Diff 510825.Apr 4 2023, 9:41 AM

pawosm01 edited the summary of this revision. (Show Details)Apr 4 2023, 10:51 AM

Herald added a subscriber: javed.absar. · View Herald TranscriptApr 4 2023, 10:51 AM

pawosm01 added reviewers: sdesmalen, david-arm.Apr 4 2023, 10:52 AM

I'll try to build a relation between D146974 and D146958.

pawosm01 added a child revision: D146958: [SCEV] Do not plant SCEV checks unnecessarily.Apr 4 2023, 11:08 AM

xbolva00 added a subscriber: xbolva00.Apr 4 2023, 11:26 AM

xbolva00 added inline comments.

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
2	This test needs to pass with current master. Tests are commited as first, so things would be broken.

Harbormaster completed remote builds in B223622: Diff 510861.Apr 4 2023, 11:46 AM

Following reviewer's advice.

wrong diff file picked; this is the correct one.

Looks OK now. @fhahn ?

pawosm01 marked an inline comment as done.Apr 4 2023, 12:13 PM

pawosm01 edited the summary of this revision. (Show Details)

Harbormaster completed remote builds in B223635: Diff 510877.Apr 4 2023, 1:00 PM

LGTM! It looks like you've addressed @fhahn's comments.

This revision is now accepted and ready to land.Apr 5 2023, 1:43 AM

fhahn added inline comments.Apr 5 2023, 2:36 AM

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
4	could you add a brief comment saying what this test is intended to check?
16	Could you add a new function that's basically the same as `@foo` but has `%arrayidx0` in `%loop2.header`?

pawosm01 marked an inline comment as done.Apr 17 2023, 7:18 AM

pawosm01 added inline comments.

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
16	Could you add a new function that's basically the same as @foo but has %arrayidx0 in %loop2.header? This will not expose the same behavior of the D146958 patch we care about in this test (namely, `vector.scevcheck` will remain).

pawosm01 marked an inline comment as done.Apr 17 2023, 7:27 AM

a short comment added as requested

pawosm01 marked an inline comment as done.Apr 17 2023, 7:30 AM

Harbormaster completed remote builds in B226098: Diff 514226.Apr 17 2023, 9:24 AM

Hi @fhahn, are you happy with the current shape?

fhahn added inline comments.Apr 23 2023, 2:34 PM

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
16	Right, but that's only with the current version of the patch; it should be relatively straightforward to also handle this case (https://reviews.llvm.org/D146958#inline-1439048). In any case, it won't hurt to have negative test cases as well.

mgabka added a subscriber: mgabka.Apr 24 2023, 2:29 AM

Extended with one more variant of the same test case, as requested.

pawosm01 marked an inline comment as done.Apr 25 2023, 7:03 AM

pawosm01 added inline comments.

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll
16	Hi Florian, your suggestion from the patch review has worked, hence I've modified this test file accordingly. I'd like to have your explicit approval before I merge this one.

LGTM, thanks!

This revision was landed with ongoing or failed builds.Apr 25 2023, 1:37 PM

Closed by commit rG20d0f80dd356: [test] A test case for D146958 (authored by pawosm01). · Explain Why

This revision was automatically updated to reflect the committed changes.

pawosm01 marked an inline comment as done.

pawosm01 added a commit: rG20d0f80dd356: [test] A test case for D146958.

Diff 516888

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll

This file was added.

				; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S < %s \| FileCheck %s

				xbolva00Unsubmitted Done Reply Inline Actions This test needs to pass with current master. Tests are commited as first, so things would be broken. xbolva00: This test needs to pass with current master. Tests are commited as first, so things would be…
				; This test is to ensure that SCEV checks (which are costly performancewise) are
				; not generated when appropriate aliasing checks are sufficient.
				fhahnUnsubmitted Done Reply Inline Actions could you add a brief comment saying what this test is intended to check? fhahn: could you add a brief comment saying what this test is intended to check?

				define void @foo(ptr %pout, ptr %pin, i64 %val0, i64 %val1, i64 %val2) {
				; CHECK-LABEL: @foo(
				; FIXME: CHECK below needs to be changed to CHECK-NOT to confirm the change.
				fhahnUnsubmitted Done Reply Inline Actions `entry`? fhahn: `entry`?
				; CHECK: vector.scevcheck
				; CHECK: vector.body
				entry:
				fhahnUnsubmitted Done Reply Inline Actions Is this load needed or can the value directly be passed as argument? fhahn: Is this load needed or can the value directly be passed as argument?
				%0 = getelementptr double, ptr %pin, i64 %val0
				br label %loop1.header

				loop1.header: ; preds = %loop1.latch, %entry
				fhahnUnsubmitted Done Reply Inline Actions Please shorten the block names and try to make them more descriptive, this will make the test easier to read. E.g. IIUC this could be something like `loop1.header`. fhahn: Please shorten the block names and try to make them more descriptive, this will make the test…
				%i = phi i64 [ %i.next, %loop1.latch ], [ 0, %entry ]
				fhahnUnsubmitted Done Reply Inline Actions Could you add a new function that's basically the same as `@foo` but has `%arrayidx0` in `%loop2.header`? fhahn: Could you add a new function that's basically the same as `@foo` but has `%arrayidx0` in…
				pawosm01AuthorUnsubmitted Done Reply Inline Actions Could you add a new function that's basically the same as @foo but has %arrayidx0 in %loop2.header? This will not expose the same behavior of the D146958 patch we care about in this test (namely, `vector.scevcheck` will remain). pawosm01: > Could you add a new function that's basically the same as @foo but has %arrayidx0 in %loop2.
				fhahnUnsubmitted Done Reply Inline Actions Right, but that's only with the current version of the patch; it should be relatively straightforward to also handle this case (https://reviews.llvm.org/D146958#inline-1439048). In any case, it won't hurt to have negative test cases as well. fhahn: Right, but that's only with the current version of the patch; it should be relatively…
				pawosm01AuthorUnsubmitted Done Reply Inline Actions Hi Florian, your suggestion from the patch review has worked, hence I've modified this test file accordingly. I'd like to have your explicit approval before I merge this one. pawosm01: Hi Florian, your suggestion from the patch review has worked, hence I've modified this test…
				%mul0 = mul nsw i64 %i, %val2
				%arrayidx0 = getelementptr inbounds double, ptr %0, i64 %mul0
				fhahnUnsubmitted Done Reply Inline Actions Is this branch needed here? fhahn: Is this branch needed here?
				%mul1 = mul nsw i64 %i, %val1
				br label %loop2.header

				fhahnUnsubmitted Done Reply Inline Actions Is this load needed or can the value directly be passed as argument? fhahn: Is this load needed or can the value directly be passed as argument?
				loop2.header: ; preds = %loop1.header, %loop2.header
				%j = phi i64 [ 0, %loop1.header ], [ %j.next, %loop2.header ]
				%1 = load double, ptr %arrayidx0, align 8
				%arrayidx1 = getelementptr inbounds double, ptr %0, i64 %j
				%2 = load double, ptr %arrayidx1, align 8
				fhahnUnsubmitted Done Reply Inline Actions this could be `loop2.header`. fhahn: this could be `loop2.header`.
				%sum = fadd contract double %1, %2
				%3 = getelementptr double, ptr %pout, i64 %mul1
				%arrayidx2 = getelementptr inbounds double, ptr %3, i64 %j
				store double %sum, ptr %arrayidx2, align 8
				%j.next = add nuw nsw i64 %j, 1
				fhahnUnsubmitted Done Reply Inline Actions is this branch needed? fhahn: is this branch needed?
				pawosm01AuthorUnsubmitted Done Reply Inline Actions Yes pawosm01: Yes
				%cmp = icmp slt i64 %j.next, %val1
				br i1 %cmp, label %loop2.header, label %loop1.latch
				fhahnUnsubmitted Done Reply Inline Actions This could be `loop3.header`. Is a 3 level loop nest needed for the test? Would a 2 level loop nest be sufficient? fhahn: This could be `loop3.header`. Is a 3 level loop nest needed for the test? Would a 2 level loop…

				loop1.latch: ; preds = %loop2.header
				%i.next = add nuw nsw i64 %i, 1
				%exitcond = icmp eq i64 %i.next, %val1
				br i1 %exitcond, label %exit, label %loop1.header

				exit: ; preds = %loop1.latch
				ret void
				}

				; Similar test to the above but with the %arrayidx0 moved to the loop2.header

				define void @bar(ptr %pout, ptr %pin, i64 %val0, i64 %val1, i64 %val2) {
				fhahnUnsubmitted Done Reply Inline Actions `loop2.latch`? fhahn: `loop2.latch`?
				; CHECK-LABEL: @bar(
				; FIXME: CHECK below needs to be changed to CHECK-NOT to confirm the change.
				; CHECK: vector.scevcheck
				; CHECK: vector.body
				entry:
				fhahnUnsubmitted Done Reply Inline Actions `loop1.latch` fhahn: `loop1.latch`
				%0 = getelementptr double, ptr %pin, i64 %val0
				br label %loop1.header

				loop1.header: ; preds = %loop1.latch, %entry
				%i = phi i64 [ %i.next, %loop1.latch ], [ 0, %entry ]
				fhahnUnsubmitted Done Reply Inline Actions `exit`? fhahn: `exit`?
				%mul0 = mul nsw i64 %i, %val2
				%mul1 = mul nsw i64 %i, %val1
				br label %loop2.header

				loop2.header: ; preds = %loop1.header, %loop2.header
				%j = phi i64 [ 0, %loop1.header ], [ %j.next, %loop2.header ]
				%arrayidx0 = getelementptr inbounds double, ptr %0, i64 %mul0
				%1 = load double, ptr %arrayidx0, align 8
				%arrayidx1 = getelementptr inbounds double, ptr %0, i64 %j
				%2 = load double, ptr %arrayidx1, align 8
				%sum = fadd contract double %1, %2
				%3 = getelementptr double, ptr %pout, i64 %mul1
				%arrayidx2 = getelementptr inbounds double, ptr %3, i64 %j
				store double %sum, ptr %arrayidx2, align 8
				%j.next = add nuw nsw i64 %j, 1
				%cmp = icmp slt i64 %j.next, %val1
				br i1 %cmp, label %loop2.header, label %loop1.latch

				loop1.latch: ; preds = %loop2.header
				%i.next = add nuw nsw i64 %i, 1
				%exitcond = icmp eq i64 %i.next, %val1
				br i1 %exitcond, label %exit, label %loop1.header

				exit: ; preds = %loop1.latch
				ret void
				}

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Diff 516888

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll

This is an archive of the discontinued LLVM Phabricator instance.

[test] A test case for D146958ClosedPublic

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Diff 516888

llvm/test/Transforms/LoopVectorize/vector-no-scevcheck.ll

[test] A test case for D146958
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