[RISCV] Add .insn support for compressed formats.

[craig.topper]

Summary

We've supported .insn for non-compressed for a while. This finishes the compressed supported.

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1630

This is a slightly weird error to give in this case... then again so is the non-C equivalent by the looks of it

2516

Wrap?

llvm/test/MC/RISCV/insn_c.s

2

Test errors?

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1630

Why is it weird?

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1630

C0 through C2 aren't numbers, this kind of implies only 0 through 2 are accepted, not also C0 through C2.

[MaskRay]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2516

Consider llvm::is_contained({...}, Format) to reduce the length and therefore improve readability.

llvm/test/MC/RISCV/insn_c.s

3

--check-prefix instead of (es) if there is just one prefix.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1630

Do you want me to say "opcode must be a valid opcode name or an immediate in the range [0, 2]"?

If you've figured out the format for these directives you're probably also looking at the opcode list.

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1630

That sounds fine to me, thanks

[craig.topper]

-Use StringSwitch to check Format.
-Update error message.
-Fix check-prefix

Working on error test cases

[craig.topper]

Add error tests

[MaskRay]

llvm/test/MC/RISCV/insn_c-invalid.s

4 ↗

(On Diff #507545)

For new tests, use [[#@LINE]]. [[@LINE]] is deprecated lit syntax.

[craig.topper]

Use #@LINE instead of @LINE

[asb]

LGTM - I just wonder about if we want to gate this on C/Zca as this patch does. Assuming someone reused the 16-bit encoding space, perhaps they want to using .insn to insert some of their instructions. OTOH, perhaps it's not so likely that the instruction formats would be as they want, at which point .insn isn't very useful.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
#include "RISCVGenAsmMatcher.inc"
   OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
   OperandMatchResultTy parseBareSymbol(OperandVector &Operands);
   OperandMatchResultTy parseCallSymbol(OperandVector &Operands);
   OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands);
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
   OperandMatchResultTy parseVTypeI(OperandVector &Operands);
   OperandMatchResultTy parseMaskReg(OperandVector &Operands);
   OperandMatchResultTy parseInsnDirectiveOpcode(OperandVector &Operands);
+  OperandMatchResultTy parseInsnCDirectiveOpcode(OperandVector &Operands);
   OperandMatchResultTy parseGPRAsFPR(OperandVector &Operands);
   OperandMatchResultTy parseFRMArg(OperandVector &Operands);
   OperandMatchResultTy parseFenceArg(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
   bool parseDirectiveAttribute();
bool isV0Reg() const {
     return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
   }
   bool isAnyReg() const {
     return Kind == KindTy::Register &&
            (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) ||
             RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) ||
             RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum));
   }
+  bool isAnyRegC() const {
+    return Kind == KindTy::Register &&
+           (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(
+                Reg.RegNum) ||
+            RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(
+                Reg.RegNum));
+  }
   bool isImm() const override { return Kind == KindTy::Immediate; }
   bool isMem() const override { return false; }
   bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
 
   bool isGPR() const {
     return Kind == KindTy::Register &&
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
template <unsigned N> bool IsUImm() const {
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<N>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm2() const { return IsUImm<2>(); }
   bool isUImm3() const { return IsUImm<3>(); }
+  bool isUImm4() const { return IsUImm<4>(); }
   bool isUImm5() const { return IsUImm<5>(); }
+  bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
+  bool isUImm8() const { return IsUImm<8>(); }
 
   bool isRnumArg() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(10) &&
case AsmToken::Identifier: {
     }
 
     break;
   }
   case AsmToken::Percent:
     break;
   }
 
-  Error(S, "opcode must be in the range [0, 127] and the lower 2 bits must be "
-           "0x3");
+  Error(S, "opcode must be a valid opcode name or an immediate in the range "
+           "[0, 127] and the lower 2 bits must be 0x3");
+  return MatchOperand_ParseFail;
+}
+
+OperandMatchResultTy
+RISCVAsmParser::parseInsnCDirectiveOpcode(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  SMLoc E;
+  const MCExpr *Res;
+
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::LParen:
+  case AsmToken::Minus:
+  case AsmToken::Plus:
+  case AsmToken::Exclaim:
+  case AsmToken::Tilde:
+  case AsmToken::Integer:
+  case AsmToken::String: {
+    if (getParser().parseExpression(Res, E))
+      return MatchOperand_ParseFail;
+
+    auto *CE = dyn_cast<MCConstantExpr>(Res);
+    if (CE) {
+      int64_t Imm = CE->getValue();
+      if (Imm >= 0 && Imm <= 2) {
+        Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
+        return MatchOperand_Success;
+      }
+    }
+
+    break;
+  }
+  case AsmToken::Identifier: {
+    StringRef Identifier;
+    if (getParser().parseIdentifier(Identifier))
+      return MatchOperand_ParseFail;
+
+    unsigned Opcode;
+    if (Identifier == "C0")
+      Opcode = 0;
+    else if (Identifier == "C1")
+      Opcode = 1;
+    else if (Identifier == "C2")
+      Opcode = 2;
+    else
+      break;
+
+    Res = MCConstantExpr::create(Opcode, getContext());
+    E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
+    Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
+    return MatchOperand_Success;
+  }
+  case AsmToken::Percent: {
+    // Discard operand with modifier.
+    break;
+  }
+  }
+
+  Error(S, "opcode must be a valid opcode name or an immediate in the range "
+           "[0, 2]");
   return MatchOperand_ParseFail;
 }
 
 OperandMatchResultTy
 RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Res;
 
case AsmToken::Identifier: {
     // Accept a named Sys Reg if the required features are present.
     if (SysReg) {
       if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) {
         Error(S, "system register use requires an option to be enabled");
         return MatchOperand_ParseFail;
       }
       Operands.push_back(
           RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding));
       return MatchOperand_Success;
     }
 
     Twine Msg = "operand must be a valid system register name "
                 "or an integer in the range";
     Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]");
     return MatchOperand_ParseFail;
   }
   case AsmToken::Percent: {
else {
 
     // Then emit the arch string.
     getTargetStreamer().emitTextAttribute(Tag, ISAInfo->toString());
   }
 
   return false;
 }
 
+bool isValidInsnFormat(StringRef Format, bool AllowC) {
+  return StringSwitch<bool>(Format)
+    .Cases("r", "r4", "i", "b", "sb", "u", "j", "uj", "s", true)
+    .Cases("cr", "ci", "ciw", "css", "cl", "cs", "ca", "cb", "cj", AllowC)
+    .Default(false);
+}
+
 /// parseDirectiveInsn
 /// ::= .insn [ format encoding, (operands (, operands)*) ]
 bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
   MCAsmParser &Parser = getParser();
 
   // Expect instruction format as identifier.
   StringRef Format;
   SMLoc ErrorLoc = Parser.getTok().getLoc();
   if (Parser.parseIdentifier(Format))
     return Error(ErrorLoc, "expected instruction format");
 
-  if (Format != "r" && Format != "r4" && Format != "i" && Format != "b" &&
-      Format != "sb" && Format != "u" && Format != "j" && Format != "uj" &&
-      Format != "s")
+  bool AllowC = getSTI().hasFeature(RISCV::FeatureStdExtC) ||
+                getSTI().hasFeature(RISCV::FeatureExtZca);
+  if (!isValidInsnFormat(Format, AllowC))
     return Error(ErrorLoc, "invalid instruction format");
 
   std::string FormatName = (".insn_" + Format).str();
 
   ParseInstructionInfo Info;
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
 
   if (ParseInstruction(Info, FormatName, L, Operands))

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM2_LSB0,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
+  OPERAND_UIMM6,
   OPERAND_UIMM7,
   OPERAND_UIMM7_LSB00,
   OPERAND_UIMM8_LSB00,
+  OPERAND_UIMM8,
   OPERAND_UIMM8_LSB000,
   OPERAND_UIMM9_LSB000,
   OPERAND_UIMM10_LSB00_NONZERO,
   OPERAND_UIMM12,
   OPERAND_ZERO,
   OPERAND_SIMM5,
   OPERAND_SIMM5_PLUS1,
   OPERAND_SIMM6,

llvm/lib/Target/RISCV/RISCVInstrFormatsC.td

class RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
   bits<3> rs1;
 
   let Inst{15-10} = funct6;
   let Inst{9-7} = rs1;
   let Inst{6} = funct1;
   let Inst{4-2} = rs2;
   let Inst{1-0} = opcode;
 }
+
+//===----------------------------------------------------------------------===//
+// Instruction classes for .insn directives
+//===----------------------------------------------------------------------===//
+
+class DirectiveInsnCR<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCR> {
+  bits<2> opcode;
+  bits<4> funct4;
+
+  bits<5> rs2;
+  bits<5> rd;
+
+  let Inst{15-12} = funct4;
+  let Inst{11-7} = rd;
+  let Inst{6-2} = rs2;
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn cr " # argstr;
+}
+
+class DirectiveInsnCI<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCI> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<6> imm6;
+  bits<5> rd;
+
+  let Inst{15-13} = funct3;
+  let Inst{12} = imm6{5};
+  let Inst{11-7} = rd;
+  let Inst{6-2} = imm6{4-0};
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn ci " # argstr;
+}
+
+class DirectiveInsnCIW<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCIW> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<8> imm8;
+  bits<3> rd;
+
+  let Inst{15-13} = funct3;
+  let Inst{12-5} = imm8;
+  let Inst{4-2} = rd;
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn ciw " # argstr;
+}
+
+class DirectiveInsnCSS<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCSS> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<6> imm6;
+  bits<5> rs2;
+
+  let Inst{15-13} = funct3;
+  let Inst{12-7} = imm6;
+  let Inst{6-2} = rs2;
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn css " # argstr;
+}
+
+class DirectiveInsnCL<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCL> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<5> imm5;
+  bits<3> rd;
+  bits<3> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{12-10} = imm5{4-2};
+  let Inst{9-7} = rs1;
+  let Inst{6-5} = imm5{1-0};
+  let Inst{4-2} = rd;
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn cl " # argstr;
+}
+
+class DirectiveInsnCS<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCS> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<5> imm5;
+  bits<3> rs2;
+  bits<3> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{12-10} = imm5{4-2};
+  let Inst{9-7} = rs1;
+  let Inst{6-5} = imm5{1-0};
+  let Inst{4-2} = rs2;
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn cs " # argstr;
+}
+
+class DirectiveInsnCA<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCA> {
+  bits<2> opcode;
+  bits<6> funct6;
+  bits<2> funct2;
+
+  bits<3> rd;
+  bits<3> rs2;
+
+  let Inst{15-10} = funct6;
+  let Inst{9-7} = rd;
+  let Inst{6-5} = funct2;
+  let Inst{4-2} = rs2;
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn ca " # argstr;
+}
+
+class DirectiveInsnCB<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCB> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<8> imm8;
+  bits<3> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{12} = imm8{7};
+  let Inst{11-10} = imm8{3-2};
+  let Inst{9-7} = rs1;
+  let Inst{6-5} = imm8{6-5};
+  let Inst{4-3} = imm8{1-0};
+  let Inst{2} = imm8{4};
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn cb " # argstr;
+}
+
+class DirectiveInsnCJ<dag outs, dag ins, string argstr>
+  : RVInst16<outs, ins, "", "", [], InstFormatCJ> {
+  bits<2> opcode;
+  bits<3> funct3;
+
+  bits<11> imm11;
+
+  let Inst{15-13} = funct3;
+  let Inst{12} = imm11{10};
+  let Inst{11} = imm11{3};
+  let Inst{10-9} = imm11{8-7};
+  let Inst{8} = imm11{9};
+  let Inst{7} = imm11{5};
+  let Inst{6} = imm11{6};
+  let Inst{5-3} = imm11{2-0};
+  let Inst{2} = imm11{4};
+  let Inst{1-0} = opcode;
+
+  let AsmString = ".insn cj " # argstr;
+}

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #define CASE_OPERAND_UIMM(NUM)                                                 \
   case RISCVOp::OPERAND_UIMM##NUM:                                             \
     Ok = isUInt<NUM>(Imm);                                                     \
     break;
         CASE_OPERAND_UIMM(2)
         CASE_OPERAND_UIMM(3)
         CASE_OPERAND_UIMM(4)
         CASE_OPERAND_UIMM(5)
+        CASE_OPERAND_UIMM(6)
         CASE_OPERAND_UIMM(7)
+        CASE_OPERAND_UIMM(8)
         CASE_OPERAND_UIMM(12)
         CASE_OPERAND_UIMM(20)
           // clang-format on
         case RISCVOp::OPERAND_UIMM2_LSB0:
           Ok = isShiftedUInt<1, 1>(Imm);
           break;
         case RISCVOp::OPERAND_UIMM7_LSB00:
           Ok = isShiftedUInt<5, 2>(Imm);

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 def uimm3 : Operand<XLenVT> {
   let ParserMatchClass = UImmAsmOperand<3>;
   let DecoderMethod = "decodeUImmOperand<3>";
   let OperandType = "OPERAND_UIMM3";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<4>;
+  let DecoderMethod = "decodeUImmOperand<4>";
+  let OperandType = "OPERAND_UIMM4";
+  let OperandNamespace = "RISCVOp";
+}
+
 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<5>;
   let DecoderMethod = "decodeUImmOperand<5>";
   let OperandType = "OPERAND_UIMM5";
   let OperandNamespace = "RISCVOp";
 }
 
 def InsnDirectiveOpcode : AsmOperandClass {
   let Name = "InsnDirectiveOpcode";
   let ParserMethod = "parseInsnDirectiveOpcode";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isImm";
 }
 
+def uimm6 : Operand<XLenVT> {
+  let ParserMatchClass = UImmAsmOperand<6>;
+  let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_UIMM6";
+  let OperandNamespace = "RISCVOp";
+}
+
 def uimm7_opcode : Operand<XLenVT> {
   let ParserMatchClass = InsnDirectiveOpcode;
   let DecoderMethod = "decodeUImmOperand<7>";
   let OperandType = "OPERAND_UIMM7";
   let OperandNamespace = "RISCVOp";
 }
 
 def uimm7 : Operand<XLenVT> {
   let ParserMatchClass = UImmAsmOperand<7>;
   let DecoderMethod = "decodeUImmOperand<7>";
   let OperandType = "OPERAND_UIMM7";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm8 : Operand<XLenVT> {
+  let ParserMatchClass = UImmAsmOperand<8>;
+  let DecoderMethod = "decodeUImmOperand<8>";
+  let OperandType = "OPERAND_UIMM8";
+  let OperandNamespace = "RISCVOp";
+}
+
 def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<12>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<12>";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<12>(Imm);

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isShiftedInt<11, 1>(Imm);
     return MCOp.isBareSymbolRef();
   }];
   let OperandType = "OPERAND_PCREL";
 }
 
+def InsnCDirectiveOpcode : AsmOperandClass {
+  let Name = "InsnCDirectiveOpcode";
+  let ParserMethod = "parseInsnCDirectiveOpcode";
+  let RenderMethod = "addImmOperands";
+  let PredicateMethod = "isImm";
+}
+
+def uimm2_opcode : Operand<XLenVT> {
+  let ParserMatchClass = InsnCDirectiveOpcode;
+  let DecoderMethod = "decodeUImmOperand<2>";
+  let OperandType = "OPERAND_UIMM2";
+  let OperandNamespace = "RISCVOp";
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 class CStackLoad<bits<3> funct3, string OpcodeStr,
                  RegisterClass cls, DAGOperand opnd>
     : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SPMem:$rs1, opnd:$imm),

 let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
 def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SPMem:$rs1, 0)>;
 def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SPMem:$rs1, 0)>;
 }
 } // EmitPriority = 0
 
+//===----------------------------------------------------------------------===//
+// .insn directive instructions
+//===----------------------------------------------------------------------===//
+
+def AnyRegCOperand : AsmOperandClass {
+  let Name = "AnyRegCOperand";
+  let RenderMethod = "addRegOperands";
+  let PredicateMethod = "isAnyRegC";
+}
+
+def AnyRegC : Operand<XLenVT> {
+  let OperandType = "OPERAND_REGISTER";
+  let ParserMatchClass = AnyRegCOperand;
+}
+
+// isCodeGenOnly = 1 to hide them from the tablegened assembly parser.
+let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1,
+    hasNoSchedulingInfo = 1, Predicates = [HasStdExtCOrZca] in {
+def InsnCR : DirectiveInsnCR<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode,
+                                                     uimm4:$funct4,
+                                                     AnyReg:$rs2),
+                             "$opcode, $funct4, $rd, $rs2">;
+def InsnCI : DirectiveInsnCI<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
+                                                      uimm3:$funct3,
+                                                      simm6:$imm6),
+                             "$opcode, $funct3, $rd, $imm6">;
+def InsnCIW : DirectiveInsnCIW<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
+                                                        uimm3:$funct3,
+                                                        uimm8:$imm8),
+                               "$opcode, $funct3, $rd, $imm8">;
+def InsnCSS : DirectiveInsnCSS<(outs), (ins uimm2_opcode:$opcode,
+                                            uimm3:$funct3,
+                                            AnyReg:$rs2,
+                                            uimm6:$imm6),
+                               "$opcode, $funct3, $rs2, $imm6">;
+def InsnCL : DirectiveInsnCL<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
+                                                      uimm3:$funct3,
+                                                      AnyRegC:$rs1,
+                                                      uimm5:$imm5),
+                             "$opcode, $funct3, $rd, ${imm5}(${rs1})">;
+def InsnCS : DirectiveInsnCS<(outs), (ins uimm2_opcode:$opcode,
+                                          uimm3:$funct3,
+                                          AnyRegC:$rs2,
+                                          AnyRegC:$rs1,
+                                          uimm5:$imm5),
+                             "$opcode, $funct3, $rs2, ${imm5}(${rs1})">;
+def InsnCA : DirectiveInsnCA<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
+                                                      uimm6:$funct6,
+                                                      uimm2:$funct2,
+                                                      AnyRegC:$rs2),
+                             "$opcode, $funct6, $funct2, $rd, $rs2">;
+def InsnCB : DirectiveInsnCB<(outs), (ins uimm2_opcode:$opcode, uimm3:$funct3,
+                                          AnyRegC:$rs1,
+                                          simm9_lsb0:$imm8),
+                             "$opcode, $funct3, $rs1, $imm8">;
+def InsnCJ : DirectiveInsnCJ<(outs), (ins uimm2_opcode:$opcode,
+                                          uimm3:$funct3,
+                                          simm12_lsb0:$imm11),
+                             "$opcode, $funct3, $imm11">;
+}
+
+// Use InstAliases to match these so that we can combine the insn and format
+// into a mnemonic to use as the key for the tablegened asm matcher table. The
+// parser will take care of creating these fake mnemonics and will only do it
+// for known formats.
+let EmitPriority = 0, Predicates = [HasStdExtCOrZca] in {
+def : InstAlias<".insn_cr $opcode, $funct4, $rd, $rs2",
+                (InsnCR AnyReg:$rd, uimm2_opcode:$opcode, uimm4:$funct4,
+                        AnyReg:$rs2)>;
+def : InstAlias<".insn_ci $opcode, $funct3, $rd, $imm6",
+                (InsnCI AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
+                        simm6:$imm6)>;
+def : InstAlias<".insn_ciw $opcode, $funct3, $rd, $imm8",
+                (InsnCIW AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
+                         uimm8:$imm8)>;
+def : InstAlias<".insn_css $opcode, $funct3, $rs2, $imm6",
+                (InsnCSS uimm2_opcode:$opcode, uimm3:$funct3, AnyReg:$rs2,
+                         uimm6:$imm6)>;
+def : InstAlias<".insn_cl $opcode, $funct3, $rd, ${imm5}(${rs1})",
+                (InsnCL AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
+                        AnyRegC:$rs1, uimm5:$imm5)>;
+def : InstAlias<".insn_cs $opcode, $funct3, $rs2, ${imm5}(${rs1})",
+                (InsnCS uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs2,
+                        AnyRegC:$rs1, uimm5:$imm5)>;
+def : InstAlias<".insn_ca $opcode, $funct6, $funct2, $rd, $rs2",
+                (InsnCA AnyRegC:$rd, uimm2_opcode:$opcode, uimm6:$funct6,
+                        uimm2:$funct2, AnyRegC:$rs2)>;
+def : InstAlias<".insn_cb $opcode, $funct3, $rs1, $imm8",
+                (InsnCB uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs1,
+                        simm9_lsb0:$imm8)>;
+def : InstAlias<".insn_cj $opcode, $funct3, $imm11",
+                (InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, simm12_lsb0:$imm11)>;
+}
+
 //===----------------------------------------------------------------------===/i
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
 // Patterns are defined in the same order the compressed instructions appear
 // on page 82 of the ISA manual.
 
 // Quadrant 0

llvm/test/MC/RISCV/insn-invalid.s

 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
 
 # Too many operands
 .insn i  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:33: error: invalid operand for instruction
 .insn r  0x43,  0,  0, fa0, fa1, fa2, fa3, fa4 # CHECK: :[[@LINE]]:44: error: invalid operand for instruction
 
 # Too few operands
 .insn r  0x33,  0,  0, a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 .insn i  0x13,  0,  a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 
 .insn r  0x33,  0,  0, a0, 13 # CHECK: :[[@LINE]]:28: error: invalid operand for instruction
 .insn i  0x13,  0, a0, a1, a2 # CHECK: :[[@LINE]]:28: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
 .insn q  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format
 
 # Invalid immediate
-.insn i  0x99,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
-.insn i  0,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
+.insn i  0x99,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be a valid opcode name or an immediate in the range [0, 127] and the lower 2 bits must be 0x3
+.insn i  0,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be a valid opcode name or an immediate in the range [0, 127] and the lower 2 bits must be 0x3
 .insn r  0x33,  8,  0, a0, a1, a2 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7]
 .insn r4 0x43,  0,  4, fa0, fa1, fa2, fa3 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]
 
 # Unrecognized opcode name
-.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
+.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: opcode must be a valid opcode name or an immediate in the range [0, 127] and the lower 2 bits must be 0x3
 
 # Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed.
 .insn_i  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive

llvm/test/MC/RISCV/insn_c.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f,+c -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefix=CHECK-ASM %s
+# RUN: llvm-mc %s -triple riscv64 -mattr=+f,+c -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefix=CHECK-ASM %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f,+c < %s \
+# RUN:     | llvm-objdump --mattr=+f,+c -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefix=CHECK-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f,+c < %s \
+# RUN:     | llvm-objdump --mattr=+f,+c -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefix=CHECK-OBJ %s
+
+target:
+
+# CHECK-ASM: .insn cr  2, 9, a0, a1
+# CHECK-ASM: encoding: [0x2e,0x95]
+# CHECK-OBJ: c.add a0, a1
+.insn cr  2, 9, a0, a1
+
+# CHECK-ASM: .insn cr  2, 9, a0, a1
+# CHECK-ASM: encoding: [0x2e,0x95]
+# CHECK-OBJ: c.add a0, a1
+.insn cr C2, 9, a0, a1
+
+# CHECK-ASM: .insn ci  1, 0, a0, 13
+# CHECK-ASM: encoding: [0x35,0x05]
+# CHECK-OBJ: c.addi a0, 13
+.insn ci  1, 0, a0, 13
+
+# CHECK-ASM: .insn ci  1, 0, a0, 13
+# CHECK-ASM: encoding: [0x35,0x05]
+# CHECK-OBJ: c.addi a0, 13
+.insn ci C1, 0, a0, 13
+
+# CHECK-ASM: .insn ciw  0, 0, a0, 13
+# CHECK-ASM: encoding: [0xa8,0x01]
+# CHECK-OBJ: c.addi4spn a0, sp, 200
+.insn ciw  0, 0, a0, 13
+
+# CHECK-ASM: .insn ciw  0, 0, a0, 13
+# CHECK-ASM: encoding: [0xa8,0x01]
+# CHECK-OBJ: c.addi4spn a0, sp, 200
+.insn ciw C0, 0, a0, 13
+
+# CHECK-ASM: .insn css  2, 6, a0, 13
+# CHECK-ASM: encoding: [0xaa,0xc6]
+# CHECK-OBJ: c.swsp a0, 76(sp)
+.insn css  2, 6, a0, 13
+
+# CHECK-ASM: .insn cl  0, 2, a0, 13
+# CHECK-ASM: encoding: [0xa8,0x4d]
+# CHECK-OBJ: c.lw a0, 88(a1)
+.insn cl  0, 2, a0, 13(a1)
+
+# CHECK-ASM: .insn cs  0, 6, a0, 13
+# CHECK-ASM: encoding: [0xa8,0xcd]
+# CHECK-OBJ: c.sw a0, 88(a1)
+.insn cs  0, 6, a0, 13(a1)
+
+# CHECK-ASM: .insn ca  1, 35, 0, a0, a1
+# CHECK-ASM: encoding: [0x0d,0x8d]
+# CHECK-OBJ: c.sub a0, a1
+.insn ca  1, 35, 0, a0, a1
+
+# CHECK-ASM: .insn cb 1, 6, a0, target
+# CHECK-ASM: encoding: [0x01'A',0xc1'A']
+# CHECK-OBJ: c.beqz a0, 0x0 <target>
+.insn cb  1, 6, a0, target
+
+# CHECK-ASM: .insn cj 1, 5, target
+# CHECK-ASM: encoding: [0bAAAAAA01,0b101AAAAA]
+# CHECK-OBJ: c.j 0x0 <target>
+.insn cj  1, 5, target