[SelectionDAG][RISCV] Fix SimplifyDemandedBits for scalable vectors

[dtcxzyw]

Summary

The function SimplifyDemandedBits attempts to get the bit-width of a scalable vector type while building LLVM-test-suite with -march=rv64gcv. This patch skips some simplifications since we assume we know nothing about scalable vectors for now.

[craig.topper]

This code has been fixed a different way in another patch

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (const APInt *SA =
       // TODO - support non-uniform vector amounts.
       if (Op0.getOpcode() == ISD::ANY_EXTEND) {
         SDValue InnerOp = Op0.getOperand(0);
         EVT InnerVT = InnerOp.getValueType();
         unsigned InnerBits = InnerVT.getScalarSizeInBits();
         if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
             isTypeDesirableForOp(ISD::SHL, InnerVT)) {
           EVT ShTy = getShiftAmountTy(InnerVT, DL);
+          if (ShTy.isScalableVector())
+            return false;
           if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
             ShTy = InnerVT;
           SDValue NarrowShl =
               TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
                               TLO.DAG.getConstant(ShAmt, dl, ShTy));
           return TLO.CombineTo(
               Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
         }