[llvm-exegesis] Prevent llvm-exegesis from using unsupported opcodes

[kpdev42]

Summary

When generating snippets for AArch64 with --opcode-index=-1, the code
generator asserts on opcodes that are not supported according to CPU
features.

The same assertion can be triggered even when generating a serial
snippet for a supported opcode if SERIAL_VIA_NON_MEMORY_INSTR execution
mode is used and an unsupported instruction is chosen as the "other
instruction". Unlike the first case, this one may result in flaky
failures because the other instruction is randomly chosen from the
instructions suitable for serializing execution.

This patch adjusts TableGen emitter for *GenInstrInfo.inc to make
possible to query for opcode availability instead of just asserting on
unsupported ones.

~~

Huawei RRI, OS Lab

[courbet]

In principle I like that, however this has implications on the size of the various llvm binaries. Can you please measure the increase in binary size for e.g. clang ?

[kpdev42]

In D146303#4223120, @courbet wrote:

In principle I like that, however this has implications on the size of the various llvm binaries. Can you please measure the increase in binary size for e.g. clang ?

Sure. Built with the following cmake cache

set(CMAKE_C_COMPILER   /usr/bin/clang   CACHE STRING "")
set(CMAKE_CXX_COMPILER /usr/bin/clang++ CACHE STRING "")
set(LLVM_PARALLEL_LINK_JOBS 6 CACHE STRING "")
set(LLVM_CCACHE_BUILD  ON CACHE BOOL "")

set(CMAKE_BUILD_TYPE       Release CACHE STRING "")
set(LLVM_ENABLE_ASSERTIONS OFF     CACHE BOOL "")

set(LLVM_ENABLE_PROJECTS  "clang;lld" CACHE STRING "")
set(LLVM_TARGETS_TO_BUILD "all" CACHE STRING "")

Host compiler is

$ /usr/bin/clang --version
Ubuntu clang version 15.0.6
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/bin

Size of bin/clang-17 increases by about 150 kilobytes mostly because of the .rodata section.

[kpdev42]

ping

[courbet]

Thanks for the data. Can you get someone to approve that the size change is OK ? Otherwise LGTM for the exegesis part.

[kpdev42]

Rebase patch

[kpdev42]

In D146303#4251056, @courbet wrote:

Thanks for the data. Can you get someone to approve that the size change is OK ? Otherwise LGTM for the exegesis part.

I will try to find someone )

[kpdev42]

Reworked the patch. Now it should not increase the size of unrelated
llvm tools and clang. Most of the changes to TableGen emitter are
factored out into a separate patch https://reviews.llvm.org/D148516

[kpdev42]

Rebased

[kpdev42]

Change according to clang-format

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 #include "AArch64.h"
 #include "AArch64RegisterInfo.h"
 
+#define GET_AVAILABLE_OPCODE_CHECKER
+#include "AArch64GenInstrInfo.inc"
+
 namespace llvm {
 namespace exegesis {
 
 static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
   case 32:
     return AArch64::MOVi32imm;
   case 64:

 }
 
 #include "AArch64GenExegesis.inc"
 
 namespace {
 
 class ExegesisAArch64Target : public ExegesisTarget {
 public:
-  ExegesisAArch64Target() : ExegesisTarget(AArch64CpuPfmCounters) {}
+  ExegesisAArch64Target()
+      : ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
 
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override {
     if (AArch64::GPR32RegClass.contains(Reg))
       return {loadImmediate(Reg, 32, Value)};
     if (AArch64::GPR64RegClass.contains(Reg))
       return {loadImmediate(Reg, 64, Value)};

llvm/tools/llvm-exegesis/lib/Mips/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "../Error.h"
 #include "../Target.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "Mips.h"
 #include "MipsRegisterInfo.h"
 
+#define GET_AVAILABLE_OPCODE_CHECKER
+#include "MipsGenInstrInfo.inc"
+
 namespace llvm {
 namespace exegesis {
 
 #ifndef NDEBUG
 // Returns an error if we cannot handle the memory references in this
 // instruction.
 static Error isInvalidMemoryInstr(const Instruction &Instr) {
   switch (Instr.Description.TSFlags & MipsII::FormMask) {
static void setMemOp(InstructionTemplate &IT, int OpIdx,
   IT.getValueFor(Op) = OpVal;
 }
 
 #include "MipsGenExegesis.inc"
 
 namespace {
 class ExegesisMipsTarget : public ExegesisTarget {
 public:
-  ExegesisMipsTarget() : ExegesisTarget(MipsCpuPfmCounters) {}
+  ExegesisMipsTarget()
+      : ExegesisTarget(MipsCpuPfmCounters, Mips_MC::isOpcodeAvailable) {}
 
 private:
   unsigned getScratchMemoryRegister(const llvm::Triple &TT) const override;
   unsigned getMaxMemoryAccessSize() const override { return 64; }
   void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                           unsigned Offset) const override;
 
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,

llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 // The PowerPC ExegesisTarget.
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 #include "PPC.h"
 #include "PPCRegisterInfo.h"
 
+#define GET_AVAILABLE_OPCODE_CHECKER
+#include "PPCGenInstrInfo.inc"
+
 namespace llvm {
 namespace exegesis {
 
 // Helper to fill a memory operand with a value.
 static void setMemOp(InstructionTemplate &IT, int OpIdx,
                      const MCOperand &OpVal) {
   const auto Op = IT.getInstr().Operands[OpIdx];
   assert(Op.isExplicit() && "invalid memory pattern");
   IT.getValueFor(Op) = OpVal;
 }
 
 #include "PPCGenExegesis.inc"
 
 namespace {
 class ExegesisPowerPCTarget : public ExegesisTarget {
 public:
-  ExegesisPowerPCTarget() : ExegesisTarget(PPCCpuPfmCounters) {}
+  ExegesisPowerPCTarget()
+      : ExegesisTarget(PPCCpuPfmCounters, PPC_MC::isOpcodeAvailable) {}
 
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override;
   bool matchesArch(Triple::ArchType Arch) const override {
     return Arch == Triple::ppc64le;
   }
   unsigned getScratchMemoryRegister(const Triple &) const override;

llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp

 };
 
 static constexpr size_t kMaxAliasingInstructions = 10;
 
 static std::vector<const Instruction *>
 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
                             size_t MaxAliasingInstructions,
                             const BitVector &ForbiddenRegisters) {
+  const auto &ET = State.getExegesisTarget();
+  const auto AvailableFeatures = State.getSubtargetInfo().getFeatureBits();
   // Randomly iterate the set of instructions.
   std::vector<unsigned> Opcodes;
   Opcodes.resize(State.getInstrInfo().getNumOpcodes());
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   llvm::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
 
   std::vector<const Instruction *> AliasingInstructions;
   for (const unsigned OtherOpcode : Opcodes) {
+    if (!ET.isOpcodeAvailable(OtherOpcode, AvailableFeatures))
+      continue;
     if (OtherOpcode == Instr->Description.getOpcode())
       continue;
     const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
     const MCInstrDesc &OtherInstrDesc = OtherInstr.Description;
     // Ignore instructions that we cannot run.
     if (OtherInstrDesc.isPseudo() || OtherInstrDesc.usesCustomInsertionHook() ||
         OtherInstrDesc.isBranch() || OtherInstrDesc.isIndirectBranch() ||
         OtherInstrDesc.isCall() || OtherInstrDesc.isReturn()) {
           continue;
     }
     if (OtherInstr.hasMemoryOperands())
       continue;
-    if (!State.getExegesisTarget().allowAsBackToBack(OtherInstr))
+    if (!ET.allowAsBackToBack(OtherInstr))
       continue;
     if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
       AliasingInstructions.push_back(&OtherInstr);
     if (AliasingInstructions.size() >= MaxAliasingInstructions)
       break;
   }
   return AliasingInstructions;
 }

llvm/tools/llvm-exegesis/lib/Target.h

 #include "SnippetGenerator.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Error.h"
+#include "llvm/TargetParser/SubtargetFeature.h"
 #include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
 namespace exegesis {
 
 extern cl::OptionCategory Options;
 extern cl::OptionCategory BenchmarkOptions;
 extern cl::OptionCategory AnalysisOptions;

 struct CpuAndPfmCounters {
   const char *CpuName;
   const PfmCountersInfo *PCI;
   bool operator<(StringRef S) const { return StringRef(CpuName) < S; }
 };
 
 class ExegesisTarget {
 public:
-  explicit ExegesisTarget(ArrayRef<CpuAndPfmCounters> CpuPfmCounters)
-      : CpuPfmCounters(CpuPfmCounters) {}
+  typedef bool (*OpcodeAvailabilityChecker)(unsigned, const FeatureBitset &);
+  ExegesisTarget(ArrayRef<CpuAndPfmCounters> CpuPfmCounters,
+                 OpcodeAvailabilityChecker IsOpcodeAvailable)
+      : CpuPfmCounters(CpuPfmCounters), IsOpcodeAvailable(IsOpcodeAvailable) {}
 
   // Targets can use this to create target-specific perf counters.
   virtual Expected<std::unique_ptr<pfm::Counter>>
   createCounter(StringRef CounterName, const LLVMState &State,
                 const pid_t ProcessID = 0) const;
 
   // Targets can use this to add target-specific passes in assembleToStream();
   virtual void addTargetSpecificPasses(PassManagerBase &PM) const {}
public:
   // Generates code to move argument registers, unmap memory above and below the
   // snippet, and map the auxiliary memory into the subprocess. The code
   // generated by this function may clobber registers.
   virtual std::vector<MCInst> generateMemoryInitialSetup() const {
     report_fatal_error("generateMemoryInitialSetup is not supported on the "
                        "current architecture\n");
   }
 
+  // Returns true if all features are available that are required by Opcode.
+  virtual bool isOpcodeAvailable(unsigned Opcode,
+                                 const FeatureBitset &Features) const {
+    return IsOpcodeAvailable(Opcode, Features);
+  }
+
   // Sets the stack register to the auxiliary memory so that operations
   // requiring the stack can be formed (e.g., setting large registers). The code
   // generated by this function may clobber registers.
   virtual std::vector<MCInst> setStackRegisterToAuxMem() const {
     report_fatal_error("setStackRegisterToAuxMem is not implemented on the "
                        "current architectures");
   }
 
std::unique_ptr<BenchmarkRunner> virtual createLatencyBenchmarkRunner(
       BenchmarkRunner::ExecutionModeE ExecutionMode) const;
   std::unique_ptr<BenchmarkRunner> virtual createUopsBenchmarkRunner(
       const LLVMState &State, BenchmarkPhaseSelectorE BenchmarkPhaseSelector,
       Benchmark::ResultAggregationModeE ResultAggMode,
       BenchmarkRunner::ExecutionModeE ExecutionMode) const;
 
   const ExegesisTarget *Next = nullptr;
   const ArrayRef<CpuAndPfmCounters> CpuPfmCounters;
+  const OpcodeAvailabilityChecker IsOpcodeAvailable;
 };
 
 } // namespace exegesis
 } // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H

llvm/tools/llvm-exegesis/lib/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "Target.h"
 
 #include "LatencyBenchmarkRunner.h"
 #include "ParallelSnippetGenerator.h"
 #include "PerfHelper.h"
 #include "SerialSnippetGenerator.h"
 #include "UopsBenchmarkRunner.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/Error.h"
+#include "llvm/TargetParser/SubtargetFeature.h"
 
 namespace llvm {
 namespace exegesis {
 
 cl::OptionCategory Options("llvm-exegesis options");
 cl::OptionCategory BenchmarkOptions("llvm-exegesis benchmark options");
 cl::OptionCategory AnalysisOptions("llvm-exegesis analysis options");
 

 const PfmCountersInfo &ExegesisTarget::getDummyPfmCounters() const {
   return PfmCountersInfo::Dummy;
 }
 
 ExegesisTarget::SavedState::~SavedState() {} // anchor.
 
 namespace {
 
+bool opcodeIsNotAvailable(unsigned, const FeatureBitset &) { return false; }
+
 // Default implementation.
 class ExegesisDefaultTarget : public ExegesisTarget {
 public:
-  ExegesisDefaultTarget() : ExegesisTarget({}) {}
+  ExegesisDefaultTarget() : ExegesisTarget({}, opcodeIsNotAvailable) {}
 
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override {
     llvm_unreachable("Not yet implemented");
   }
 
   bool matchesArch(Triple::ArchType Arch) const override {

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

 #endif
 
 #ifdef __linux__
 #include <sys/mman.h>
 #include <sys/syscall.h>
 #include <unistd.h>
 #endif
 
+#define GET_AVAILABLE_OPCODE_CHECKER
+#include "X86GenInstrInfo.inc"
+
 namespace llvm {
 namespace exegesis {
 
 // If a positive value is specified, we are going to use the LBR in
 // latency-mode.
 //
 // Note:
 //  -  A small value is preferred, but too low a value could result in

 #if defined(__x86_64__) || defined(_M_X64)
   alignas(16) char FPState[512];
   uint64_t Eflags;
 #endif
 };
 
 class ExegesisX86Target : public ExegesisTarget {
 public:
-  ExegesisX86Target() : ExegesisTarget(X86CpuPfmCounters) {}
+  ExegesisX86Target()
+      : ExegesisTarget(X86CpuPfmCounters, X86_MC::isOpcodeAvailable) {}
 
   Expected<std::unique_ptr<pfm::Counter>>
   createCounter(StringRef CounterName, const LLVMState &State,
                 const pid_t ProcessID) const override {
     // If LbrSamplingPeriod was provided, then ignore the
     // CounterName because we only have one for LBR.
     if (LbrSamplingPeriod > 0) {
       // Can't use LBR without HAVE_LIBPFM, LIBPFM_HAS_FIELD_CYCLES, or without

llvm/tools/llvm-exegesis/llvm-exegesis.cpp

 
 // Checks that only one of OpcodeNames, OpcodeIndex or SnippetsFile is provided,
 // and returns the opcode indices or {} if snippets should be read from
 // `SnippetsFile`.
 static std::vector<unsigned> getOpcodesOrDie(const LLVMState &State) {
   const size_t NumSetFlags = (OpcodeNames.empty() ? 0 : 1) +
                              (OpcodeIndex == 0 ? 0 : 1) +
                              (SnippetsFile.empty() ? 0 : 1);
+  const auto &ET = State.getExegesisTarget();
+  const auto AvailableFeatures = State.getSubtargetInfo().getFeatureBits();
+
   if (NumSetFlags != 1) {
     ExitOnErr.setBanner("llvm-exegesis: ");
     ExitWithError("please provide one and only one of 'opcode-index', "
                   "'opcode-name' or 'snippets-file'");
   }
   if (!SnippetsFile.empty())
     return {};
   if (OpcodeIndex > 0)
     return {static_cast<unsigned>(OpcodeIndex)};
   if (OpcodeIndex < 0) {
     std::vector<unsigned> Result;
     unsigned NumOpcodes = State.getInstrInfo().getNumOpcodes();
     Result.reserve(NumOpcodes);
-    for (unsigned I = 0, E = NumOpcodes; I < E; ++I)
+    for (unsigned I = 0, E = NumOpcodes; I < E; ++I) {
+      if (!ET.isOpcodeAvailable(I, AvailableFeatures))
+        continue;
       Result.push_back(I);
+    }
     return Result;
   }
   // Resolve opcode name -> opcode.
   const auto ResolveName = [&State](StringRef OpcodeName) -> unsigned {
     const auto &Map = State.getOpcodeNameToOpcodeIdxMapping();
     auto I = Map.find(OpcodeName);
     if (I != Map.end())
       return I->getSecond();

llvm/utils/TableGen/InstrInfoEmitter.cpp

 }
 
 void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
                                            const CodeGenTarget &Target) {
   const auto &All = SubtargetFeatureInfo::getAll(Records);
   std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
   SubtargetFeatures.insert(All.begin(), All.end());
 
-  OS << "#if defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)\n"
+  OS << "#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) "
+     << "||\\\n"
+     << "    defined(GET_AVAILABLE_OPCODE_CHECKER)\n"
      << "#define GET_COMPUTE_FEATURES\n"
      << "#endif\n";
   OS << "#ifdef GET_COMPUTE_FEATURES\n"
      << "#undef GET_COMPUTE_FEATURES\n"
      << "namespace llvm {\n"
      << "namespace " << Target.getName() << "_MC {\n\n";
 
   // Emit the subtarget feature enumeration.
OS << "  };\n\n"
      << "  assert(Opcode < " << InstIdx << ");\n"
      << "  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];\n"
      << "}\n\n";
 
   OS << "} // end namespace " << Target.getName() << "_MC\n"
      << "} // end namespace llvm\n"
      << "#endif // GET_COMPUTE_FEATURES\n\n";
 
+  OS << "#ifdef GET_AVAILABLE_OPCODE_CHECKER\n"
+     << "#undef GET_AVAILABLE_OPCODE_CHECKER\n"
+     << "namespace llvm {\n"
+     << "namespace " << Target.getName() << "_MC {\n";
+  OS << "bool isOpcodeAvailable("
+     << "unsigned Opcode, const FeatureBitset &Features) {\n"
+     << "  FeatureBitset AvailableFeatures = "
+     << "computeAvailableFeatures(Features);\n"
+     << "  FeatureBitset RequiredFeatures = "
+     << "computeRequiredFeatures(Opcode);\n"
+     << "  FeatureBitset MissingFeatures =\n"
+     << "      (AvailableFeatures & RequiredFeatures) ^\n"
+     << "      RequiredFeatures;\n"
+     << "  return !MissingFeatures.any();\n"
+     << "}\n";
+  OS << "} // end namespace " << Target.getName() << "_MC\n"
+     << "} // end namespace llvm\n"
+     << "#endif // GET_AVAILABLE_OPCODE_CHECKER\n\n";
+
   OS << "#ifdef ENABLE_INSTR_PREDICATE_VERIFIER\n"
      << "#undef ENABLE_INSTR_PREDICATE_VERIFIER\n"
      << "#include <sstream>\n\n";
 
   OS << "namespace llvm {\n";
   OS << "namespace " << Target.getName() << "_MC {\n\n";
 
   // Emit the name table for error messages.