[MachineOutliner] Add IsOutlined to MachineFunction

[• pcwang-thead]

Summary

We add a field IsOutlined to indicate whether a MachineFunction
is outlined and set it true for outlined functions in MachineOutliner.

[craig.topper]

llvm/include/llvm/CodeGen/MachineFunction.h

377

If we add this property, it needs to be connected to MIR parsing and printing.

[jrtc27]

Is there a reason we can't instead add the right live-outs?

[• pcwang-thead]

In D146191#4201151, @jrtc27 wrote:

Is there a reason we can't instead add the right live-outs?

I tried, but it seems to be hard.
We call these outlined functions as function, but they are just shared code fragments with only one basic block. There are some differences between normal functions and outlined functions:

1. For outlined functions, they end with a JALR instruction (in which isReturn is false); while for normal functions, they end with a PseudoRET (in which isReturn is true). So the only basic block in outlined function is not ReturnBlock(See MachineBasicBlock::isReturnBlock()).
2. For normal functions, the live-outs of ReturnBlock are callee-saved registers and return value(s)? (IIUC, correct me if I am wrong). But all defs in outlined functions should be live.

I digged into LivePhysRegs.cpp and I could't find a way to add live-outs manually.

[• pcwang-thead]

Add MIR parsing and printing.

[craig.topper]

Do the T-Head specific pseudos being expanded need to expanded as late as the other pseudos? Could you have an earlier expansion pass? I was already nervous about the short forward branch instructions being affected before. I know we determined those cases were ok.

[• pcwang-thead]

In D146191#4225567, @craig.topper wrote:

Do the T-Head specific pseudos being expanded need to expanded as late as the other pseudos? Could you have an earlier expansion pass? I was already nervous about the short forward branch instructions being affected before. I know we determined those cases were ok.

Yes and thanks, I just tried. They can be placed in addPreEmitPass() just like MCP.
Apart from this, do you think it's still worthy marking outlined functions?

[asb]

In D146191#4226495, @pcwang-thead wrote:

In D146191#4225567, @craig.topper wrote:

Do the T-Head specific pseudos being expanded need to expanded as late as the other pseudos? Could you have an earlier expansion pass? I was already nervous about the short forward branch instructions being affected before. I know we determined those cases were ok.

Yes and thanks, I just tried. They can be placed in addPreEmitPass() just like MCP.
Apart from this, do you think it's still worthy marking outlined functions?

For my part, I'd be really interested in @paquette's thoughts on this.

[paquette]

In D146191#4227164, @asb wrote:

In D146191#4226495, @pcwang-thead wrote:

In D146191#4225567, @craig.topper wrote:

Do the T-Head specific pseudos being expanded need to expanded as late as the other pseudos? Could you have an earlier expansion pass? I was already nervous about the short forward branch instructions being affected before. I know we determined those cases were ok.

Yes and thanks, I just tried. They can be placed in addPreEmitPass() just like MCP.
Apart from this, do you think it's still worthy marking outlined functions?

For my part, I'd be really interested in @paquette's thoughts on this.

If you mean adding the IsOutlined field, I think that it's a good idea. Currently the only way to recognize if a function is outlined is to look at its name, which isn't great. The field is an improvement.

I think it needs a small MIR testcase though. :)

[asb]

Thanks Jessica - in that case, LGTM once it has the MIR test case Jessica requested.

[craig.topper]

In D146191#4230864, @asb wrote:

Thanks Jessica - in that case, LGTM once it has the MIR test case Jessica requested.

I thought the earlier conclusion was that the RISC-V part wasn’t needed if T-Head moves their pseudo expansion in their downstream.

[asb]

In D146191#4230950, @craig.topper wrote:

In D146191#4230864, @asb wrote:

Thanks Jessica - in that case, LGTM once it has the MIR test case Jessica requested.

I thought the earlier conclusion was that the RISC-V part wasn’t needed if T-Head moves their pseudo expansion in their downstream.

Yes, let's drop the RISC-V part of this if there's not a good motivation for running MCP so late.

[• pcwang-thead]

Remove MCP parts and add MIR test.

I didn't find a target-independent way to test this, so I add some CHECKs to existed RISCV test.

[• pcwang-thead]

Ping. :-)

[paquette]

LGTM!

llvm/include/llvm/CodeGen/MIRYamlMapping.h

struct MachineFunction {
   bool TracksRegLiveness = false;
   bool HasWinCFI = false;
 
   bool CallsEHReturn = false;
   bool CallsUnwindInit = false;
   bool HasEHCatchret = false;
   bool HasEHScopes = false;
   bool HasEHFunclets = false;
+  bool IsOutlined = false;
 
   bool FailsVerification = false;
   bool TracksDebugUserValues = false;
   bool UseDebugInstrRef = false;
   std::vector<VirtualRegisterDefinition> VirtualRegisters;
   std::vector<MachineFunctionLiveIn> LiveIns;
   std::optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
   // TODO: Serialize the various register masks.
static void mapping(IO &YamlIO, MachineFunction &MF) {
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false);
     YamlIO.mapOptional("hasWinCFI", MF.HasWinCFI, false);
 
     YamlIO.mapOptional("callsEHReturn", MF.CallsEHReturn, false);
     YamlIO.mapOptional("callsUnwindInit", MF.CallsUnwindInit, false);
     YamlIO.mapOptional("hasEHCatchret", MF.HasEHCatchret, false);
     YamlIO.mapOptional("hasEHScopes", MF.HasEHScopes, false);
     YamlIO.mapOptional("hasEHFunclets", MF.HasEHFunclets, false);
+    YamlIO.mapOptional("isOutlined", MF.IsOutlined, false);
     YamlIO.mapOptional("debugInstrRef", MF.UseDebugInstrRef, false);
 
     YamlIO.mapOptional("failsVerification", MF.FailsVerification, false);
     YamlIO.mapOptional("tracksDebugUserValues", MF.TracksDebugUserValues,
                        false);
     YamlIO.mapOptional("registers", MF.VirtualRegisters,
                        std::vector<VirtualRegisterDefinition>());
     YamlIO.mapOptional("liveins", MF.LiveIns,

llvm/include/llvm/CodeGen/MachineFunction.h

class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   /// CodeView label annotations.
   std::vector<std::pair<MCSymbol *, MDNode *>> CodeViewAnnotations;
 
   bool CallsEHReturn = false;
   bool CallsUnwindInit = false;
   bool HasEHCatchret = false;
   bool HasEHScopes = false;
   bool HasEHFunclets = false;
+  bool IsOutlined = false;
 
   /// BBID to assign to the next basic block of this function.
   unsigned NextBBID = 0;
 
   /// Section Type for basic blocks, only relevant with basic block sections.
   BasicBlockSection BBSectionsType = BasicBlockSection::None;
 
   /// List of C++ TypeInfo used.
public:
   void setHasEHCatchret(bool V) { HasEHCatchret = V; }
 
   bool hasEHScopes() const { return HasEHScopes; }
   void setHasEHScopes(bool V) { HasEHScopes = V; }
 
   bool hasEHFunclets() const { return HasEHFunclets; }
   void setHasEHFunclets(bool V) { HasEHFunclets = V; }
 
+  bool isOutlined() const { return IsOutlined; }
+  void setIsOutlined(bool V) { IsOutlined = V; }
+
   /// Find or create an LandingPadInfo for the specified MachineBasicBlock.
   LandingPadInfo &getOrCreateLandingPadInfo(MachineBasicBlock *LandingPad);
 
   /// Return a reference to the landing pad info for the current function.
   const std::vector<LandingPadInfo> &getLandingPads() const {
     return LandingPads;
   }
 

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasWinCFI(YamlMF.HasWinCFI);
 
   MF.setCallsEHReturn(YamlMF.CallsEHReturn);
   MF.setCallsUnwindInit(YamlMF.CallsUnwindInit);
   MF.setHasEHCatchret(YamlMF.HasEHCatchret);
   MF.setHasEHScopes(YamlMF.HasEHScopes);
   MF.setHasEHFunclets(YamlMF.HasEHFunclets);
+  MF.setIsOutlined(YamlMF.IsOutlined);
 
   if (YamlMF.Legalized)
     MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
   if (YamlMF.RegBankSelected)
     MF.getProperties().set(
         MachineFunctionProperties::Property::RegBankSelected);
   if (YamlMF.Selected)
     MF.getProperties().set(MachineFunctionProperties::Property::Selected);

llvm/lib/CodeGen/MIRPrinter.cpp

void MIRPrinter::print(const MachineFunction &MF) {
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasWinCFI = MF.hasWinCFI();
 
   YamlMF.CallsEHReturn = MF.callsEHReturn();
   YamlMF.CallsUnwindInit = MF.callsUnwindInit();
   YamlMF.HasEHCatchret = MF.hasEHCatchret();
   YamlMF.HasEHScopes = MF.hasEHScopes();
   YamlMF.HasEHFunclets = MF.hasEHFunclets();
+  YamlMF.IsOutlined = MF.isOutlined();
   YamlMF.UseDebugInstrRef = MF.useDebugInstrRef();
 
   YamlMF.Legalized = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Legalized);
   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
   YamlMF.Selected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Selected);

llvm/lib/CodeGen/MachineOutliner.cpp

if (UW != UWTableKind::None)
     F->setUWTableKind(UW);
 
   BasicBlock *EntryBB = BasicBlock::Create(C, "entry", F);
   IRBuilder<> Builder(EntryBB);
   Builder.CreateRetVoid();
 
   MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
   MachineFunction &MF = MMI.getOrCreateMachineFunction(*F);
+  MF.setIsOutlined(true);
   MachineBasicBlock &MBB = *MF.CreateMachineBasicBlock();
 
   // Insert the new function into the module.
   MF.insert(MF.begin(), &MBB);
 
   MachineFunction *OriginalMF = FirstCand.front()->getMF();
   const std::vector<MCCFIInstruction> &Instrs =
       OriginalMF->getFrameInstructions();

llvm/test/CodeGen/RISCV/machineoutliner.mir

 # RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
-# RUN: | FileCheck -check-prefix=RV32I-MO %s
+# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s
 # RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
-# RUN: | FileCheck -check-prefix=RV64I-MO %s
+# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s
 
 --- |
   define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }
 
   define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }
 
   define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }
 
   ; Should not outline linkonce_odr functions which could be deduplicated by the
   ; linker.
   define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 }
 
   ; Should not outline functions with named linker sections
   define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 }
 
   ; Cannot outline if the X5 (t0) register is not free
   define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 }
 
 ...
 ---
 name:            outline_0
 tracksRegLiveness: true
+isOutlined: false
 body:             |
   bb.0:
     liveins: $x10, $x11
     ; RV32I-MO-LABEL: name: outline_0
     ; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     ;
     ; RV64I-MO-LABEL: name: outline_0
     ; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     $x11 = ORI $x11, 1023
     $x12 = ADDI $x10, 17
     $x11 = AND $x12, $x11
     $x10 = SUB $x10, $x11
     PseudoRET implicit $x10
 
 ...
 ---
 name:            outline_1
 tracksRegLiveness: true
+isOutlined: false
 body:             |
   bb.0:
     liveins: $x10, $x11
     ; RV32I-MO-LABEL: name: outline_1
     ; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     ;
     ; RV64I-MO-LABEL: name: outline_1
     ; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     $x11 = ORI $x11, 1023
     $x12 = ADDI $x10, 17
     $x11 = AND $x12, $x11
     $x10 = SUB $x10, $x11
     PseudoRET implicit $x10
 
 ...
 ---
 name:            outline_2
 tracksRegLiveness: true
+isOutlined: false
 body:             |
   bb.0:
     liveins: $x10, $x11
     ; RV32I-MO-LABEL: name: outline_2
     ; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     ;
     ; RV64I-MO-LABEL: name: outline_2
     ; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     $x11 = ORI $x11, 1023
     $x12 = ADDI $x10, 17
     $x11 = AND $x12, $x11
     $x10 = SUB $x10, $x11
     PseudoRET implicit $x10
 
 ...
 ---
 name:            dont_outline_0
 tracksRegLiveness: true
+isOutlined: false
 body:             |
   bb.0:
     liveins: $x10, $x11
     ; RV32I-MO-LABEL: name: dont_outline_0
     ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     ;
     ; RV64I-MO-LABEL: name: dont_outline_0
     ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     $x11 = ORI $x11, 1023
     $x12 = ADDI $x10, 17
     $x11 = AND $x12, $x11
     $x10 = SUB $x10, $x11
     PseudoRET implicit $x10
 
 ...
 ---
 name:            dont_outline_1
 tracksRegLiveness: true
+isOutlined: false
 body:             |
   bb.0:
     liveins: $x10, $x11
     ; RV32I-MO-LABEL: name: dont_outline_1
     ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     ;
     ; RV64I-MO-LABEL: name: dont_outline_1
     ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     $x11 = ORI $x11, 1023
     $x12 = ADDI $x10, 17
     $x11 = AND $x12, $x11
     $x10 = SUB $x10, $x11
     PseudoRET implicit $x10
 
 ...
 ---
 name:            dont_outline_2
 tracksRegLiveness: true
+isOutlined: false
 body:             |
   bb.0:
     liveins: $x10, $x11, $x5
     ; RV32I-MO-LABEL: name: dont_outline_2
     ; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     ;
     ; RV64I-MO-LABEL: name: dont_outline_2
     ; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
     $x11 = ORI $x11, 1023
     $x12 = ADDI $x10, 17
     $x11 = AND $x12, $x11
     $x10 = SUB $x10, $x11
     $x10 = ADD $x10, $x5
     PseudoRET implicit $x10
 
 ...
+
+# CHECK-LABEL: name: OUTLINED_FUNCTION_0
+# CHECK: isOutlined: true

llvm/tools/llvm-reduce/ReducerWorkItem.cpp

if (!SrcMF->getFrameInstructions().empty() ||
       !SrcMF->getCatchretTargets().empty())
     report_fatal_error("cloning not implemented for machine function property");
 
   DstMF->setCallsEHReturn(SrcMF->callsEHReturn());
   DstMF->setCallsUnwindInit(SrcMF->callsUnwindInit());
   DstMF->setHasEHCatchret(SrcMF->hasEHCatchret());
   DstMF->setHasEHScopes(SrcMF->hasEHScopes());
   DstMF->setHasEHFunclets(SrcMF->hasEHFunclets());
+  DstMF->setIsOutlined(SrcMF->isOutlined());
 
   if (!SrcMF->getLandingPads().empty() ||
       !SrcMF->getCodeViewAnnotations().empty() ||
       !SrcMF->getTypeInfos().empty() ||
       !SrcMF->getFilterIds().empty() ||
       SrcMF->hasAnyWasmLandingPadIndex() ||
       SrcMF->hasAnyCallSiteLandingPad() ||
       SrcMF->hasAnyCallSiteLabel() ||