[RuntimeDyld][ELF] Add minimal RISC-V support

[jobnoorman]

Summary

This patch is part of implementing initial RISC-V support in BOLT.

I understand from other discussions (e.g. D127842, D98560) that JITLink
might be preferred over RuntimeDyld in general. However, since BOLT
still uses RuntimeDyld, adding minimal RISC-V support to it seems the
easiest way forward for now.

The following relocations are implemented:

• R_RISCV_CALL(_PLT)
• R_RISCV_GOT_HI20
• R_RISCV_PCREL_HI20
• R_RISCV_PCREL_LO12_I
• R_RISCV_32_PCREL
• R_RISCV_ADD32
• R_RISCV_SUB32

Most are fairly straightforward. The exception is R_RISCV_PCREL_LO12_I,
which is a relocation that refers to a corresponding *HI20 one (i.e.,
the symbol it refers to points to an instruction with a *HI20
relocation). In order to implement this, a member (PCRelHIRelocs) was
added to the RuntimeDyldELF class that maps offsets with a *HI20
relocation to their target address. Whenever a LO12 relocations is
encountered, this map is queried in order to find its target. Note that
this assumes that *HI20 relocations are processed before the
corresponding LO12 one. This seems to hold for my test cases but I'm not
entirely sure if this is actually guaranteed.

This patch also contains test cases for all relocations. However, there
is an issue with testing R_RISCV_32_PCREL: llvm-mc only emits this for
.eh_frame sections and uses unnamed symbols there. Since the symbol
lookup in RuntimeDyld seems to be based only on symbol names, these
symbols don't get resolved properly (Value is always 0).

This is not really a problem for the initial BOLT bring-up since we can
test on code that doesn't need .eh_frames. However, since GCC's startup
code contains them, we need to handle them somehow.

Note that I have included a (disabled) test case for R_RISCV_32_PCREL
relocations that passes if llvm-mc is modified to use section-relative
relocations in .eh_frame. I'm not sure if it makes sense to keep it in
this patch though.

[jobnoorman]

Friendly ping.

[lhames]

Is there something preventing Bolt from moving to ORC / JITLink? If Bolt is able to move over then the aim should be to do that. If Bolt is unable to move over then we need to know why so that we can address the issue. RuntimeDyld is very much in maintenance mode at the moment, and we're working hard to reach parity in backend coverage so that we can officially deprecate it.

None of that is a total blocker to landing this, but the bar is high, and it should be understood that Bolt will need to migrate in the future.

[rafauler]

In D145686#4222642, @lhames wrote:

Is there something preventing Bolt from moving to ORC / JITLink? If Bolt is able to move over then the aim should be to do that. If Bolt is unable to move over then we need to know why so that we can address the issue. RuntimeDyld is very much in maintenance mode at the moment, and we're working hard to reach parity in backend coverage so that we can officially deprecate it.

None of that is a total blocker to landing this, but the bar is high, and it should be understood that Bolt will need to migrate in the future.

Hi @lhames , is JITLink mature for X86 and AArch64? Those are the two requirements for BOLT.

[lhames]

In D145686#4225806, @rafauler wrote:

In D145686#4222642, @lhames wrote:

Is there something preventing Bolt from moving to ORC / JITLink? If Bolt is able to move over then the aim should be to do that. If Bolt is unable to move over then we need to know why so that we can address the issue. RuntimeDyld is very much in maintenance mode at the moment, and we're working hard to reach parity in backend coverage so that we can officially deprecate it.

None of that is a total blocker to landing this, but the bar is high, and it should be understood that Bolt will need to migrate in the future.

Hi @lhames , is JITLink mature for X86 and AArch64? Those are the two requirements for BOLT.

@rafaelauler JITLink's MachO x86_64 and aarch64 backends are mature. ELF x86_64 and aarch64 are mature for PIC, but may be missing some static relocations. These relocations can easily be added if needed, and should not be considered a blocker to moving over.

COFF x86-64 is solid (though new). I believe JITLink's support for it is already strictly better than RuntimeDyld's. COFF/aarch64 hasn't been added yet, but should be doable if you need it.

[jobnoorman]

BOLT's JITLink port has been accepted (D147544) so I will close this.

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

void resolvePPC64Relocation(const SectionEntry &Section, uint64_t Offset,
                               uint64_t Value, uint32_t Type, int64_t Addend);
 
   void resolveSystemZRelocation(const SectionEntry &Section, uint64_t Offset,
                                 uint64_t Value, uint32_t Type, int64_t Addend);
 
   void resolveBPFRelocation(const SectionEntry &Section, uint64_t Offset,
                             uint64_t Value, uint32_t Type, int64_t Addend);
 
+  void resolveRISCVRelocation(const SectionEntry &Section, uint64_t Offset,
+                              uint64_t Value, uint32_t Type, int64_t Addend,
+                              SID SectionID);
+
   unsigned getMaxStubSize() const override {
     if (Arch == Triple::aarch64 || Arch == Triple::aarch64_be)
       return 20; // movz; movk; movk; movk; br
     if (Arch == Triple::arm || Arch == Triple::thumb)
       return 8; // 32-bit instruction and 32-bit address
     else if (IsMipsO32ABI || IsMipsN32ABI)
       return 16;
     else if (IsMipsN64ABI)

 private:
   // A map to avoid duplicate got entries (Mips64 specific)
   StringMap<uint64_t> GOTSymbolOffsets;
 
   // *HI16 relocations will be added for resolving when we find matching
   // *LO16 part. (Mips specific)
   SmallVector<std::pair<RelocationValueRef, RelocationEntry>, 8> PendingRelocs;
 
+  // Mapping from *HI20 relocations to their PC-relative target. Used to resolve
+  // the corresponding *LO12 relocations. RISC-V specific.
+  SmallVector<std::pair<RelocationValueRef, uint64_t>, 8> PCRelHIRelocs;
+
   // When a module is loaded we save the SectionID of the EH frame section
   // in a table until we receive a request to register all unregistered
   // EH frame sections with the memory manager.
   SmallVector<SID, 2> UnregisteredEHFrameSections;
 
   // Map between GOT relocation value and corresponding GOT offset
   std::map<RelocationValueRef, uint64_t> GOTOffsetMap;
 

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

case ELF::R_BPF_64_ABS32: {
     write(isBE, Section.getAddressWithOffset(Offset), static_cast<uint32_t>(Value));
     LLVM_DEBUG(dbgs() << "Writing " << format("%p", Value) << " at "
                       << format("%p\n", Section.getAddressWithOffset(Offset)));
     break;
   }
   }
 }
 
+static void applyUpperImmRISCV(uint8_t *InstrAddr, uint32_t Imm) {
+  uint32_t UpperImm = (Imm + 0x800) & 0xfffff000;
+  auto Instr = support::ulittle32_t::ref(InstrAddr);
+  Instr = (Instr & 0xfff) | UpperImm;
+}
+
+static void applyLowerImmRISCV(uint8_t *InstrAddr, uint32_t Imm) {
+  uint32_t LowerImm = Imm & 0xfff;
+  auto Instr = support::ulittle32_t::ref(InstrAddr);
+  Instr = (Instr & 0xfffff) | (LowerImm << 20);
+}
+
+void RuntimeDyldELF::resolveRISCVRelocation(const SectionEntry &Section,
+                                            uint64_t Offset, uint64_t Value,
+                                            uint32_t Type, int64_t Addend,
+                                            SID SectionID) {
+  switch (Type) {
+  default:
+    llvm_unreachable("unimplemented reloc");
+  case ELF::R_RISCV_CALL:
+  case ELF::R_RISCV_CALL_PLT: {
+    uint64_t PC = Section.getLoadAddressWithOffset(Offset);
+    uint64_t PCOffset = Value + Addend - PC;
+    applyUpperImmRISCV(Section.getAddressWithOffset(Offset), PCOffset);
+    applyLowerImmRISCV(Section.getAddressWithOffset(Offset + 4), PCOffset);
+    break;
+  }
+  case ELF::R_RISCV_GOT_HI20:
+  case ELF::R_RISCV_PCREL_HI20: {
+    uint64_t PC = Section.getLoadAddressWithOffset(Offset);
+    uint64_t PCOffset = Value + Addend - PC;
+    applyUpperImmRISCV(Section.getAddressWithOffset(Offset), PCOffset);
+    auto ValueRef = RelocationValueRef{SectionID, Offset};
+    PCRelHIRelocs.push_back(std::make_pair(ValueRef, PCOffset));
+    break;
+  }
+  case ELF::R_RISCV_PCREL_LO12_I: {
+    uint64_t HIOffset = Addend;
+
+    for (auto I = PCRelHIRelocs.begin(), E = PCRelHIRelocs.end(); I != E; ++I) {
+      auto &Rel = I->first;
+
+      if (Rel.SectionID == SectionID && Rel.Offset == HIOffset) {
+        auto PCOffset = I->second;
+        applyLowerImmRISCV(Section.getAddressWithOffset(Offset), PCOffset);
+        return;
+      }
+    }
+
+    llvm_unreachable(
+        "R_RISCV_PCREL_LO12_I without matching R_RISCV_PCREL_HI20");
+  }
+  case ELF::R_RISCV_32_PCREL: {
+    uint64_t FinalAddress = Section.getLoadAddressWithOffset(Offset);
+    int64_t RealOffset = Value + Addend - FinalAddress;
+    int32_t TruncOffset = (RealOffset & 0xffffffff);
+    support::ulittle32_t::ref(Section.getAddressWithOffset(Offset)) =
+        TruncOffset;
+    break;
+  }
+  case ELF::R_RISCV_ADD32: {
+    auto Ref = support::ulittle32_t::ref(Section.getAddressWithOffset(Offset));
+    Ref = Ref + Value + Addend;
+    break;
+  }
+  case ELF::R_RISCV_SUB32: {
+    auto Ref = support::ulittle32_t::ref(Section.getAddressWithOffset(Offset));
+    Ref = Ref - Value - Addend;
+    break;
+  }
+  }
+}
+
 // The target location for the relocation is described by RE.SectionID and
 // RE.Offset.  RE.SectionID can be used to find the SectionEntry.  Each
 // SectionEntry has three members describing its location.
 // SectionEntry::Address is the address at which the section has been loaded
 // into memory in the current (host) process.  SectionEntry::LoadAddress is the
 // address that the section will have in the target process.
 // SectionEntry::ObjAddress is the address of the bits for this section in the
 // original emitted object image (also in the current address space).
case Triple::ppc64le:
     break;
   case Triple::systemz:
     resolveSystemZRelocation(Section, Offset, Value, Type, Addend);
     break;
   case Triple::bpfel:
   case Triple::bpfeb:
     resolveBPFRelocation(Section, Offset, Value, Type, Addend);
     break;
+  case Triple::riscv32:
+  case Triple::riscv64:
+    resolveRISCVRelocation(Section, Offset, Value, Type, Addend, SectionID);
+    break;
   default:
     llvm_unreachable("Unsupported CPU type!");
   }
 }
 
 void *RuntimeDyldELF::computePlaceholderAddress(unsigned SectionID, uint64_t Offset) const {
   return (void *)(Sections[SectionID].getObjAddress() + Offset);
 }

llvm/test/ExecutionEngine/RuntimeDyld/RISCV/ELF_RISCV_relocations.s

+# RUN: rm -rf %t && mkdir -p %t
+# RUN: llvm-mc -triple=riscv64-linux-elf -filetype=obj -o %t/reloc.o %s
+# RUN: llvm-rtdyld -triple=riscv64-linux-elf -verify -dummy-extern f=0x12345678 -dummy-extern d=0xabcdef12 -check=%s %t/reloc.o
+
+# RUN: rm -rf %t && mkdir -p %t
+# RUN: llvm-mc -triple=riscv32-linux-elf -filetype=obj -o %t/reloc.o %s
+# RUN: llvm-rtdyld -triple=riscv32-linux-elf -verify -dummy-extern f=0x12345678 -dummy-extern d=0xabcdef12 -check=%s %t/reloc.o
+
+    .skip 0x1234
+    .p2align 2
+g:
+# R_RISCV_CALL_PLT
+    call f
+
+h:
+# R_RISCV_PCREL_HI20
+# R_RISCV_PCREL_LO12_I
+    la t0, d
+
+a:
+# R_RISCV_ADD32
+# R_RISCV_SUB32
+    .word h-g
+
+b:
+# R_RISCV_32_PCREL
+    .cfi_startproc
+    nop
+    .cfi_endproc
+
+## Check R_RISCV_CALL_PLT
+# rtdyld-check: (*{4}g)[31:12] = (f-g+0x800)[31:12]
+# rtdyld-check: (*{4}(g+4))[31:20] = (f-g)[11:0]
+
+## Check R_RISCV_PCREL_HI20
+# rtdyld-check: (*{4}h)[31:12] = (d-h+0x800)[31:12]
+
+## Check R_RISCV_PCREL_LO12_I
+# rtdyld-check: (*{4}(h+4))[31:20] = (d-h)[11:0]
+
+## Check R_RISCV_ADD32 and R_RISCV_SUB32
+# rtdyld-check: *{4}a = (h-g)
+
+## Check R_RISCV_32_PCREL added to .eh_frame+0x1c
+## NOTE disabled because unnamed symbols in .eh_frame do not get resolved
+## rtdyld-check: *{4}(section_addr(reloc.o, .eh_frame) + 0x1c) = (b - (section_addr(reloc.o, .eh_frame) + 0x1c))[31:0]
+

llvm/test/ExecutionEngine/RuntimeDyld/RISCV/lit.local.cfg

+if not 'RISCV' in config.root.targets:
+    config.unsupported = True