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Differential D145185

[AArch64] Fix crash in LowerBUILD_VECTOR trying to create invalid EXTRACT_SUBVECTOR.
ClosedPublic

Authored by aemerson on Mar 2 2023, 1:55 PM.

Details

Reviewers
dmgreen
t.p.northover
fhahn
Commits
rG1e1f1195a8bf: [AArch64] Fix crash in LowerBUILD_VECTOR trying to create invalid…
Summary

This fixes and assertion and miscompile due to falling through to the code that tries to use EXTRACT_SUBVECTOR, even when we bailed out due to having a non-constant extract operand.

rdar://106096671

Diff Detail

Unit TestsFailed

TimeTest
60,060 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

aemerson created this revision.Mar 2 2023, 1:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2023, 1:55 PM
Herald added subscribers: StephenFan, hiraditya, kristof.beyls. · View Herald Transcript
aemerson requested review of this revision.Mar 2 2023, 1:55 PM
dmgreen accepted this revision.Mar 2 2023, 2:02 PM

Sounds good to me.

This revision is now accepted and ready to land.Mar 2 2023, 2:02 PM
This revision was landed with ongoing or failed builds.Mar 2 2023, 2:10 PM
Closed by commit rG1e1f1195a8bf: [AArch64] Fix crash in LowerBUILD_VECTOR trying to create invalid… (authored by aemerson). · Explain Why
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rG1e1f1195a8bf: [AArch64] Fix crash in LowerBUILD_VECTOR trying to create invalid….
Harbormaster completed remote builds in B217045: Diff 501970.Mar 2 2023, 3:25 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
5 lines
test/
CodeGen/
AArch64/
51 lines

Diff 501970

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,991 Lines • ▼ Show 20 Lines
SDNode *Vector = nullptr; SDNode *Vector = nullptr;
bool Even = false; bool Even = false;
bool Odd = false; bool Odd = false;
// Check whether the extract elements match the Even pattern <0,2,4,...> or // Check whether the extract elements match the Even pattern <0,2,4,...> or
// the Odd pattern <1,3,5,...>. // the Odd pattern <1,3,5,...>.
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
SDValue V = Op.getOperand(i); SDValue V = Op.getOperand(i);
const SDNode *N = V.getNode(); const SDNode *N = V.getNode();
if (!isa<ConstantSDNode>(N->getOperand(1))) if (!isa<ConstantSDNode>(N->getOperand(1))) {
Even = false;
Odd = false;
break; break;
}
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
// All elements are extracted from the same vector. // All elements are extracted from the same vector.
if (!Vector) { if (!Vector) {
Vector = N0.getNode(); Vector = N0.getNode();
// Check that the type of EXTRACT_VECTOR_ELT matches the type of // Check that the type of EXTRACT_VECTOR_ELT matches the type of
// BUILD_VECTOR. // BUILD_VECTOR.
if (VT.getVectorElementType() != if (VT.getVectorElementType() !=
▲ Show 20 Lines • Show All 9,991 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/build-vector-to-extract-subvec-crash.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-darwin"
define i32 @widget(i64 %arg, <8 x i16> %arg1) {
; CHECK-LABEL: widget:
; CHECK: // %bb.0: // %bb
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: bfi x10, x0, #1, #3
; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: dup v1.8h, w9
; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: ld1 { v1.h }[1], [x10]
; CHECK-NEXT: str q1, [x8]
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
bb:
%inst = inttoptr i64 %arg to ptr
%inst2 = extractelement <8 x i16> %arg1, i64 0
store i16 %inst2, ptr %inst, align 2
%inst3 = getelementptr i16, ptr %inst, i64 1
%inst4 = getelementptr i16, ptr %inst, i64 2
%inst5 = extractelement <8 x i16> %arg1, i64 0
%inst6 = getelementptr i16, ptr %inst, i64 3
%inst7 = extractelement <8 x i16> zeroinitializer, i64 %arg
store i16 %inst7, ptr %inst3, align 2
%inst8 = extractelement <8 x i16> %arg1, i64 0
store i16 %inst8, ptr %inst4, align 2
store i16 %inst5, ptr %inst6, align 2
%inst9 = extractelement <8 x i16> %arg1, i64 0
%inst10 = getelementptr i16, ptr %inst, i64 4
store i16 %inst9, ptr %inst10, align 2
%inst11 = extractelement <8 x i16> %arg1, i64 0
%inst12 = getelementptr i16, ptr %inst, i64 5
store i16 %inst11, ptr %inst12, align 2
%inst13 = extractelement <8 x i16> %arg1, i64 0
%inst14 = getelementptr i16, ptr %inst, i64 6
store i16 %inst13, ptr %inst14, align 2
%inst15 = extractelement <8 x i16> %arg1, i64 0
%inst16 = getelementptr i16, ptr %inst, i64 7
store i16 %inst15, ptr %inst16, align 2
ret i32 0
}