[DAGCombiner] Add fold for `~x & x` -> `0`

[goldstein.w.n]

Summary

This is generally done by the InstCombine, but can be emitted as an
intermediate step and is cheap to handle.

[goldstein.w.n]

More tests

[RKSimon]

Did you look at performing this inside SimplifyDemandedBits instead?

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6630

Use isBitwiseNot / getBitwiseNotOperand ?

[goldstein.w.n]

In D145143#4164231, @RKSimon wrote:

Did you look at performing this inside SimplifyDemandedBits instead?

Just took a look. Seems to me SimplifyDemandedBits is not really the place to check for patterns between operands, but could move there if you prefer

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6630

Made new helper that uses isBitwiseNot.

[goldstein.w.n]

Use new helper + isBitwiseNot

[RKSimon]

LGTM with a couple of minors

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6628

Don't bother with the helper - just inline the check.

6630

Use VT instead of getScalarValueSizeInBits/getValueType

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6628

Keep areBitwiseNotOfEachother - sorry I didn't see D145177 :)

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6630

Also change for the add patch.

[goldstein.w.n]

Use VT

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitAND(SDNode *N) {
   if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1}))
     return C;
 
   // canonicalize constant to RHS
   if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
       !DAG.isConstantIntBuildVectorOrConstantInt(N1))
     return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
 
+  auto IsAndnXX = [](SDValue Op0, SDValue Op1) {
+    return Op0.getOpcode() == ISD::XOR && Op0.getOperand(0) == Op1 &&
+           isAllOnesOrAllOnesSplat(Op0.getOperand(1));
+  };
+  if (IsAndnXX(N0, N1) || IsAndnXX(N1, N0))
+    return DAG.getConstant(APInt::getZero(N1.getScalarValueSizeInBits()),
+                           SDLoc(N), N1.getValueType());
+
   // fold vector ops
   if (VT.isVector()) {
     if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N)))
       return FoldedVOp;
 
     // fold (and x, 0) -> 0, vector edition
     if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
       // do not return N1, because undef node may exist in N1

llvm/test/CodeGen/X86/andn-x-x.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s
 
 define <2 x i64> @andnp_xx(<2 x i64> %v0) nounwind {
 ; CHECK-LABEL: andnp_xx:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andnps %xmm0, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %x = xor <2 x i64> %v0, <i64 -1, i64 -1>
   %y = and <2 x i64> %v0, %x
   ret <2 x i64> %y
 }
 
 define <2 x i64> @andnp_xx_2(<2 x i64> %v0) nounwind {
 ; CHECK-LABEL: andnp_xx_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andnps %xmm0, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %x = xor <2 x i64> %v0, <i64 -1, i64 -1>
   %y = and <2 x i64> %x, %v0
   ret <2 x i64> %y
 }
 
 define i64 @andn_xx(i64 %v0) nounwind {
 ; CHECK-LABEL: andn_xx:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    notq %rax
-; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %x = xor i64 %v0, -1
   %y = and i64 %v0, %x
   ret i64 %y
 }
 
 define i64 @andn_xx_2(i64 %v0) nounwind {
 ; CHECK-LABEL: andn_xx_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    notq %rax
-; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %x = xor i64 %v0, -1
   %y = and i64 %x, %v0
   ret i64 %y
 }