[mlir][llvm] Add AliasAnalysis and AccessGroup interfaces to intrinsics.

[gysit]

Summary

This revision updates the memcpy, memove, and memset intrinsics to
implement the AliasAnalysis and AccessGroup interfaces. The changes
will enable the import and export of alias scope, tbaa, and
access group metadata attached to these intrinsics. It also
renames the requiresAliasScope flag to requiresAliasAnalysis since
the intrinsics also support tbaa and not only access scope metadata.

The revision still maintains the string based attribute lookup
in the translation from MLIR to LLVMIR. Using the interfaces
instead of the string based lookup is left to a followup revision.

Depends on D144851

[gysit]

@frgossen and @hgreving
https://reviews.llvm.org/D143654 caused problems since with the translation of alias and access group metadata.

https://reviews.llvm.org/D144851 will introduce AliasAnalysisOpInterface and AccessGroupOpInterface. These interfaces will provide access to the access group, alias scope, and tbaa metadata attributes (they also implement verification for these attributes). This revision adds the interfaces to the memcopy, memmove, and memset intrinsics. At the moment, the translation from MLIR to LLVM IR still uses the string based attribute lookup. In a follow up revision I plan to switch to using the new interfaces. Intrinsics automatically implement the interfaces if the requiresAccessGroup and requiresAliasAnalysis flags are set. Additionally, LLVM_IntrOpBase now defines the list of attributes aliasAttrs that need to be added to the argument list. Intrinsic setting the flags thus can add them as follows:

dag args = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
                Arg<LLVM_AnyPointer,"",[MemRead]>:$src,
                AnySignlessInteger:$len, I1:$isVolatile);
// Append the alias attributes defined by LLVM_IntrOpBase.
let arguments = !con(args, aliasAttrs);

I also did an update to mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp. Modifying it is a bit dangerous though since it does not have any upstream uses as far as I can tell. @hgreving you seem to have downstream uses for this? Would it make sense to move the file in the downstream project? Or am I completely mistaken and this is used somewhere (e.g. to regenerate parts of LLVMIntrinsicOps.td at some point)?

[Dinistro]

I'm not familiar with this tblgen part, so I suggest to wait for answers of the downstream users. The rest is looking nice.

[gysit]

Consistently rename alias scopes to alias analysis in LLVMIRIntrinsicGen.cpp.

[Dinistro]

After looking a bit closer over the tblgen part, I conclude that this looks good to me.

mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td

 // ArmNeon op definitions
 //===----------------------------------------------------------------------===//
 
 // ArmNeon dialect op that corresponds (and is convertible to) an LLVM IR
 // intrinsic.
 class ArmNeon_IntrOp<string mnemonic, list<int> overloadedResults,
                      list<int> overloadedOperands, int numResults,
                      list<Trait> traits = [], bit requiresAccessGroup = 0,
-                     bit requiresAliasScope = 0>
+                     bit requiresAliasAnalysis = 0>
     : LLVM_IntrOpBase</*dialect=*/ArmNeon_Dialect,
                       /*opName=*/"intr." # mnemonic,
                       /*enumName=*/"aarch64_neon_" # !subst(".", "_", mnemonic),
                       /*overloadedResults=*/overloadedResults,
                       /*overloadedOperands=*/overloadedOperands,
                       /*traits=*/traits,
                       /*numResults=*/numResults,
                       /*requiresAccessGroup=*/requiresAccessGroup,
-                      /*requiresAliasScope=*/requiresAliasScope>;
+                      /*requiresAliasAnalysis=*/requiresAliasAnalysis>;
 
 // ArmNeon dialect op that corresponds to an LLVM IR intrinsic with one
 // overloaded result.
 class ArmNeon_OverloadedOneResultIntrOp<string mnemonic,
                                         list<Trait> traits = []>
   : ArmNeon_IntrOp<mnemonic, [0], [], 1, traits>;
 
 // ArmNeon dialect op that corresponds to an LLVM IR intrinsic with one

mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td

 #ifndef LLVM_INTRINSIC_OPS
 #define LLVM_INTRINSIC_OPS
 
 include "mlir/IR/OpBase.td"
 include "mlir/Dialect/LLVMIR/LLVMAttrDefs.td"
 include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
-include "mlir/Dialect/LLVMIR/LLVMAttrDefs.td"
 include "mlir/Interfaces/InferTypeOpInterface.td"
 
 // Operations that correspond to LLVM intrinsics. With MLIR operation set being
 // extendable, there is no reason to introduce a hard boundary between "core"
 // operations and intrinsics. However, we systematically prefix them with
 // "intr." to avoid potential name clashes.
 
 class LLVM_UnaryIntrOpBase<string func, Type element,

 def LLVM_MinNumOp : LLVM_BinarySameArgsIntrOpF<"minnum">;
 def LLVM_MaximumOp : LLVM_BinarySameArgsIntrOpF<"maximum">;
 def LLVM_MinimumOp : LLVM_BinarySameArgsIntrOpF<"minimum">;
 def LLVM_SMaxOp : LLVM_BinarySameArgsIntrOpI<"smax">;
 def LLVM_SMinOp : LLVM_BinarySameArgsIntrOpI<"smin">;
 def LLVM_UMaxOp : LLVM_BinarySameArgsIntrOpI<"umax">;
 def LLVM_UMinOp : LLVM_BinarySameArgsIntrOpI<"umin">;
 
-def LLVM_MemcpyOp : LLVM_ZeroResultIntrOp<"memcpy", [0, 1, 2]> {
-  let arguments = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
-                       Arg<LLVM_AnyPointer,"",[MemRead]>:$src,
-                       AnySignlessInteger:$len, I1:$isVolatile);
-}
-def LLVM_MemcpyInlineOp : LLVM_ZeroResultIntrOp<"memcpy.inline", [0, 1, 2]> {
-  let arguments = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
-                       Arg<LLVM_AnyPointer,"",[MemRead]>:$src,
-                       AnySignlessInteger:$len, I1:$isVolatile);
-}
-def LLVM_MemmoveOp : LLVM_ZeroResultIntrOp<"memmove", [0, 1, 2]> {
-  let arguments = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
-                       Arg<LLVM_AnyPointer,"",[MemRead]>:$src,
-                       AnySignlessInteger:$len, I1:$isVolatile);
-}
-
-def LLVM_MemsetOp : LLVM_ZeroResultIntrOp<"memset", [0, 2]> {
-  let arguments = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
-                       I8:$val, AnySignlessInteger:$len, I1:$isVolatile);
+class LLVM_MemcpyIntrOpBase<string name> :
+    LLVM_ZeroResultIntrOp<name, [0, 1, 2], [], /*requiresAccessGroup=*/1,
+                                               /*requiresAliasAnalysis=*/1> {
+  dag args = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
+  // Append the alias attributes defined by LLVM_IntrOpBase.
+  let arguments = !con(args, aliasAttrs);
+  let builders = [
+    OpBuilder<(ins "Value":$dst, "Value":$src, "Value":$len,
+                   "Value":$isVolatile), [{
+      build($_builder, $_state, dst, src, len, isVolatile,
+            /*access_groups=*/nullptr, /*alias_scopes=*/nullptr,
+            /*noalias_scopes=*/nullptr, /*tbaa=*/nullptr);
+    }]
+  >];
+}
+
+def LLVM_MemcpyOp : LLVM_MemcpyIntrOpBase<"memcpy">;
+def LLVM_MemcpyInlineOp : LLVM_MemcpyIntrOpBase<"memcpy.inline">;
+def LLVM_MemmoveOp : LLVM_MemcpyIntrOpBase<"memmove">;
+
+def LLVM_MemsetOp : LLVM_ZeroResultIntrOp<"memset", [0, 2], [],
+                      /*requiresAccessGroup=*/1, /*requiresAliasAnalysis=*/1> {
+  dag args = (ins Arg<LLVM_AnyPointer,"",[MemWrite]>:$dst,
+  // Append the alias attributes defined by LLVM_IntrOpBase.
+  let arguments = !con(args, aliasAttrs);
+  let builders = [
+    OpBuilder<(ins "Value":$dst, "Value":$val, "Value":$len,
+                    "Value":$isVolatile), [{
+      build($_builder, $_state, dst, val, len, isVolatile,
+            /*access_groups=*/nullptr, /*alias_scopes=*/nullptr,
+            /*noalias_scopes=*/nullptr, /*tbaa=*/nullptr);
+    }]
+  >];
 }
 
 //===----------------------------------------------------------------------===//
 // Lifetime Markers
 //===----------------------------------------------------------------------===//
 
 /// Base operation for lifetime markers. The LLVM intrinsics require the size
 /// operand to be an immediate. In MLIR it is encoded as an attribute.

mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td

 // differentiate between differently-typed versions of the intrinsic.
 // If the intrinsic has multiple results, this will eventually be packed into a
 // single struct result. In this case, the types of any overloaded results need
 // to be accessed via the LLVMStructType, instead of directly via the result.
 // "opName" contains the name of the operation to be associated with the
 // intrinsic and "enumName" contains the name of the intrinsic as appears in
 // `llvm::Intrinsic` enum; one usually wants these to be related. Additionally,
 // the base class also defines the "mlirBuilder" field to support the inverse
-// translation starting from an LLVM IR intrinsic.
+// translation starting from an LLVM IR intrinsic. The "requiresAccessGroup",
+// "requiresAliasAnalysis", and "requiresFastmath" flags specify which
+// interfaces the intrinsic implements. If the corresponding flags are set, the
+// "aliasAttrs" list contains the arguments required by the access group and
+// alias analysis interfaces. Derived intrinsics should append the "aliasAttrs"
+// to their argument list if they set one of the flags.
 class LLVM_IntrOpBase<Dialect dialect, string opName, string enumName,
                       list<int> overloadedResults, list<int> overloadedOperands,
                       list<Trait> traits, int numResults,
-                      bit requiresAccessGroup = 0, bit requiresAliasScope = 0,
+                      bit requiresAccessGroup = 0, bit requiresAliasAnalysis = 0,
                       bit requiresFastmath = 0>
     : LLVM_OpBase<dialect, opName, !listconcat(
+        !if(!gt(requiresAccessGroup, 0),
+            [DeclareOpInterfaceMethods<AccessGroupOpInterface>], []),
+        !if(!gt(requiresAliasAnalysis, 0),
+            [DeclareOpInterfaceMethods<AliasAnalysisOpInterface>], []),
         !if(!gt(requiresFastmath, 0),
-            [DeclareOpInterfaceMethods<FastmathFlagsInterface>],
-            []),
+            [DeclareOpInterfaceMethods<FastmathFlagsInterface>], []),
         traits)>,
+      LLVM_MemOpPatterns,
       Results<!if(!gt(numResults, 0), (outs LLVM_Type:$res), (outs))> {
+  dag aliasAttrs = !con(
+        !if(!gt(requiresAccessGroup, 0),
+            (ins OptionalAttr<SymbolRefArrayAttr>:$access_groups),
+            (ins )),
+        !if(!gt(requiresAccessGroup, 0),
+            (ins OptionalAttr<SymbolRefArrayAttr>:$alias_scopes,
+                 OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes,
+                 OptionalAttr<SymbolRefArrayAttr>:$tbaa),
+            (ins )));
   string resultPattern = !if(!gt(numResults, 1),
                              LLVM_IntrPatterns.structResult,
                              LLVM_IntrPatterns.result);
   string llvmEnumName = enumName;
   let llvmBuilder = [{
     llvm::Module *module = builder.GetInsertBlock()->getModule();
     llvm::Function *fn = llvm::Intrinsic::getDeclaration(
         module,
         llvm::Intrinsic::}] # enumName # [{,
         { }] # !interleave(!listconcat(
             ListIntSubst<resultPattern, overloadedResults>.lst,
             ListIntSubst<LLVM_IntrPatterns.operand,
                          overloadedOperands>.lst), ", ") # [{
         });
     auto operands = moduleTranslation.lookupValues(opInst.getOperands());
-    }] # [{auto *inst = builder.CreateCall(fn, operands);
-    }] # !if(!gt(requiresAccessGroup, 0),
-      "moduleTranslation.setAccessGroupsMetadata(op, inst);",
-      "(void) inst;")
-    # !if(!gt(requiresAliasScope, 0),
-      "moduleTranslation.setAliasScopeMetadata(op, inst);",
-      "(void) inst;")
+    }] # [{
+    auto *inst = builder.CreateCall(fn, operands);
+    (void) inst;
+    }] # !if(!gt(requiresAccessGroup, 0), setAccessGroupsMetadataCode, "")
+       # !if(!gt(requiresAliasAnalysis, 0), setAliasAnalysisMetadataCode, "")
        # !if(!gt(numResults, 0), "$res = inst;", "");
 
   string mlirBuilder = [{
     FailureOr<SmallVector<Value>> mlirOperands =
       moduleImport.convertValues(llvmOperands);
     if (failed(mlirOperands))
       return failure();
     SmallVector<Type> resultTypes =
     }] # !if(!gt(numResults, 0), "{$_resultType};", "{};") # [{
     auto op = $_builder.create<$_qualCppClassName>(
       $_location, resultTypes, *mlirOperands);
     }] # !if(!gt(requiresFastmath, 0),
       "moduleImport.setFastmathFlagsAttr(inst, op);", "")
     # !if(!gt(numResults, 0), "$res = op;", "$_op = op;");
 }
 
 // Base class for LLVM intrinsic operations, should not be used directly. Places
 // the intrinsic into the LLVM dialect and prefixes its name with "intr.".
 class LLVM_IntrOp<string mnem, list<int> overloadedResults,
                   list<int> overloadedOperands, list<Trait> traits,
                   int numResults, bit requiresAccessGroup = 0,
-                  bit requiresAliasScope = 0, bit requiresFastmath = 0>
+                  bit requiresAliasAnalysis = 0, bit requiresFastmath = 0>
     : LLVM_IntrOpBase<LLVM_Dialect, "intr." # mnem, !subst(".", "_", mnem),
                       overloadedResults, overloadedOperands, traits,
-                      numResults, requiresAccessGroup, requiresAliasScope,
+                      numResults, requiresAccessGroup, requiresAliasAnalysis,
                       requiresFastmath>;
 
 // Base class for LLVM intrinsic operations returning no results. Places the
 // intrinsic into the LLVM dialect and prefixes its name with "intr.".
 //
 // Sample use: derive an entry from this class and populate the fields.
 //
 //    def LLVM_Name : LLVM_ZeroResultIntrOp<"name", [0], [Pure]>,
 //                    Arguments<(ins LLVM_Type, LLVM_Type)>;
 //
 // The mnemonic will be prefixed with "llvm.intr.", where the "llvm." part comes
 // from the LLVM dialect. The overloadedOperands list contains the indices of
 // the operands the type of which will be passed in the LLVM IR intrinsic
 // builder. In the example above, the Op has two arguments, but only the first
 // one (as indicated by `[0]`) is necessary to resolve the overloaded intrinsic.
 // The Op has no results.
 class LLVM_ZeroResultIntrOp<string mnem, list<int> overloadedOperands = [],
-                            list<Trait> traits = []>
-    : LLVM_IntrOp<mnem, [], overloadedOperands, traits, 0>;
+                            list<Trait> traits = [],
+                            bit requiresAccessGroup = 0,
+                            bit requiresAliasAnalysis = 0>
+    : LLVM_IntrOp<mnem, [], overloadedOperands, traits, /*numResults=*/0,
+                  requiresAccessGroup, requiresAliasAnalysis>;
 
 // Base class for LLVM intrinsic operations returning one result. Places the
 // intrinsic into the LLVM dialect and prefixes its name with "intr.". This is
 // similar to LLVM_ZeroResultIntrOp but allows one to define Ops returning one
 // result, called "res". Additionally, the overloadedResults list should contain
 // "0" if the result must be used to resolve overloaded intrinsics, or remain
 // empty otherwise.
 class LLVM_OneResultIntrOp<string mnem, list<int> overloadedResults = [],
                            list<int> overloadedOperands = [],
                            list<Trait> traits = [],
                            bit requiresFastmath = 0>
     : LLVM_IntrOp<mnem, overloadedResults, overloadedOperands, traits, 1,
-                  /*requiresAccessGroup=*/0, /*requiresAliasScope=*/0,
+                  /*requiresAccessGroup=*/0, /*requiresAliasAnalysis=*/0,
                   requiresFastmath>;
 
 def LLVM_OneResultOpBuilder :
   OpBuilder<(ins "Type":$resultType, "ValueRange":$operands,
     CArg<"ArrayRef<NamedAttribute>", "{}">:$attributes),
   [{
     if (resultType) $_state.addTypes(resultType);
     $_state.addOperands(operands);

mlir/test/Target/LLVMIR/Import/metadata-alias-scopes.ll

define void @supported_ops(ptr %arg1, float %arg2, i32 %arg3, i32 %arg4) {
   ; CHECK: llvm.load {{.*}}alias_scopes =
   %1 = load i32, ptr %arg1, !alias.scope !3
   ; CHECK: llvm.store {{.*}}alias_scopes =
   store i32 %1, ptr %arg1, !alias.scope !3
   ; CHECK: llvm.atomicrmw {{.*}}alias_scopes =
   %2 = atomicrmw fmax ptr %arg1, float %arg2 acquire, !alias.scope !3
   ; CHECK: llvm.cmpxchg {{.*}}alias_scopes =
   %3 = cmpxchg ptr %arg1, i32 %arg3, i32 %arg4 monotonic seq_cst, !alias.scope !3
+  ; CHECK: "llvm.intr.memcpy"{{.*}}alias_scopes =
+  call void @llvm.memcpy.p0.p0.i32(ptr %arg1, ptr %arg1, i32 4, i1 false), !alias.scope !3
+  ; CHECK: "llvm.intr.memset"{{.*}}alias_scopes =
+  call void @llvm.memset.p0.i32(ptr %arg1, i8 42, i32 4, i1 false), !alias.scope !3
   ret void
 }
 
+declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg)
+declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
+
 !0 = distinct !{!0, !"The domain"}
 !1 = distinct !{!1}
 !2 = !{!2, !0}
 !3 = !{!2}

mlir/test/Target/LLVMIR/Import/metadata-loop.ll

define void @supported_ops(ptr %arg1, float %arg2, i32 %arg3, i32 %arg4) {
   ; CHECK: llvm.load {{.*}}access_groups =
   %1 = load i32, ptr %arg1, !llvm.access.group !0
   ; CHECK: llvm.store {{.*}}access_groups =
   store i32 %1, ptr %arg1, !llvm.access.group !0
   ; CHECK: llvm.atomicrmw {{.*}}access_groups =
   %2 = atomicrmw fmax ptr %arg1, float %arg2 acquire, !llvm.access.group !0
   ; CHECK: llvm.cmpxchg {{.*}}access_groups =
   %3 = cmpxchg ptr %arg1, i32 %arg3, i32 %arg4 monotonic seq_cst, !llvm.access.group !0
+  ; CHECK: "llvm.intr.memcpy"{{.*}}access_groups =
+  call void @llvm.memcpy.p0.p0.i32(ptr %arg1, ptr %arg1, i32 4, i1 false), !llvm.access.group !0
+  ; CHECK: "llvm.intr.memset"{{.*}}access_groups =
+  call void @llvm.memset.p0.i32(ptr %arg1, i8 42, i32 4, i1 false), !llvm.access.group !0
   ret void
 }
 
+declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg)
+declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
+
 !0 = !{!1, !2}
 !1 = distinct !{}
 !2 = distinct !{}
 
 ; // -----
 
 ; CHECK: #[[$ANNOT_ATTR:.*]] = #llvm.loop_annotation<disableNonforced = true, mustProgress = true, isVectorized = true>
 

mlir/test/Target/LLVMIR/Import/metadata-tbaa.ll

define void @supported_ops(ptr %arg1, float %arg2, i32 %arg3, i32 %arg4) {
   ; CHECK: llvm.load {{.*}}tbaa =
   %1 = load i32, ptr %arg1, !tbaa !0
   ; CHECK: llvm.store {{.*}}tbaa =
   store i32 %1, ptr %arg1, !tbaa !0
   ; CHECK: llvm.atomicrmw {{.*}}tbaa =
   %2 = atomicrmw fmax ptr %arg1, float %arg2 acquire, !tbaa !0
   ; CHECK: llvm.cmpxchg {{.*}}tbaa =
   %3 = cmpxchg ptr %arg1, i32 %arg3, i32 %arg4 monotonic seq_cst, !tbaa !0
+  ; CHECK: "llvm.intr.memcpy"{{.*}}tbaa =
+  call void @llvm.memcpy.p0.p0.i32(ptr %arg1, ptr %arg1, i32 4, i1 false), !tbaa !0
+  ; CHECK: "llvm.intr.memset"{{.*}}tbaa =
+  call void @llvm.memset.p0.i32(ptr %arg1, i8 42, i32 4, i1 false), !tbaa !0
   ret void
 }
 
+declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg)
+declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
+
 !0 = !{!1, !1, i64 0}
 !1 = !{!"scalar type", !2, i64 0}
 !2 = !{!"Simple C/C++ TBAA"}

mlir/test/Target/LLVMIR/llvmir.mlir

 
 module {
   llvm.func @aliasScope(%arg1 : !llvm.ptr) {
       %0 = llvm.mlir.constant(0 : i32) : i32
       llvm.store %0, %arg1 {alias_scopes = [@metadata::@scope1], noalias_scopes = [@metadata::@scope2, @metadata::@scope3]} : i32, !llvm.ptr
       %1 = llvm.load %arg1 {alias_scopes = [@metadata::@scope2], noalias_scopes = [@metadata::@scope1, @metadata::@scope3]} : !llvm.ptr -> i32
       %2 = llvm.atomicrmw add %arg1, %0 monotonic {alias_scopes = [@metadata::@scope3], noalias_scopes = [@metadata::@scope1, @metadata::@scope2]} : !llvm.ptr, i32
       %3 = llvm.cmpxchg %arg1, %1, %2 acq_rel monotonic {alias_scopes = [@metadata::@scope3]} : !llvm.ptr, i32
+      %4 = llvm.mlir.constant(0 : i1) : i1
+      %5 = llvm.mlir.constant(42 : i8) : i8
+      "llvm.intr.memcpy"(%arg1, %arg1, %0, %4) {alias_scopes = [@metadata::@scope3]} : (!llvm.ptr, !llvm.ptr, i32, i1) -> ()
+      "llvm.intr.memset"(%arg1, %5, %0, %4) {noalias_scopes = [@metadata::@scope3]} : (!llvm.ptr, i8, i32, i1) -> ()
       llvm.return
   }
 
   llvm.metadata @metadata {
     llvm.alias_scope_domain @domain {description = "The domain"}
     llvm.alias_scope @scope1 {domain = @domain, description = "The first scope"}
     llvm.alias_scope @scope2 {domain = @domain}
     llvm.alias_scope @scope3 {domain = @domain}
   }
 }
 
 // Function
 // CHECK-LABEL: aliasScope
 // CHECK:  store {{.*}}, !alias.scope ![[SCOPES1:[0-9]+]], !noalias ![[SCOPES23:[0-9]+]]
 // CHECK:  load {{.*}}, !alias.scope ![[SCOPES2:[0-9]+]], !noalias ![[SCOPES13:[0-9]+]]
 // CHECK:  atomicrmw {{.*}}, !alias.scope ![[SCOPES3:[0-9]+]], !noalias ![[SCOPES12:[0-9]+]]
 // CHECK:  cmpxchg {{.*}}, !alias.scope ![[SCOPES3]]
+// CHECK:  llvm.memcpy{{.*}}, !alias.scope ![[SCOPES3]]
+// CHECK:  llvm.memset{{.*}}, !noalias ![[SCOPES3]]
 
 // Metadata
 // CHECK-DAG: ![[DOMAIN:[0-9]+]] = distinct !{![[DOMAIN]], !"The domain"}
 // CHECK-DAG: ![[SCOPE1:[0-9]+]] = distinct !{![[SCOPE1]], ![[DOMAIN]], !"The first scope"}
 // CHECK-DAG: ![[SCOPE2:[0-9]+]] = distinct !{![[SCOPE2]], ![[DOMAIN]]}
 // CHECK-DAG: ![[SCOPE3:[0-9]+]] = distinct !{![[SCOPE3]], ![[DOMAIN]]}
 // CHECK-DAG: ![[SCOPES1]] = !{![[SCOPE1]]}
 // CHECK-DAG: ![[SCOPES2]] = !{![[SCOPE2]]}

mlir/test/Target/LLVMIR/loop-metadata.mlir

^bb4:
     // CHECK: = load i32, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE:[0-9]+]]
     %5 = llvm.load %4 {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr -> i32
     // CHECK: store i32 %{{.*}}, ptr %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
     llvm.store %5, %4 {access_groups = [@metadata::@group1, @metadata::@group2]} : i32, !llvm.ptr
     // CHECK: = atomicrmw add ptr %{{.*}}, i32 %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
     %6 = llvm.atomicrmw add %4, %5 monotonic {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr, i32
     // CHECK: = cmpxchg ptr %{{.*}}, i32 %{{.*}}, i32 %{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
     %7 = llvm.cmpxchg %4, %5, %6 acq_rel monotonic {access_groups = [@metadata::@group1, @metadata::@group2]} : !llvm.ptr, i32
+    %8 = llvm.mlir.constant(0 : i1) : i1
+    %9 = llvm.mlir.constant(42 : i8) : i8
+    // CHECK: llvm.memcpy{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
+    "llvm.intr.memcpy"(%4, %4, %0, %8) {access_groups = [@metadata::@group1, @metadata::@group2]} : (!llvm.ptr, !llvm.ptr, i32, i1) -> ()
+    // CHECK: llvm.memset{{.*}} !llvm.access.group ![[ACCESS_GROUPS_NODE]]
+    "llvm.intr.memset"(%4, %9, %0, %8) {access_groups = [@metadata::@group1, @metadata::@group2]} : (!llvm.ptr, i8, i32, i1) -> ()
     // CHECK: br label {{.*}} !llvm.loop ![[LOOP_NODE]]
     llvm.br ^bb3(%3 : i32) {loop_annotation = #llvm.loop_annotation<
           licm = <disable = true>,
           interleave = <count = 1>,
           unroll = <disable = true>, pipeline = <disable = true, initiationinterval = 2>,
           parallelAccesses = @metadata::@group1, @metadata::@group2>}
 
   ^bb5:

mlir/test/Target/LLVMIR/tbaa.mlir

llvm.func @tbaa2(%arg0: !llvm.ptr, %arg1: !llvm.ptr) {
     %4 = llvm.fptosi %3 : f32 to i32
     %5 = llvm.getelementptr inbounds %arg0[%0, 0] : (!llvm.ptr, i32) -> !llvm.ptr, !llvm.struct<"struct.agg1_t", (i32, i32)>
     // CHECK: store i32 %{{.*}}, ptr %{{.*}},{{.*}}!tbaa ![[STAG:[0-9]*]]
     llvm.store %4, %5 {tbaa = [@__tbaa::@tbaa_tag_7]} : i32, !llvm.ptr
     // CHECK: atomicrmw add ptr %{{.*}}, i32 %{{.*}} !tbaa ![[STAG]]
     %6 = llvm.atomicrmw add %5, %4 monotonic {tbaa = [@__tbaa::@tbaa_tag_7]} : !llvm.ptr, i32
     // CHECK: cmpxchg ptr %{{.*}}, i32 %{{.*}}, i32 %{{.*}} !tbaa ![[STAG]]
     %7 = llvm.cmpxchg %5, %6, %4 acq_rel monotonic {tbaa = [@__tbaa::@tbaa_tag_7]} : !llvm.ptr, i32
+    %8 = llvm.mlir.constant(0 : i1) : i1
+    %9 = llvm.mlir.constant(42 : i8) : i8
+    // CHECK: llvm.memcpy{{.*}} !tbaa ![[STAG]]
+    "llvm.intr.memcpy"(%arg1, %arg1, %0, %8) {tbaa = [@__tbaa::@tbaa_tag_7]} : (!llvm.ptr, !llvm.ptr, i32, i1) -> ()
+    // CHECK: llvm.memset{{.*}} !tbaa ![[STAG]]
+    "llvm.intr.memset"(%arg1, %9, %0, %8) {tbaa = [@__tbaa::@tbaa_tag_7]} : (!llvm.ptr, i8, i32, i1) -> ()
     llvm.return
   }
 }
 
 // CHECK-DAG: ![[LTAG]] = !{![[AGG2T:[0-9]*]], ![[F32T:[0-9]*]], i64 0}
 // CHECK-DAG: ![[AGG2T]] = !{!"agg2_t", ![[F32T]], i64 0, ![[F32T]], i64 4}
 // CHECK-DAG: ![[I64T]] = !{!"float", ![[CHART:[0-9]*]], i64 0}
 // CHECK-DAG: ![[CHART]] = !{!"omnipotent char", ![[ROOT:[0-9]*]], i64 0}
 // CHECK-DAG: ![[ROOT]] = !{!"Simple C/C++ TBAA"}
 // CHECK-DAG: ![[STAG]] = !{![[AGG1T:[0-9]*]], ![[I32T:[0-9]*]], i64 0}
 // CHECK-DAG: ![[AGG1T]] = !{!"agg1_t", ![[I32T]], i64 0, ![[I32T]], i64 4}
 // CHECK-DAG: ![[I32T]] = !{!"int", ![[CHART]], i64 0}

mlir/test/mlir-tblgen/llvm-intrinsics.td

 // CHECK: [0]
 // The second operand is overloadable, but the first operand needs to
 // match the result type.
 // CHECK: [1]
 // It has no side effects.
 // CHECK: [NoMemoryEffect]
 // It has a result.
 // CHECK: 1,
-// It does not require an access group.
+// It does not implement the access group interface.
 // CHECK: 0,
-// It does not require alias scopes.
+// It does not implement the alias analysis interface.
 // CHECK: 0>
 // CHECK: Arguments<(ins LLVM_Type, LLVM_Type
 
 //---------------------------------------------------------------------------//
 
 // This checks that we can define an op that takes in an access group metadata.
 //
 // RUN: cat %S/../../../llvm/include/llvm/IR/Intrinsics.td \
 // RUN: | grep -v "llvm/IR/Intrinsics" \
 // RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filter=ptrmask --llvmir-intrinsics-access-group-regexp=ptrmask \
 // RUN: | FileCheck --check-prefix=GROUPS %s
 
 // GROUPS-LABEL: def LLVM_ptrmask
 // GROUPS: LLVM_IntrOp<"ptrmask
 // It has no side effects.
 // GROUPS: [NoMemoryEffect]
 // It has a result.
 // GROUPS: 1,
-// It requires generation of an access group LLVM metadata.
+// It implements the access group interface.
 // GROUPS: 1,
-// It does not require alias scopes.
+// It does not implement the alias analysis interface.
 // GROUPS: 0>
 // It has an access group attribute.
 // GROUPS: OptionalAttr<SymbolRefArrayAttr>:$access_groups
 
 //---------------------------------------------------------------------------//
 
-// This checks that we can define an op that takes in alias scopes metadata.
+// This checks that we can define an op that takes in alias analysis metadata.
 //
 // RUN: cat %S/../../../llvm/include/llvm/IR/Intrinsics.td \
 // RUN: | grep -v "llvm/IR/Intrinsics" \
-// RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filter=ptrmask --llvmir-intrinsics-alias-scopes-regexp=ptrmask \
+// RUN: | mlir-tblgen -gen-llvmir-intrinsics -I %S/../../../llvm/include/ --llvmir-intrinsics-filter=ptrmask --llvmir-intrinsics-alias-analysis-regexp=ptrmask \
 // RUN: | FileCheck --check-prefix=ALIAS %s
 
 // ALIAS-LABEL: def LLVM_ptrmask
 // ALIAS: LLVM_IntrOp<"ptrmask
 // It has no side effects.
 // ALIAS: [NoMemoryEffect]
 // It has a result.
 // ALIAS: 1,
-// It does not require an access group.
+// It does not implement the access group interface.
 // ALIAS: 0,
-// It requires generation of alias scopes LLVM metadata.
+// It implements the alias analysis interface.
 // ALIAS: 1>
-// It has alias scopes and noalias.
+// It has alias scopes, noalias, and tbaa.
 // ALIAS: OptionalAttr<SymbolRefArrayAttr>:$alias_scopes
 // ALIAS: OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes
+// ALIAS: OptionalAttr<SymbolRefArrayAttr>:$tbaa
 
 //---------------------------------------------------------------------------//
 
 // This checks that the ODS we produce can be consumed by MLIR tablegen. We only
 // make sure the entire process does not fail and produces some C++. The shape
 // of this C++ code is tested by ODS tests.
 
 // RUN: cat %S/../../../llvm/include/llvm/IR/Intrinsics.td \

mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp

opBaseClass("dialect-opclass-base",
                 llvm::cl::init("LLVM_IntrOp"), llvm::cl::cat(intrinsicGenCat));
 
 static llvm::cl::opt<std::string> accessGroupRegexp(
     "llvmir-intrinsics-access-group-regexp",
     llvm::cl::desc("Mark intrinsics that match the specified "
                    "regexp as taking an access group metadata"),
     llvm::cl::cat(intrinsicGenCat));
 
-static llvm::cl::opt<std::string> aliasScopesRegexp(
-    "llvmir-intrinsics-alias-scopes-regexp",
+static llvm::cl::opt<std::string> aliasAnalysisRegexp(
+    "llvmir-intrinsics-alias-analysis-regexp",
     llvm::cl::desc("Mark intrinsics that match the specified "
-                   "regexp as taking alias.scopes and noalias metadata"),
+                   "regexp as taking alias.scopes, noalias, and tbaa metadata"),
     llvm::cl::cat(intrinsicGenCat));
 
 // Used to represent the indices of overloadable operands/results.
 using IndicesTy = llvm::SmallBitVector;
 
 /// Return a CodeGen value type entry from a type record.
 static llvm::MVT::SimpleValueType getValueType(const llvm::Record *rec) {
   return (llvm::MVT::SimpleValueType)rec->getValueAsDef("VT")->getValueAsInt(

 /// Returns true on error, false on success.
 static bool emitIntrinsic(const llvm::Record &record, llvm::raw_ostream &os) {
   LLVMIntrinsic intr(record);
 
   llvm::Regex accessGroupMatcher(accessGroupRegexp);
   bool requiresAccessGroup =
       !accessGroupRegexp.empty() && accessGroupMatcher.match(record.getName());
 
-  llvm::Regex aliasScopesMatcher(aliasScopesRegexp);
-  bool requiresAliasScopes =
-      !aliasScopesRegexp.empty() && aliasScopesMatcher.match(record.getName());
+  llvm::Regex aliasAnalysisMatcher(aliasAnalysisRegexp);
+  bool requiresAliasAnalysis = !aliasAnalysisRegexp.empty() &&
+                               aliasAnalysisMatcher.match(record.getName());
 
   // Prepare strings for traits, if any.
   llvm::SmallVector<llvm::StringRef, 2> traits;
   if (intr.isCommutative())
     traits.push_back("Commutative");
   if (!intr.hasSideEffects())
     traits.push_back("NoMemoryEffect");
 
   // Prepare strings for operands.
   llvm::SmallVector<llvm::StringRef, 8> operands(intr.getNumOperands(),
                                                  "LLVM_Type");
   if (requiresAccessGroup)
     operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$access_groups");
-  if (requiresAliasScopes) {
+  if (requiresAliasAnalysis) {
     operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$alias_scopes");
     operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$noalias_scopes");
+    operands.push_back("OptionalAttr<SymbolRefArrayAttr>:$tbaa");
   }
 
   // Emit the definition.
   os << "def LLVM_" << intr.getProperRecordName() << " : " << opBaseClass
      << "<\"" << intr.getOperationName() << "\", ";
   printBracketedRange(intr.getOverloadableResultsIdxs().set_bits(), os);
   os << ", ";
   printBracketedRange(intr.getOverloadableOperandsIdxs().set_bits(), os);
   os << ", ";
   printBracketedRange(traits, os);
   os << ", " << intr.getNumResults() << ", "
      << (requiresAccessGroup ? "1" : "0") << ", "
-     << (requiresAliasScopes ? "1" : "0") << ">, Arguments<(ins"
+     << (requiresAliasAnalysis ? "1" : "0") << ">, Arguments<(ins"
      << (operands.empty() ? "" : " ");
   llvm::interleaveComma(operands, os);
   os << ")>;\n\n";
 
   return false;
 }
 
 /// Traverses the list of TableGen definitions derived from the "Intrinsic"