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Differential D144536

[VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp.abs/ctlz/cttz.
ClosedPublic

Authored by fakepaper56 on Feb 21 2023, 11:35 PM.

Details

Reviewers
craig.topper
reames
frasercrmck
rogfer01
eopXD
Commits
rG419948fe6708: [VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp.
Summary

The patch ensures last two operands of vp.abs/ctlz/cttz are mask and evl.

Diff Detail

Event Timeline

fakepaper56 created this revision.Feb 21 2023, 11:35 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2023, 11:36 PM
Herald added subscribers: luke, luismarques, apazos and 18 others. · View Herald Transcript
fakepaper56 requested review of this revision.Feb 21 2023, 11:36 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2023, 11:36 PM
Herald added subscribers: llvm-commits, • pcwang-thead, jdoerfert, MaskRay. · View Herald Transcript
craig.topper accepted this revision.Feb 22 2023, 8:48 AM

LGTM

This revision is now accepted and ready to land.Feb 22 2023, 8:48 AM
This revision was landed with ongoing or failed builds.Feb 22 2023, 9:58 PM
Closed by commit rG419948fe6708: [VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp. (authored by fakepaper56). · Explain Why
This revision was automatically updated to reflect the committed changes.
fakepaper56 added a commit: rG419948fe6708: [VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp..

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
14 lines
14 lines
lib/
CodeGen/
SelectionDAG/
10 lines
test/
Analysis/
CostModel/
RISCV/
548 lines
CodeGen/
RISCV/
rvv/
144 lines
240 lines
240 lines
111 lines
180 lines
180 lines
unittests/
IR/
6 lines

Diff 499723

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 1,539 Lines • ▼ Show 20 Lines def int_vp_srem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
llvm_i32_ty]>; llvm_i32_ty]>;
def int_vp_urem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], def int_vp_urem : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>, [ LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty]>; llvm_i32_ty]>;
def int_vp_abs : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], def int_vp_abs : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>, [ LLVMMatchType<0>,
llvm_i1_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty, llvm_i32_ty]>;
llvm_i1_ty]>;
def int_vp_smin : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], def int_vp_smin : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>, [ LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty]>; llvm_i32_ty]>;
def int_vp_smax : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], def int_vp_smax : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>, [ LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
▲ Show 20 Lines • Show All 262 Lines • ▼ Show 20 Lines def int_vp_reduce_fmax : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
llvm_i32_ty]>; llvm_i32_ty]>;
def int_vp_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], def int_vp_reduce_fmin : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
[ LLVMVectorElementType<0>, [ LLVMVectorElementType<0>,
llvm_anyvector_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty]>; llvm_i32_ty]>;
} }
let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn, ImmArg<ArgIndex<3>>] in { let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn, ImmArg<ArgIndex<1>>] in {
def int_vp_ctlz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], def int_vp_ctlz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>, [ LLVMMatchType<0>,
llvm_i1_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty, llvm_i32_ty]>;
llvm_i1_ty]>;
def int_vp_cttz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], def int_vp_cttz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>, [ LLVMMatchType<0>,
llvm_i1_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty, llvm_i32_ty]>;
llvm_i1_ty]>;
} }
def int_get_active_lane_mask: def int_get_active_lane_mask:
DefaultAttrsIntrinsic<[llvm_anyvector_ty], DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_anyint_ty, LLVMMatchType<1>], [llvm_anyint_ty, LLVMMatchType<1>],
[IntrNoMem, IntrNoSync, IntrWillReturn]>; [IntrNoMem, IntrNoSync, IntrWillReturn]>;
def int_experimental_vp_splice: def int_experimental_vp_splice:
▲ Show 20 Lines • Show All 362 Lines • Show Last 20 Lines

llvm/include/llvm/IR/VPIntrinsics.def

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
VP_PROPERTY_BINARYOP VP_PROPERTY_BINARYOP
END_REGISTER_VP(vp_umin, VP_UMIN) END_REGISTER_VP(vp_umin, VP_UMIN)
// llvm.vp.umax(x,y,mask,vlen) // llvm.vp.umax(x,y,mask,vlen)
BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1) BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1)
VP_PROPERTY_BINARYOP VP_PROPERTY_BINARYOP
END_REGISTER_VP(vp_umax, VP_UMAX) END_REGISTER_VP(vp_umax, VP_UMAX)
// llvm.vp.abs(x,mask,vlen,is_int_min_poison) // llvm.vp.abs(x,is_int_min_poison,mask,vlen)
BEGIN_REGISTER_VP(vp_abs, 1, 2, VP_ABS, -1) BEGIN_REGISTER_VP_INTRINSIC(vp_abs, 2, 3)
BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2)
HELPER_MAP_VPID_TO_VPSD(vp_abs, VP_ABS)
END_REGISTER_VP(vp_abs, VP_ABS) END_REGISTER_VP(vp_abs, VP_ABS)
// llvm.vp.bswap(x,mask,vlen) // llvm.vp.bswap(x,mask,vlen)
BEGIN_REGISTER_VP(vp_bswap, 1, 2, VP_BSWAP, -1) BEGIN_REGISTER_VP(vp_bswap, 1, 2, VP_BSWAP, -1)
END_REGISTER_VP(vp_bswap, VP_BSWAP) END_REGISTER_VP(vp_bswap, VP_BSWAP)
// llvm.vp.bitreverse(x,mask,vlen) // llvm.vp.bitreverse(x,mask,vlen)
BEGIN_REGISTER_VP(vp_bitreverse, 1, 2, VP_BITREVERSE, -1) BEGIN_REGISTER_VP(vp_bitreverse, 1, 2, VP_BITREVERSE, -1)
END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE) END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE)
// llvm.vp.ctpop(x,mask,vlen) // llvm.vp.ctpop(x,mask,vlen)
BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1) BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1)
END_REGISTER_VP(vp_ctpop, VP_CTPOP) END_REGISTER_VP(vp_ctpop, VP_CTPOP)
// llvm.vp.ctlz(x,mask,vlen, is_zero_poison) // llvm.vp.ctlz(x,is_zero_poison,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 1, 2) BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 2, 3)
BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2) BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTLZ) END_REGISTER_VP_SDNODE(VP_CTLZ)
BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2) BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF) END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF)
END_REGISTER_VP_INTRINSIC(vp_ctlz) END_REGISTER_VP_INTRINSIC(vp_ctlz)
// llvm.vp.cttz(x,mask,vlen, is_zero_poison) // llvm.vp.cttz(x,is_zero_poison,mask,vlen)
BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 1, 2) BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 2, 3)
BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2) BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTTZ) END_REGISTER_VP_SDNODE(VP_CTTZ)
BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2) BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2)
END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF) END_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF)
END_REGISTER_VP_INTRINSIC(vp_cttz) END_REGISTER_VP_INTRINSIC(vp_cttz)
// llvm.vp.fshl(x,y,z,mask,vlen) // llvm.vp.fshl(x,y,z,mask,vlen)
BEGIN_REGISTER_VP(vp_fshl, 3, 4, VP_FSHL, -1) BEGIN_REGISTER_VP(vp_fshl, 3, 4, VP_FSHL, -1)
▲ Show 20 Lines • Show All 385 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,440 Lines • ▼ Show 20 Lines#include "llvm/IR/ConstrainedOps.def"
SDValue FPResult = Result.getValue(0); SDValue FPResult = Result.getValue(0);
setValue(&FPI, FPResult); setValue(&FPI, FPResult);
} }
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) { static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) {
std::optional<unsigned> ResOPC; std::optional<unsigned> ResOPC;
switch (VPIntrin.getIntrinsicID()) { switch (VPIntrin.getIntrinsicID()) {
case Intrinsic::vp_ctlz: { case Intrinsic::vp_ctlz: {
bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(3))->isOne(); bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ; ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
break; break;
} }
case Intrinsic::vp_cttz: { case Intrinsic::vp_cttz: {
bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(3))->isOne(); bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(1))->isOne();
ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ; ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
break; break;
} }
#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \ #define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
case Intrinsic::VPID: \ case Intrinsic::VPID: \
ResOPC = ISD::VPSD; \ ResOPC = ISD::VPSD; \
break; break;
#include "llvm/IR/VPIntrinsics.def" #include "llvm/IR/VPIntrinsics.def"
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines case ISD::VP_PTRTOINT: {
setValue(&VPIntrin, N); setValue(&VPIntrin, N);
break; break;
} }
case ISD::VP_ABS: case ISD::VP_ABS:
case ISD::VP_CTLZ: case ISD::VP_CTLZ:
case ISD::VP_CTLZ_ZERO_UNDEF: case ISD::VP_CTLZ_ZERO_UNDEF:
case ISD::VP_CTTZ: case ISD::VP_CTTZ:
case ISD::VP_CTTZ_ZERO_UNDEF: { case ISD::VP_CTTZ_ZERO_UNDEF: {
// Pop is_zero_poison operand for cp.ctlz/cttz or SDValue Result =
// is_int_min_poison operand for vp.abs. DAG.getNode(Opcode, DL, VTs, {OpValues[0], OpValues[2], OpValues[3]});
OpValues.pop_back();
SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues);
setValue(&VPIntrin, Result); setValue(&VPIntrin, Result);
break; break;
} }
} }
} }
SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain, SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain,
const BasicBlock *EHPadBB, const BasicBlock *EHPadBB,
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llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lines;
call <vscale x 4 x i64> @llvm.vp.ctpop.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> undef, i32 undef) call <vscale x 4 x i64> @llvm.vp.ctpop.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i64> @llvm.vp.ctpop.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> undef, i32 undef) call <vscale x 8 x i64> @llvm.vp.ctpop.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i64> @llvm.vp.ctpop.nvx16i64(<vscale x 16 x i64> undef, <vscale x 16 x i1> undef, i32 undef) call <vscale x 16 x i64> @llvm.vp.ctpop.nvx16i64(<vscale x 16 x i64> undef, <vscale x 16 x i1> undef, i32 undef)
ret void ret void
} }
define void @vp_ctlz() { define void @vp_ctlz() {
; CHECK-LABEL: 'vp_ctlz' ; CHECK-LABEL: 'vp_ctlz'
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %1 = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %1 = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %2 = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %2 = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %3 = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %3 = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %4 = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %4 = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %5 = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %5 = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %6 = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %6 = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %7 = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %7 = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %8 = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %8 = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %9 = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %9 = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %10 = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %10 = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %11 = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> undef, <vscale x 64 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %11 = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> undef, i1 false, <vscale x 64 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %12 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %12 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %13 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %13 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %14 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %14 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %15 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %15 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %16 = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %16 = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %17 = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %17 = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %18 = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %18 = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %19 = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %19 = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %20 = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %20 = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %21 = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %21 = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %22 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %22 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %23 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %23 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %24 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %24 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %25 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %25 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %26 = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %26 = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %27 = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %27 = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %28 = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %28 = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %29 = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %29 = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %30 = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %30 = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %31 = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %31 = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %32 = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %32 = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %33 = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %33 = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %34 = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %34 = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %35 = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %35 = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %36 = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %36 = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %37 = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %37 = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %38 = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %38 = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %39 = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %39 = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %40 = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %40 = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %41 = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %41 = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %42 = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %42 = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %43 = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %43 = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %44 = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %44 = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %45 = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %45 = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %46 = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %46 = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %47 = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %47 = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %48 = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %48 = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %49 = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %49 = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
; ;
call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i8> @llvm.vp.ctlz.nvx1i8(<vscale x 1 x i8> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i8> @llvm.vp.ctlz.nvx1i8(<vscale x 1 x i8> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i8> @llvm.vp.ctlz.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i8> @llvm.vp.ctlz.nvx2i8(<vscale x 2 x i8> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i8> @llvm.vp.ctlz.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i8> @llvm.vp.ctlz.nvx4i8(<vscale x 4 x i8> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i8> @llvm.vp.ctlz.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i8> @llvm.vp.ctlz.nvx8i8(<vscale x 8 x i8> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i8> @llvm.vp.ctlz.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i8> @llvm.vp.ctlz.nvx16i8(<vscale x 16 x i8> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <vscale x 32 x i8> @llvm.vp.ctlz.nvx32i8(<vscale x 32 x i8> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) call <vscale x 32 x i8> @llvm.vp.ctlz.nvx32i8(<vscale x 32 x i8> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
call <vscale x 64 x i8> @llvm.vp.ctlz.nvx64i8(<vscale x 64 x i8> undef, <vscale x 64 x i1> undef, i32 undef, i1 false) call <vscale x 64 x i8> @llvm.vp.ctlz.nvx64i8(<vscale x 64 x i8> undef, i1 false, <vscale x 64 x i1> undef, i32 undef)
call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i16> @llvm.vp.ctlz.nvx1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i16> @llvm.vp.ctlz.nvx1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i16> @llvm.vp.ctlz.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i16> @llvm.vp.ctlz.nvx2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i16> @llvm.vp.ctlz.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i16> @llvm.vp.ctlz.nvx4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i16> @llvm.vp.ctlz.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i16> @llvm.vp.ctlz.nvx8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i16> @llvm.vp.ctlz.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i16> @llvm.vp.ctlz.nvx16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <vscale x 32 x i16> @llvm.vp.ctlz.nvx32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) call <vscale x 32 x i16> @llvm.vp.ctlz.nvx32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i16> @llvm.vp.ctlz.nvx1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i16> @llvm.vp.ctlz.nvx1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i16> @llvm.vp.ctlz.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i16> @llvm.vp.ctlz.nvx2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i16> @llvm.vp.ctlz.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i16> @llvm.vp.ctlz.nvx4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i16> @llvm.vp.ctlz.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i16> @llvm.vp.ctlz.nvx8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i16> @llvm.vp.ctlz.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i16> @llvm.vp.ctlz.nvx16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <vscale x 32 x i16> @llvm.vp.ctlz.nvx32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) call <vscale x 32 x i16> @llvm.vp.ctlz.nvx32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i32> @llvm.vp.ctlz.nvx1i32(<vscale x 1 x i32> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i32> @llvm.vp.ctlz.nvx1i32(<vscale x 1 x i32> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i32> @llvm.vp.ctlz.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i32> @llvm.vp.ctlz.nvx2i32(<vscale x 2 x i32> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i32> @llvm.vp.ctlz.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i32> @llvm.vp.ctlz.nvx4i32(<vscale x 4 x i32> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i32> @llvm.vp.ctlz.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i32> @llvm.vp.ctlz.nvx8i32(<vscale x 8 x i32> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i32> @llvm.vp.ctlz.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i32> @llvm.vp.ctlz.nvx16i32(<vscale x 16 x i32> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i64> @llvm.vp.ctlz.nvx1i64(<vscale x 1 x i64> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i64> @llvm.vp.ctlz.nvx1i64(<vscale x 1 x i64> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i64> @llvm.vp.ctlz.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i64> @llvm.vp.ctlz.nvx2i64(<vscale x 2 x i64> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i64> @llvm.vp.ctlz.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i64> @llvm.vp.ctlz.nvx4i64(<vscale x 4 x i64> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i64> @llvm.vp.ctlz.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i64> @llvm.vp.ctlz.nvx8i64(<vscale x 8 x i64> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i64> @llvm.vp.ctlz.nvx16i64(<vscale x 16 x i64> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i64> @llvm.vp.ctlz.nvx16i64(<vscale x 16 x i64> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
ret void ret void
} }
define void @vp_cttz() { define void @vp_cttz() {
; CHECK-LABEL: 'vp_cttz' ; CHECK-LABEL: 'vp_cttz'
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %1 = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %1 = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %2 = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %2 = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %3 = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %3 = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %7 = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %7 = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %8 = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %8 = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %9 = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %9 = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %10 = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %10 = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %11 = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> undef, <vscale x 64 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %11 = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> undef, i1 false, <vscale x 64 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %12 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %12 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %13 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %13 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %14 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %14 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %15 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %15 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %16 = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %16 = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %17 = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %17 = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %18 = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %18 = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %19 = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %19 = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %20 = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %20 = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %21 = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %21 = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %22 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %22 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %23 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %23 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %24 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %24 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %25 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %25 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %26 = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %26 = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %27 = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %27 = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %28 = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %28 = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %29 = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %29 = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %30 = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %30 = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %31 = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %31 = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %32 = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %32 = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %33 = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %33 = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %34 = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %34 = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %35 = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %35 = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %36 = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %36 = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %37 = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %37 = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %38 = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %38 = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %39 = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %39 = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %40 = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %40 = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %41 = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %41 = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %42 = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %42 = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %43 = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %43 = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %44 = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %44 = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %45 = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %45 = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %46 = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %46 = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %47 = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %47 = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %48 = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %48 = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %49 = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %49 = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
; ;
call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i8> @llvm.vp.cttz.nvx1i8(<vscale x 1 x i8> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i8> @llvm.vp.cttz.nvx1i8(<vscale x 1 x i8> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i8> @llvm.vp.cttz.nvx2i8(<vscale x 2 x i8> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i8> @llvm.vp.cttz.nvx2i8(<vscale x 2 x i8> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i8> @llvm.vp.cttz.nvx4i8(<vscale x 4 x i8> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i8> @llvm.vp.cttz.nvx4i8(<vscale x 4 x i8> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i8> @llvm.vp.cttz.nvx8i8(<vscale x 8 x i8> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i8> @llvm.vp.cttz.nvx8i8(<vscale x 8 x i8> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i8> @llvm.vp.cttz.nvx16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i8> @llvm.vp.cttz.nvx16i8(<vscale x 16 x i8> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <vscale x 32 x i8> @llvm.vp.cttz.nvx32i8(<vscale x 32 x i8> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) call <vscale x 32 x i8> @llvm.vp.cttz.nvx32i8(<vscale x 32 x i8> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
call <vscale x 64 x i8> @llvm.vp.cttz.nvx64i8(<vscale x 64 x i8> undef, <vscale x 64 x i1> undef, i32 undef, i1 false) call <vscale x 64 x i8> @llvm.vp.cttz.nvx64i8(<vscale x 64 x i8> undef, i1 false, <vscale x 64 x i1> undef, i32 undef)
call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i16> @llvm.vp.cttz.nvx1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i16> @llvm.vp.cttz.nvx1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i16> @llvm.vp.cttz.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i16> @llvm.vp.cttz.nvx2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i16> @llvm.vp.cttz.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i16> @llvm.vp.cttz.nvx4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i16> @llvm.vp.cttz.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i16> @llvm.vp.cttz.nvx8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i16> @llvm.vp.cttz.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i16> @llvm.vp.cttz.nvx16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <vscale x 32 x i16> @llvm.vp.cttz.nvx32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) call <vscale x 32 x i16> @llvm.vp.cttz.nvx32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i16> @llvm.vp.cttz.nvx1i16(<vscale x 1 x i16> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i16> @llvm.vp.cttz.nvx1i16(<vscale x 1 x i16> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i16> @llvm.vp.cttz.nvx2i16(<vscale x 2 x i16> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i16> @llvm.vp.cttz.nvx2i16(<vscale x 2 x i16> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i16> @llvm.vp.cttz.nvx4i16(<vscale x 4 x i16> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i16> @llvm.vp.cttz.nvx4i16(<vscale x 4 x i16> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i16> @llvm.vp.cttz.nvx8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i16> @llvm.vp.cttz.nvx8i16(<vscale x 8 x i16> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i16> @llvm.vp.cttz.nvx16i16(<vscale x 16 x i16> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i16> @llvm.vp.cttz.nvx16i16(<vscale x 16 x i16> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <vscale x 32 x i16> @llvm.vp.cttz.nvx32i16(<vscale x 32 x i16> undef, <vscale x 32 x i1> undef, i32 undef, i1 false) call <vscale x 32 x i16> @llvm.vp.cttz.nvx32i16(<vscale x 32 x i16> undef, i1 false, <vscale x 32 x i1> undef, i32 undef)
call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i32> @llvm.vp.cttz.nvx1i32(<vscale x 1 x i32> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i32> @llvm.vp.cttz.nvx1i32(<vscale x 1 x i32> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i32> @llvm.vp.cttz.nvx2i32(<vscale x 2 x i32> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i32> @llvm.vp.cttz.nvx2i32(<vscale x 2 x i32> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i32> @llvm.vp.cttz.nvx4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i32> @llvm.vp.cttz.nvx4i32(<vscale x 4 x i32> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i32> @llvm.vp.cttz.nvx8i32(<vscale x 8 x i32> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i32> @llvm.vp.cttz.nvx8i32(<vscale x 8 x i32> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i32> @llvm.vp.cttz.nvx16i32(<vscale x 16 x i32> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i32> @llvm.vp.cttz.nvx16i32(<vscale x 16 x i32> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef)
call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef)
call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef)
call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef)
call <vscale x 1 x i64> @llvm.vp.cttz.nvx1i64(<vscale x 1 x i64> undef, <vscale x 1 x i1> undef, i32 undef, i1 false) call <vscale x 1 x i64> @llvm.vp.cttz.nvx1i64(<vscale x 1 x i64> undef, i1 false, <vscale x 1 x i1> undef, i32 undef)
call <vscale x 2 x i64> @llvm.vp.cttz.nvx2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> undef, i32 undef, i1 false) call <vscale x 2 x i64> @llvm.vp.cttz.nvx2i64(<vscale x 2 x i64> undef, i1 false, <vscale x 2 x i1> undef, i32 undef)
call <vscale x 4 x i64> @llvm.vp.cttz.nvx4i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> undef, i32 undef, i1 false) call <vscale x 4 x i64> @llvm.vp.cttz.nvx4i64(<vscale x 4 x i64> undef, i1 false, <vscale x 4 x i1> undef, i32 undef)
call <vscale x 8 x i64> @llvm.vp.cttz.nvx8i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> undef, i32 undef, i1 false) call <vscale x 8 x i64> @llvm.vp.cttz.nvx8i64(<vscale x 8 x i64> undef, i1 false, <vscale x 8 x i1> undef, i32 undef)
call <vscale x 16 x i64> @llvm.vp.cttz.nvx16i64(<vscale x 16 x i64> undef, <vscale x 16 x i1> undef, i32 undef, i1 false) call <vscale x 16 x i64> @llvm.vp.cttz.nvx16i64(<vscale x 16 x i64> undef, i1 false, <vscale x 16 x i1> undef, i32 undef)
ret void ret void
} }
declare i16 @llvm.bswap.i16(i16) declare i16 @llvm.bswap.i16(i16)
declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>) declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>)
declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>) declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>) declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>) declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
declare <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64>, <8 x i1>, i32) declare <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64>, <8 x i1>, i32)
declare <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64>, <16 x i1>, i32)
declare <vscale x 1 x i64> @llvm.vp.ctpop.nvx1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32) declare <vscale x 1 x i64> @llvm.vp.ctpop.nvx1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i64> @llvm.vp.ctpop.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32) declare <vscale x 2 x i64> @llvm.vp.ctpop.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i64> @llvm.vp.ctpop.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32) declare <vscale x 4 x i64> @llvm.vp.ctpop.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i64> @llvm.vp.ctpop.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32) declare <vscale x 8 x i64> @llvm.vp.ctpop.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i64> @llvm.vp.ctpop.nvx16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32) declare <vscale x 16 x i64> @llvm.vp.ctpop.nvx16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32)
declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)
declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32)
declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32)
declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i8> @llvm.vp.ctlz.nvx1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i8> @llvm.vp.ctlz.nvx1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i8> @llvm.vp.ctlz.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i8> @llvm.vp.ctlz.nvx2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i8> @llvm.vp.ctlz.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i8> @llvm.vp.ctlz.nvx4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i8> @llvm.vp.ctlz.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i8> @llvm.vp.ctlz.nvx8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i8> @llvm.vp.ctlz.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i8> @llvm.vp.ctlz.nvx16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
declare <vscale x 32 x i8> @llvm.vp.ctlz.nvx32i8(<vscale x 32 x i8>, <vscale x 32 x i1>, i32, i1 immarg) declare <vscale x 32 x i8> @llvm.vp.ctlz.nvx32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
declare <vscale x 64 x i8> @llvm.vp.ctlz.nvx64i8(<vscale x 64 x i8>, <vscale x 64 x i1>, i32, i1 immarg) declare <vscale x 64 x i8> @llvm.vp.ctlz.nvx64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32)
declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32)
declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32)
declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i16> @llvm.vp.ctlz.nvx1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i16> @llvm.vp.ctlz.nvx1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i16> @llvm.vp.ctlz.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i16> @llvm.vp.ctlz.nvx2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i16> @llvm.vp.ctlz.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i16> @llvm.vp.ctlz.nvx4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i16> @llvm.vp.ctlz.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i16> @llvm.vp.ctlz.nvx8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i16> @llvm.vp.ctlz.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i16> @llvm.vp.ctlz.nvx16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
declare <vscale x 32 x i16> @llvm.vp.ctlz.nvx32i16(<vscale x 32 x i16>, <vscale x 32 x i1>, i32, i1 immarg) declare <vscale x 32 x i16> @llvm.vp.ctlz.nvx32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32)
declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32)
declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32)
declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i32> @llvm.vp.ctlz.nvx1i32(<vscale x 1 x i32>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i32> @llvm.vp.ctlz.nvx1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i32> @llvm.vp.ctlz.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i32> @llvm.vp.ctlz.nvx2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i32> @llvm.vp.ctlz.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i32> @llvm.vp.ctlz.nvx4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i32> @llvm.vp.ctlz.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i32> @llvm.vp.ctlz.nvx8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i32> @llvm.vp.ctlz.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i32> @llvm.vp.ctlz.nvx16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32)
declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32)
declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32)
declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i64> @llvm.vp.ctlz.nvx1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i64> @llvm.vp.ctlz.nvx1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i64> @llvm.vp.ctlz.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i64> @llvm.vp.ctlz.nvx2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i64> @llvm.vp.ctlz.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i64> @llvm.vp.ctlz.nvx4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i64> @llvm.vp.ctlz.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i64> @llvm.vp.ctlz.nvx8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i64> @llvm.vp.ctlz.nvx16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i64> @llvm.vp.ctlz.nvx16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)
declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32)
declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32)
declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i8> @llvm.vp.cttz.nvx1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i8> @llvm.vp.cttz.nvx1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i8> @llvm.vp.cttz.nvx2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i8> @llvm.vp.cttz.nvx2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i8> @llvm.vp.cttz.nvx4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i8> @llvm.vp.cttz.nvx4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i8> @llvm.vp.cttz.nvx8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i8> @llvm.vp.cttz.nvx8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i8> @llvm.vp.cttz.nvx16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i8> @llvm.vp.cttz.nvx16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
declare <vscale x 32 x i8> @llvm.vp.cttz.nvx32i8(<vscale x 32 x i8>, <vscale x 32 x i1>, i32, i1 immarg) declare <vscale x 32 x i8> @llvm.vp.cttz.nvx32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
declare <vscale x 64 x i8> @llvm.vp.cttz.nvx64i8(<vscale x 64 x i8>, <vscale x 64 x i1>, i32, i1 immarg) declare <vscale x 64 x i8> @llvm.vp.cttz.nvx64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32)
declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32)
declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32)
declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i16> @llvm.vp.cttz.nvx1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i16> @llvm.vp.cttz.nvx1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i16> @llvm.vp.cttz.nvx2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i16> @llvm.vp.cttz.nvx2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i16> @llvm.vp.cttz.nvx4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i16> @llvm.vp.cttz.nvx4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i16> @llvm.vp.cttz.nvx8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i16> @llvm.vp.cttz.nvx8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i16> @llvm.vp.cttz.nvx16i16(<vscale x 16 x i16>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i16> @llvm.vp.cttz.nvx16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
declare <vscale x 32 x i16> @llvm.vp.cttz.nvx32i16(<vscale x 32 x i16>, <vscale x 32 x i1>, i32, i1 immarg) declare <vscale x 32 x i16> @llvm.vp.cttz.nvx32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32)
declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32)
declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32)
declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i32> @llvm.vp.cttz.nvx1i32(<vscale x 1 x i32>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i32> @llvm.vp.cttz.nvx1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i32> @llvm.vp.cttz.nvx2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i32> @llvm.vp.cttz.nvx2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i32> @llvm.vp.cttz.nvx4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i32> @llvm.vp.cttz.nvx4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i32> @llvm.vp.cttz.nvx8i32(<vscale x 8 x i32>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i32> @llvm.vp.cttz.nvx8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i32> @llvm.vp.cttz.nvx16i32(<vscale x 16 x i32>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i32> @llvm.vp.cttz.nvx16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32)
declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32)
declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32)
declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32)
declare <vscale x 1 x i64> @llvm.vp.cttz.nvx1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i64> @llvm.vp.cttz.nvx1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
declare <vscale x 2 x i64> @llvm.vp.cttz.nvx2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32, i1 immarg) declare <vscale x 2 x i64> @llvm.vp.cttz.nvx2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
declare <vscale x 4 x i64> @llvm.vp.cttz.nvx4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32, i1 immarg) declare <vscale x 4 x i64> @llvm.vp.cttz.nvx4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
declare <vscale x 8 x i64> @llvm.vp.cttz.nvx8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32, i1 immarg) declare <vscale x 8 x i64> @llvm.vp.cttz.nvx8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
declare <vscale x 16 x i64> @llvm.vp.cttz.nvx16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32, i1 immarg) declare <vscale x 16 x i64> @llvm.vp.cttz.nvx16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)

llvm/test/CodeGen/RISCV/rvv/abs-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
declare <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @vp_abs_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_abs_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i8: ; CHECK-LABEL: vp_abs_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 1 x i8> @vp_abs_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_abs_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i8_unmasked: ; CHECK-LABEL: vp_abs_nxv1i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
declare <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @vp_abs_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_abs_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i8: ; CHECK-LABEL: vp_abs_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 2 x i8> @vp_abs_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_abs_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i8_unmasked: ; CHECK-LABEL: vp_abs_nxv2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
declare <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @vp_abs_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_abs_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i8: ; CHECK-LABEL: vp_abs_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @vp_abs_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_abs_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i8_unmasked: ; CHECK-LABEL: vp_abs_nxv4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
declare <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @vp_abs_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_abs_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i8: ; CHECK-LABEL: vp_abs_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 8 x i8> @vp_abs_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_abs_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i8_unmasked: ; CHECK-LABEL: vp_abs_nxv8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
declare <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i8> @vp_abs_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_abs_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i8: ; CHECK-LABEL: vp_abs_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @vp_abs_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_abs_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i8_unmasked: ; CHECK-LABEL: vp_abs_nxv16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
declare <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i1>, i32, i1) declare <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
define <vscale x 32 x i8> @vp_abs_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_abs_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv32i8: ; CHECK-LABEL: vp_abs_nxv32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 32 x i8> @vp_abs_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_abs_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv32i8_unmasked: ; CHECK-LABEL: vp_abs_nxv32i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
declare <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i1>, i32, i1) declare <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
define <vscale x 64 x i8> @vp_abs_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_abs_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv64i8: ; CHECK-LABEL: vp_abs_nxv64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 64 x i8> @vp_abs_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_abs_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv64i8_unmasked: ; CHECK-LABEL: vp_abs_nxv64i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
%v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
declare <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @vp_abs_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_abs_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i16: ; CHECK-LABEL: vp_abs_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 1 x i16> @vp_abs_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_abs_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i16_unmasked: ; CHECK-LABEL: vp_abs_nxv1i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
declare <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @vp_abs_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_abs_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i16: ; CHECK-LABEL: vp_abs_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 2 x i16> @vp_abs_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_abs_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i16_unmasked: ; CHECK-LABEL: vp_abs_nxv2i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
declare <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @vp_abs_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_abs_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i16: ; CHECK-LABEL: vp_abs_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 4 x i16> @vp_abs_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_abs_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i16_unmasked: ; CHECK-LABEL: vp_abs_nxv4i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
declare <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i16> @vp_abs_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_abs_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i16: ; CHECK-LABEL: vp_abs_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @vp_abs_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_abs_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i16_unmasked: ; CHECK-LABEL: vp_abs_nxv8i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
declare <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i16> @vp_abs_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_abs_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i16: ; CHECK-LABEL: vp_abs_nxv16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 16 x i16> @vp_abs_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_abs_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i16_unmasked: ; CHECK-LABEL: vp_abs_nxv16i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
declare <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i1>, i32, i1) declare <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
define <vscale x 32 x i16> @vp_abs_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_abs_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv32i16: ; CHECK-LABEL: vp_abs_nxv32i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 32 x i16> @vp_abs_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_abs_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv32i16_unmasked: ; CHECK-LABEL: vp_abs_nxv32i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
declare <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @vp_abs_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_abs_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i32: ; CHECK-LABEL: vp_abs_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 1 x i32> @vp_abs_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_abs_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i32_unmasked: ; CHECK-LABEL: vp_abs_nxv1i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
declare <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @vp_abs_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_abs_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i32: ; CHECK-LABEL: vp_abs_nxv2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 2 x i32> @vp_abs_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_abs_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i32_unmasked: ; CHECK-LABEL: vp_abs_nxv2i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
declare <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i32> @vp_abs_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_abs_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i32: ; CHECK-LABEL: vp_abs_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 4 x i32> @vp_abs_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_abs_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i32_unmasked: ; CHECK-LABEL: vp_abs_nxv4i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
declare <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i32> @vp_abs_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_abs_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i32: ; CHECK-LABEL: vp_abs_nxv8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @vp_abs_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_abs_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i32_unmasked: ; CHECK-LABEL: vp_abs_nxv8i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
declare <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i32> @vp_abs_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_abs_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i32: ; CHECK-LABEL: vp_abs_nxv16i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @vp_abs_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_abs_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i32_unmasked: ; CHECK-LABEL: vp_abs_nxv16i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
declare <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i64> @vp_abs_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_abs_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i64: ; CHECK-LABEL: vp_abs_nxv1i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vp_abs_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_abs_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv1i64_unmasked: ; CHECK-LABEL: vp_abs_nxv1i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
declare <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i64> @vp_abs_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_abs_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i64: ; CHECK-LABEL: vp_abs_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vp_abs_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_abs_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv2i64_unmasked: ; CHECK-LABEL: vp_abs_nxv2i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vrsub.vi v10, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
declare <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i64> @vp_abs_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_abs_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i64: ; CHECK-LABEL: vp_abs_nxv4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vp_abs_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_abs_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv4i64_unmasked: ; CHECK-LABEL: vp_abs_nxv4i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vrsub.vi v12, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
declare <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64>, <vscale x 7 x i1>, i32, i1) declare <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64>, i1 immarg, <vscale x 7 x i1>, i32)
define <vscale x 7 x i64> @vp_abs_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_abs_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv7i64: ; CHECK-LABEL: vp_abs_nxv7i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 7 x i64> @vp_abs_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_abs_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv7i64_unmasked: ; CHECK-LABEL: vp_abs_nxv7i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
%v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
declare <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i64> @vp_abs_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_abs_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i64: ; CHECK-LABEL: vp_abs_nxv8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vp_abs_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_abs_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv8i64_unmasked: ; CHECK-LABEL: vp_abs_nxv8i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vrsub.vi v16, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
declare <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i64: ; CHECK-LABEL: vp_abs_nxv16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
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; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 16 x i64> @vp_abs_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_abs_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i64_unmasked: ; CHECK-LABEL: vp_abs_nxv16i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2 ; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0 ; CHECK-NEXT: vrsub.vi v24, v16, 0
; CHECK-NEXT: vmax.vv v16, v16, v24 ; CHECK-NEXT: vmax.vv v16, v16, v24
; CHECK-NEXT: bltu a0, a1, .LBB47_2 ; CHECK-NEXT: bltu a0, a1, .LBB47_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB47_2: ; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0 ; CHECK-NEXT: vrsub.vi v24, v8, 0
; CHECK-NEXT: vmax.vv v8, v8, v24 ; CHECK-NEXT: vmax.vv v8, v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @vp_ctlz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_ctlz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv1i8: ; CHECK-LABEL: vp_ctlz_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 1 x i8> @vp_ctlz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_ctlz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv1i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv1i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
declare <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @vp_ctlz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_ctlz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv2i8: ; CHECK-LABEL: vp_ctlz_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 2 x i8> @vp_ctlz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_ctlz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv2i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
declare <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @vp_ctlz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_ctlz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv4i8: ; CHECK-LABEL: vp_ctlz_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @vp_ctlz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_ctlz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv4i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
declare <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @vp_ctlz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_ctlz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv8i8: ; CHECK-LABEL: vp_ctlz_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 8 x i8> @vp_ctlz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_ctlz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv8i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
declare <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i8> @vp_ctlz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_ctlz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv16i8: ; CHECK-LABEL: vp_ctlz_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t ; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v10, v8, a0, v0.t ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @vp_ctlz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_ctlz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv16i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
declare <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i1>, i32, i1) declare <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
define <vscale x 32 x i8> @vp_ctlz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_ctlz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv32i8: ; CHECK-LABEL: vp_ctlz_nxv32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v12, v8, a0, v0.t ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 32 x i8> @vp_ctlz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_ctlz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv32i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv32i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
declare <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i1>, i32, i1) declare <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
define <vscale x 64 x i8> @vp_ctlz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_ctlz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv64i8: ; CHECK-LABEL: vp_ctlz_nxv64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v16, v8, a0, v0.t ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 64 x i8> @vp_ctlz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_ctlz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv64i8_unmasked: ; CHECK-LABEL: vp_ctlz_nxv64i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 64 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
%v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
declare <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @vp_ctlz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_ctlz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv1i16: ; RV32-LABEL: vp_ctlz_nxv1i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 1 x i16> @vp_ctlz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_ctlz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv1i16_unmasked: ; RV32-LABEL: vp_ctlz_nxv1i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
declare <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @vp_ctlz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_ctlz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv2i16: ; RV32-LABEL: vp_ctlz_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 2 x i16> @vp_ctlz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_ctlz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv2i16_unmasked: ; RV32-LABEL: vp_ctlz_nxv2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
declare <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @vp_ctlz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_ctlz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv4i16: ; RV32-LABEL: vp_ctlz_nxv4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 4 x i16> @vp_ctlz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_ctlz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv4i16_unmasked: ; RV32-LABEL: vp_ctlz_nxv4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
declare <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i16> @vp_ctlz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_ctlz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv8i16: ; RV32-LABEL: vp_ctlz_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @vp_ctlz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_ctlz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv8i16_unmasked: ; RV32-LABEL: vp_ctlz_nxv8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
declare <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i16> @vp_ctlz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_ctlz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv16i16: ; RV32-LABEL: vp_ctlz_nxv16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 16 x i16> @vp_ctlz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_ctlz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv16i16_unmasked: ; RV32-LABEL: vp_ctlz_nxv16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
declare <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i1>, i32, i1) declare <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
define <vscale x 32 x i16> @vp_ctlz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_ctlz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv32i16: ; RV32-LABEL: vp_ctlz_nxv32i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 32 x i16> @vp_ctlz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_ctlz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv32i16_unmasked: ; RV32-LABEL: vp_ctlz_nxv32i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
declare <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @vp_ctlz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_ctlz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv1i32: ; RV32-LABEL: vp_ctlz_nxv1i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 1 x i32> @vp_ctlz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_ctlz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv1i32_unmasked: ; RV32-LABEL: vp_ctlz_nxv1i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
declare <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @vp_ctlz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_ctlz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv2i32: ; RV32-LABEL: vp_ctlz_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 2 x i32> @vp_ctlz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_ctlz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv2i32_unmasked: ; RV32-LABEL: vp_ctlz_nxv2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
declare <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i32> @vp_ctlz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_ctlz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv4i32: ; RV32-LABEL: vp_ctlz_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 4 x i32> @vp_ctlz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_ctlz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv4i32_unmasked: ; RV32-LABEL: vp_ctlz_nxv4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
declare <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i32> @vp_ctlz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_ctlz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv8i32: ; RV32-LABEL: vp_ctlz_nxv8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @vp_ctlz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_ctlz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv8i32_unmasked: ; RV32-LABEL: vp_ctlz_nxv8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
declare <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i32> @vp_ctlz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_ctlz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv16i32: ; RV32-LABEL: vp_ctlz_nxv16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @vp_ctlz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_ctlz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv16i32_unmasked: ; RV32-LABEL: vp_ctlz_nxv16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
declare <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i64> @vp_ctlz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_ctlz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv1i64: ; RV32-LABEL: vp_ctlz_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI36_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI36_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vp_ctlz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_ctlz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv1i64_unmasked: ; RV32-LABEL: vp_ctlz_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
declare <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i64> @vp_ctlz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_ctlz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv2i64: ; RV32-LABEL: vp_ctlz_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI38_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI38_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vp_ctlz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_ctlz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv2i64_unmasked: ; RV32-LABEL: vp_ctlz_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
declare <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i64> @vp_ctlz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_ctlz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv4i64: ; RV32-LABEL: vp_ctlz_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI40_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI40_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vp_ctlz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_ctlz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv4i64_unmasked: ; RV32-LABEL: vp_ctlz_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
declare <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64>, <vscale x 7 x i1>, i32, i1) declare <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64>, i1 immarg, <vscale x 7 x i1>, i32)
define <vscale x 7 x i64> @vp_ctlz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_ctlz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv7i64: ; RV32-LABEL: vp_ctlz_nxv7i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI42_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI42_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 7 x i64> @vp_ctlz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_ctlz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv7i64_unmasked: ; RV32-LABEL: vp_ctlz_nxv7i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 7 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 7 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
%v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
declare <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i64> @vp_ctlz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_ctlz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv8i64: ; RV32-LABEL: vp_ctlz_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI44_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI44_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vp_ctlz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_ctlz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv8i64_unmasked: ; RV32-LABEL: vp_ctlz_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
declare <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv16i64: ; RV32-LABEL: vp_ctlz_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
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; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 16 x i64> @vp_ctlz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_ctlz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_nxv16i64_unmasked: ; RV32-LABEL: vp_ctlz_nxv16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t ; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
; RV64-NEXT: vand.vx v8, v8, a5, v0.t ; RV64-NEXT: vand.vx v8, v8, a5, v0.t
; RV64-NEXT: vmul.vx v8, v8, a6, v0.t ; RV64-NEXT: vmul.vx v8, v8, a6, v0.t
; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vand.vx v10, v8, a0, v0.t ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 1 ; CHECK-NEXT: vsrl.vi v10, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: vsrl.vi v10, v8, 4 ; CHECK-NEXT: vsrl.vi v10, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
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; CHECK-NEXT: vand.vx v12, v8, a0, v0.t ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 1 ; CHECK-NEXT: vsrl.vi v12, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v12, v8 ; CHECK-NEXT: vadd.vv v8, v12, v8
; CHECK-NEXT: vsrl.vi v12, v8, 4 ; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vand.vx v16, v8, a0, v0.t ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 1 ; CHECK-NEXT: vsrl.vi v16, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v16, v8 ; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4 ; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
%v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv1i16: ; RV32-LABEL: vp_ctlz_zero_undef_nxv1i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv1i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv1i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv2i16: ; RV32-LABEL: vp_ctlz_zero_undef_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv2i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv4i16: ; RV32-LABEL: vp_ctlz_zero_undef_nxv4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv4i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv8i16: ; RV32-LABEL: vp_ctlz_zero_undef_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv8i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv16i16: ; RV32-LABEL: vp_ctlz_zero_undef_nxv16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv16i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: vsrl.vi v12, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv32i16: ; RV32-LABEL: vp_ctlz_zero_undef_nxv32i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv32i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv32i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv1i32: ; RV32-LABEL: vp_ctlz_zero_undef_nxv1i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv1i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv1i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv2i32: ; RV32-LABEL: vp_ctlz_zero_undef_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv2i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv4i32: ; RV32-LABEL: vp_ctlz_zero_undef_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv4i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv8i32: ; RV32-LABEL: vp_ctlz_zero_undef_nxv8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv8i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: vsrl.vi v12, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv16i32: ; RV32-LABEL: vp_ctlz_zero_undef_nxv16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv1i64: ; RV32-LABEL: vp_ctlz_zero_undef_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI84_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI84_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv2i64: ; RV32-LABEL: vp_ctlz_zero_undef_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI86_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI86_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v10 ; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv4i64: ; RV32-LABEL: vp_ctlz_zero_undef_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI88_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI88_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v12 ; RV64-NEXT: vadd.vv v8, v8, v12
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv7i64: ; RV32-LABEL: vp_ctlz_zero_undef_nxv7i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI90_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI90_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
%v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv8i64: ; RV32-LABEL: vp_ctlz_zero_undef_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI92_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI92_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv16i64: ; RV32-LABEL: vp_ctlz_zero_undef_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_nxv16i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_nxv16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vi v24, v8, 4 ; RV64-NEXT: vsrl.vi v24, v8, 4
; RV64-NEXT: vadd.vv v8, v8, v24 ; RV64-NEXT: vadd.vv v8, v8, v24
; RV64-NEXT: vand.vx v8, v8, a5 ; RV64-NEXT: vand.vx v8, v8, a5
; RV64-NEXT: vmul.vx v8, v8, a6 ; RV64-NEXT: vmul.vx v8, v8, a6
; RV64-NEXT: vsrl.vx v8, v8, a7 ; RV64-NEXT: vsrl.vx v8, v8, a7
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32, i1 immarg) declare <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @vp_cttz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_cttz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i8: ; CHECK-LABEL: vp_cttz_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 1 x i8> @vp_cttz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_cttz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv1i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv1i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
declare <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @vp_cttz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_cttz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i8: ; CHECK-LABEL: vp_cttz_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 2 x i8> @vp_cttz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_cttz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv2i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
declare <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @vp_cttz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_cttz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i8: ; CHECK-LABEL: vp_cttz_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @vp_cttz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_cttz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv4i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
declare <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @vp_cttz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_cttz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i8: ; CHECK-LABEL: vp_cttz_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 8 x i8> @vp_cttz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_cttz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv8i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
declare <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i8: ; CHECK-LABEL: vp_cttz_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v10, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t ; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t ; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v10, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v10, v8, a0, v0.t ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @vp_cttz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_cttz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv16i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
declare <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i1>, i32, i1) declare <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv32i8: ; CHECK-LABEL: vp_cttz_nxv32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v12, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t ; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v12, v8, a0, v0.t ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 32 x i8> @vp_cttz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_cttz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv32i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv32i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
declare <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i1>, i32, i1) declare <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv64i8: ; CHECK-LABEL: vp_cttz_nxv64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v16, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t ; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v16, v8, a0, v0.t ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 64 x i8> @vp_cttz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_cttz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_nxv64i8_unmasked: ; CHECK-LABEL: vp_cttz_nxv64i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 64 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
declare <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @vp_cttz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_cttz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv1i16: ; RV32-LABEL: vp_cttz_nxv1i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 1 x i16> @vp_cttz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_cttz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv1i16_unmasked: ; RV32-LABEL: vp_cttz_nxv1i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
declare <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @vp_cttz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_cttz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv2i16: ; RV32-LABEL: vp_cttz_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 2 x i16> @vp_cttz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_cttz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv2i16_unmasked: ; RV32-LABEL: vp_cttz_nxv2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
declare <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @vp_cttz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_cttz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv4i16: ; RV32-LABEL: vp_cttz_nxv4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 4 x i16> @vp_cttz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_cttz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv4i16_unmasked: ; RV32-LABEL: vp_cttz_nxv4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
declare <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv8i16: ; RV32-LABEL: vp_cttz_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t ; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @vp_cttz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_cttz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv8i16_unmasked: ; RV32-LABEL: vp_cttz_nxv8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
declare <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv16i16: ; RV32-LABEL: vp_cttz_nxv16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t ; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 16 x i16> @vp_cttz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_cttz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv16i16_unmasked: ; RV32-LABEL: vp_cttz_nxv16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
declare <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i1>, i32, i1) declare <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv32i16: ; RV32-LABEL: vp_cttz_nxv32i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t ; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 32 x i16> @vp_cttz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_cttz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv32i16_unmasked: ; RV32-LABEL: vp_cttz_nxv32i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
declare <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @vp_cttz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_cttz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv1i32: ; RV32-LABEL: vp_cttz_nxv1i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 1 x i32> @vp_cttz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_cttz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv1i32_unmasked: ; RV32-LABEL: vp_cttz_nxv1i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
declare <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @vp_cttz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_cttz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv2i32: ; RV32-LABEL: vp_cttz_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 2 x i32> @vp_cttz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_cttz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv2i32_unmasked: ; RV32-LABEL: vp_cttz_nxv2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
declare <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv4i32: ; RV32-LABEL: vp_cttz_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t ; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 4 x i32> @vp_cttz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_cttz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv4i32_unmasked: ; RV32-LABEL: vp_cttz_nxv4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
declare <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv8i32: ; RV32-LABEL: vp_cttz_nxv8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t ; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @vp_cttz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_cttz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv8i32_unmasked: ; RV32-LABEL: vp_cttz_nxv8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
declare <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv16i32: ; RV32-LABEL: vp_cttz_nxv16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t ; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @vp_cttz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_cttz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv16i32_unmasked: ; RV32-LABEL: vp_cttz_nxv16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
declare <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i1>, i32, i1) declare <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv1i64: ; RV32-LABEL: vp_cttz_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI36_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI36_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vp_cttz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_cttz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv1i64_unmasked: ; RV32-LABEL: vp_cttz_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
declare <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32, i1) declare <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv2i64: ; RV32-LABEL: vp_cttz_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI38_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI38_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_cttz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv2i64_unmasked: ; RV32-LABEL: vp_cttz_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
declare <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i1>, i32, i1) declare <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv4i64: ; RV32-LABEL: vp_cttz_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI40_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI40_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_cttz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv4i64_unmasked: ; RV32-LABEL: vp_cttz_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
declare <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64>, <vscale x 7 x i1>, i32, i1) declare <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64>, i1 immarg, <vscale x 7 x i1>, i32)
define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv7i64: ; RV32-LABEL: vp_cttz_nxv7i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI42_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI42_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_cttz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv7i64_unmasked: ; RV32-LABEL: vp_cttz_nxv7i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 7 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 7 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
declare <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i1>, i32, i1) declare <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv8i64: ; RV32-LABEL: vp_cttz_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
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; RV64-NEXT: ld a1, %lo(.LCPI44_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI44_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_cttz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv8i64_unmasked: ; RV32-LABEL: vp_cttz_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
declare <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32, i1) declare <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv16i64: ; RV32-LABEL: vp_cttz_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
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; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_cttz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_nxv16i64_unmasked: ; RV32-LABEL: vp_cttz_nxv16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t ; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
; RV64-NEXT: vand.vx v8, v8, a5, v0.t ; RV64-NEXT: vand.vx v8, v8, a5, v0.t
; RV64-NEXT: vmul.vx v8, v8, a6, v0.t ; RV64-NEXT: vmul.vx v8, v8, a6, v0.t
; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 false, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 false) %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv1i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i8> @llvm.vp.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i8> %v ret <vscale x 1 x i8> %v
} }
define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i8> @llvm.vp.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i8> %v ret <vscale x 2 x i8> %v
} }
define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i8> @llvm.vp.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i8> @llvm.vp.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i8> %v ret <vscale x 8 x i8> %v
} }
define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: vand.vx v10, v8, a0, v0.t ; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: vadd.vv v8, v10, v8
; CHECK-NEXT: vsrl.vi v10, v8, 4 ; CHECK-NEXT: vsrl.vi v10, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i8> @llvm.vp.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: vand.vx v12, v8, a0, v0.t ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv32i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v12, v8 ; CHECK-NEXT: vadd.vv v8, v12, v8
; CHECK-NEXT: vsrl.vi v12, v8, 4 ; CHECK-NEXT: vsrl.vi v12, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i8> @llvm.vp.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8: ; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: vand.vx v16, v8, a0, v0.t ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_nxv64i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v16, v8 ; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsrl.vi v16, v8, 4 ; CHECK-NEXT: vsrl.vi v16, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer
%v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 64 x i8> @llvm.vp.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i8> %v ret <vscale x 64 x i8> %v
} }
define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv1i16: ; RV32-LABEL: vp_cttz_zero_undef_nxv1i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv1i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i16> @llvm.vp.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i16> %v ret <vscale x 1 x i16> %v
} }
define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv2i16: ; RV32-LABEL: vp_cttz_zero_undef_nxv2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i16> @llvm.vp.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i16> %v ret <vscale x 2 x i16> %v
} }
define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv4i16: ; RV32-LABEL: vp_cttz_zero_undef_nxv4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i16> @llvm.vp.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i16> %v ret <vscale x 4 x i16> %v
} }
define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv8i16: ; RV32-LABEL: vp_cttz_zero_undef_nxv8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i16> @llvm.vp.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i16> %v ret <vscale x 8 x i16> %v
} }
define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv16i16: ; RV32-LABEL: vp_cttz_zero_undef_nxv16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m4, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i16> @llvm.vp.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i16> %v ret <vscale x 16 x i16> %v
} }
define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv32i16: ; RV32-LABEL: vp_cttz_zero_undef_nxv32i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv32i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m8, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 32 x i16> @llvm.vp.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i16> %v ret <vscale x 32 x i16> %v
} }
define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv1i32: ; RV32-LABEL: vp_cttz_zero_undef_nxv1i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv1i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i32> @llvm.vp.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i32> %v ret <vscale x 1 x i32> %v
} }
define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv2i32: ; RV32-LABEL: vp_cttz_zero_undef_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i32> @llvm.vp.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i32> %v ret <vscale x 2 x i32> %v
} }
define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv4i32: ; RV32-LABEL: vp_cttz_zero_undef_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i32> @llvm.vp.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i32> %v ret <vscale x 4 x i32> %v
} }
define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv8i32: ; RV32-LABEL: vp_cttz_zero_undef_nxv8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i32> @llvm.vp.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv16i32: ; RV32-LABEL: vp_cttz_zero_undef_nxv16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i32> @llvm.vp.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv1i64: ; RV32-LABEL: vp_cttz_zero_undef_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI84_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI84_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { define <vscale x 1 x i64> @vp_cttz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 1 x i64> @llvm.vp.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv2i64: ; RV32-LABEL: vp_cttz_zero_undef_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI86_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI86_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { define <vscale x 2 x i64> @vp_cttz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v10 ; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 2 x i64> @llvm.vp.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv4i64: ; RV32-LABEL: vp_cttz_zero_undef_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI88_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI88_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { define <vscale x 4 x i64> @vp_cttz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v12 ; RV64-NEXT: vadd.vv v8, v8, v12
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 4 x i64> @llvm.vp.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv7i64: ; RV32-LABEL: vp_cttz_zero_undef_nxv7i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI90_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI90_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_cttz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv7i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 7 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer %m = shufflevector <vscale x 7 x i1> %head, <vscale x 7 x i1> poison, <vscale x 7 x i32> zeroinitializer
%v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 7 x i64> @llvm.vp.cttz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
ret <vscale x 7 x i64> %v ret <vscale x 7 x i64> %v
} }
define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv8i64: ; RV32-LABEL: vp_cttz_zero_undef_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
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; RV64-NEXT: ld a1, %lo(.LCPI92_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI92_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 8 x i64> @llvm.vp.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv16i64: ; RV32-LABEL: vp_cttz_zero_undef_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a7, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_nxv16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vi v24, v8, 4 ; RV64-NEXT: vsrl.vi v24, v8, 4
; RV64-NEXT: vadd.vv v8, v8, v24 ; RV64-NEXT: vadd.vv v8, v8, v24
; RV64-NEXT: vand.vx v8, v8, a5 ; RV64-NEXT: vand.vx v8, v8, a5
; RV64-NEXT: vmul.vx v8, v8, a6 ; RV64-NEXT: vmul.vx v8, v8, a6
; RV64-NEXT: vsrl.vx v8, v8, a7 ; RV64-NEXT: vsrl.vx v8, v8, a7
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
%m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 %evl, i1 true) %v = call <vscale x 16 x i64> @llvm.vp.cttz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
declare <2 x i8> @llvm.vp.abs.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) declare <2 x i8> @llvm.vp.abs.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)
define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i8: ; CHECK-LABEL: vp_abs_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <2 x i8> @vp_abs_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { define <2 x i8> @vp_abs_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i8_unmasked: ; CHECK-LABEL: vp_abs_v2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
declare <4 x i8> @llvm.vp.abs.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) declare <4 x i8> @llvm.vp.abs.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32)
define <4 x i8> @vp_abs_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i8> @vp_abs_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i8: ; CHECK-LABEL: vp_abs_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <4 x i8> @vp_abs_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { define <4 x i8> @vp_abs_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i8_unmasked: ; CHECK-LABEL: vp_abs_v4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
declare <8 x i8> @llvm.vp.abs.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) declare <8 x i8> @llvm.vp.abs.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32)
define <8 x i8> @vp_abs_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i8> @vp_abs_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i8: ; CHECK-LABEL: vp_abs_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <8 x i8> @vp_abs_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { define <8 x i8> @vp_abs_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i8_unmasked: ; CHECK-LABEL: vp_abs_v8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
declare <16 x i8> @llvm.vp.abs.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) declare <16 x i8> @llvm.vp.abs.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32)
define <16 x i8> @vp_abs_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i8> @vp_abs_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i8: ; CHECK-LABEL: vp_abs_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <16 x i8> @vp_abs_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { define <16 x i8> @vp_abs_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i8_unmasked: ; CHECK-LABEL: vp_abs_v16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
declare <2 x i16> @llvm.vp.abs.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) declare <2 x i16> @llvm.vp.abs.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32)
define <2 x i16> @vp_abs_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i16> @vp_abs_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i16: ; CHECK-LABEL: vp_abs_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <2 x i16> @vp_abs_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { define <2 x i16> @vp_abs_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i16_unmasked: ; CHECK-LABEL: vp_abs_v2i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
declare <4 x i16> @llvm.vp.abs.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) declare <4 x i16> @llvm.vp.abs.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32)
define <4 x i16> @vp_abs_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vp_abs_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i16: ; CHECK-LABEL: vp_abs_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <4 x i16> @vp_abs_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { define <4 x i16> @vp_abs_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i16_unmasked: ; CHECK-LABEL: vp_abs_v4i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
declare <8 x i16> @llvm.vp.abs.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) declare <8 x i16> @llvm.vp.abs.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32)
define <8 x i16> @vp_abs_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i16> @vp_abs_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i16: ; CHECK-LABEL: vp_abs_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <8 x i16> @vp_abs_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { define <8 x i16> @vp_abs_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i16_unmasked: ; CHECK-LABEL: vp_abs_v8i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
declare <16 x i16> @llvm.vp.abs.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) declare <16 x i16> @llvm.vp.abs.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32)
define <16 x i16> @vp_abs_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i16> @vp_abs_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i16: ; CHECK-LABEL: vp_abs_v16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <16 x i16> @vp_abs_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { define <16 x i16> @vp_abs_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i16_unmasked: ; CHECK-LABEL: vp_abs_v16i16_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
declare <2 x i32> @llvm.vp.abs.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) declare <2 x i32> @llvm.vp.abs.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32)
define <2 x i32> @vp_abs_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i32> @vp_abs_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i32: ; CHECK-LABEL: vp_abs_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <2 x i32> @vp_abs_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { define <2 x i32> @vp_abs_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i32_unmasked: ; CHECK-LABEL: vp_abs_v2i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
declare <4 x i32> @llvm.vp.abs.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) declare <4 x i32> @llvm.vp.abs.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32)
define <4 x i32> @vp_abs_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i32> @vp_abs_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i32: ; CHECK-LABEL: vp_abs_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <4 x i32> @vp_abs_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { define <4 x i32> @vp_abs_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i32_unmasked: ; CHECK-LABEL: vp_abs_v4i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
declare <8 x i32> @llvm.vp.abs.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) declare <8 x i32> @llvm.vp.abs.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32)
define <8 x i32> @vp_abs_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i32> @vp_abs_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i32: ; CHECK-LABEL: vp_abs_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <8 x i32> @vp_abs_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { define <8 x i32> @vp_abs_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i32_unmasked: ; CHECK-LABEL: vp_abs_v8i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
declare <16 x i32> @llvm.vp.abs.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) declare <16 x i32> @llvm.vp.abs.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32)
define <16 x i32> @vp_abs_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i32> @vp_abs_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i32: ; CHECK-LABEL: vp_abs_v16i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <16 x i32> @vp_abs_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { define <16 x i32> @vp_abs_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i32_unmasked: ; CHECK-LABEL: vp_abs_v16i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
declare <2 x i64> @llvm.vp.abs.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) declare <2 x i64> @llvm.vp.abs.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32)
define <2 x i64> @vp_abs_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vp_abs_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i64: ; CHECK-LABEL: vp_abs_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_abs_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_abs_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v2i64_unmasked: ; CHECK-LABEL: vp_abs_v2i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
declare <4 x i64> @llvm.vp.abs.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) declare <4 x i64> @llvm.vp.abs.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32)
define <4 x i64> @vp_abs_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vp_abs_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i64: ; CHECK-LABEL: vp_abs_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_abs_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_abs_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v4i64_unmasked: ; CHECK-LABEL: vp_abs_v4i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <8 x i64> @llvm.vp.abs.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) declare <8 x i64> @llvm.vp.abs.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32)
define <8 x i64> @vp_abs_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vp_abs_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i64: ; CHECK-LABEL: vp_abs_v8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_abs_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_abs_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v8i64_unmasked: ; CHECK-LABEL: vp_abs_v8i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
declare <15 x i64> @llvm.vp.abs.v15i64(<15 x i64>, <15 x i1>, i32, i1 immarg) declare <15 x i64> @llvm.vp.abs.v15i64(<15 x i64>, i1 immarg, <15 x i1>, i32)
define <15 x i64> @vp_abs_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_abs_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v15i64: ; CHECK-LABEL: vp_abs_v15i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_abs_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_abs_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v15i64_unmasked: ; CHECK-LABEL: vp_abs_v15i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <15 x i1> poison, i1 true, i32 0 %head = insertelement <15 x i1> poison, i1 true, i32 0
%m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer
%v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
declare <16 x i64> @llvm.vp.abs.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) declare <16 x i64> @llvm.vp.abs.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32)
define <16 x i64> @vp_abs_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_abs_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i64: ; CHECK-LABEL: vp_abs_v16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_abs_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_abs_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v16i64_unmasked: ; CHECK-LABEL: vp_abs_v16i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
declare <32 x i64> @llvm.vp.abs.v32i64(<32 x i64>, <32 x i1>, i32, i1 immarg) declare <32 x i64> @llvm.vp.abs.v32i64(<32 x i64>, i1 immarg, <32 x i1>, i32)
define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v32i64: ; CHECK-LABEL: vp_abs_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: vslidedown.vi v1, v0, 2 ; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: mv a1, a0 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2 ; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB34_2: ; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0, v0.t ; CHECK-NEXT: vrsub.vi v24, v8, 0, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1 ; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1 ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t ; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_abs_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_abs_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_v32i64_unmasked: ; CHECK-LABEL: vp_abs_v32i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
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; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1 ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t ; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <32 x i1> poison, i1 true, i32 0 %head = insertelement <32 x i1> poison, i1 true, i32 0
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)
define <2 x i8> @vp_ctlz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i8> @vp_ctlz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i8: ; CHECK-LABEL: vp_ctlz_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <2 x i8> @vp_ctlz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { define <2 x i8> @vp_ctlz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v2i8_unmasked: ; CHECK-LABEL: vp_ctlz_v2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32)
define <4 x i8> @vp_ctlz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i8> @vp_ctlz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i8: ; CHECK-LABEL: vp_ctlz_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <4 x i8> @vp_ctlz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { define <4 x i8> @vp_ctlz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v4i8_unmasked: ; CHECK-LABEL: vp_ctlz_v4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32)
define <8 x i8> @vp_ctlz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i8> @vp_ctlz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i8: ; CHECK-LABEL: vp_ctlz_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <8 x i8> @vp_ctlz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { define <8 x i8> @vp_ctlz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v8i8_unmasked: ; CHECK-LABEL: vp_ctlz_v8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32)
define <16 x i8> @vp_ctlz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i8> @vp_ctlz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i8: ; CHECK-LABEL: vp_ctlz_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <16 x i8> @vp_ctlz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { define <16 x i8> @vp_ctlz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_v16i8_unmasked: ; CHECK-LABEL: vp_ctlz_v16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32)
define <2 x i16> @vp_ctlz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i16> @vp_ctlz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v2i16: ; RV32-LABEL: vp_ctlz_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <2 x i16> @vp_ctlz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { define <2 x i16> @vp_ctlz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v2i16_unmasked: ; RV32-LABEL: vp_ctlz_v2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32)
define <4 x i16> @vp_ctlz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vp_ctlz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i16: ; RV32-LABEL: vp_ctlz_v4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <4 x i16> @vp_ctlz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { define <4 x i16> @vp_ctlz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i16_unmasked: ; RV32-LABEL: vp_ctlz_v4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32)
define <8 x i16> @vp_ctlz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i16> @vp_ctlz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i16: ; RV32-LABEL: vp_ctlz_v8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <8 x i16> @vp_ctlz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { define <8 x i16> @vp_ctlz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i16_unmasked: ; RV32-LABEL: vp_ctlz_v8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32)
define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v16i16: ; RV32-LABEL: vp_ctlz_v16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v16i16_unmasked: ; RV32-LABEL: vp_ctlz_v16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32)
define <2 x i32> @vp_ctlz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i32> @vp_ctlz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v2i32: ; RV32-LABEL: vp_ctlz_v2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <2 x i32> @vp_ctlz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { define <2 x i32> @vp_ctlz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v2i32_unmasked: ; RV32-LABEL: vp_ctlz_v2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32)
define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i32: ; RV32-LABEL: vp_ctlz_v4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <4 x i32> @vp_ctlz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { define <4 x i32> @vp_ctlz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i32_unmasked: ; RV32-LABEL: vp_ctlz_v4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32)
define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i32: ; RV32-LABEL: vp_ctlz_v8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i32_unmasked: ; RV32-LABEL: vp_ctlz_v8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32)
define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v16i32: ; RV32-LABEL: vp_ctlz_v16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v16i32_unmasked: ; RV32-LABEL: vp_ctlz_v16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32)
define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v2i64: ; RV32-LABEL: vp_ctlz_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI24_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI24_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v2i64_unmasked: ; RV32-LABEL: vp_ctlz_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32)
define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i64: ; RV32-LABEL: vp_ctlz_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI26_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI26_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i64_unmasked: ; RV32-LABEL: vp_ctlz_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32)
define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i64: ; RV32-LABEL: vp_ctlz_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI28_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI28_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i64_unmasked: ; RV32-LABEL: vp_ctlz_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
declare <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64>, <15 x i1>, i32, i1 immarg) declare <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64>, i1 immarg, <15 x i1>, i32)
define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v15i64: ; RV32-LABEL: vp_ctlz_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI30_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI30_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v15i64_unmasked: ; RV32-LABEL: vp_ctlz_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <15 x i1> poison, i1 false, i32 0 %head = insertelement <15 x i1> poison, i1 false, i32 0
%m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer
%v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32)
define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v16i64: ; RV32-LABEL: vp_ctlz_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI32_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI32_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v16i64_unmasked: ; RV32-LABEL: vp_ctlz_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
declare <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64>, <32 x i1>, i32, i1 immarg) declare <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64>, i1 immarg, <32 x i1>, i32)
define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v32i64: ; RV32-LABEL: vp_ctlz_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
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; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t ; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v32i64_unmasked: ; RV32-LABEL: vp_ctlz_v32i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t ; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t ; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a4, v0.t ; RV64-NEXT: vand.vx v16, v16, a4, v0.t
; RV64-NEXT: vmul.vx v16, v16, a5, v0.t ; RV64-NEXT: vmul.vx v16, v16, a5, v0.t
; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t ; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <32 x i1> poison, i1 false, i32 0 %head = insertelement <32 x i1> poison, i1 false, i32 0
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i8: ; CHECK-LABEL: vp_ctlz_zero_undef_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v2i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_v2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i8: ; CHECK-LABEL: vp_ctlz_zero_undef_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v4i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_v4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i8: ; CHECK-LABEL: vp_ctlz_zero_undef_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v8i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_v8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i8: ; CHECK-LABEL: vp_ctlz_zero_undef_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_v16i8_unmasked: ; CHECK-LABEL: vp_ctlz_zero_undef_v16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: vsrl.vi v9, v8, 1
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v2i16: ; RV32-LABEL: vp_ctlz_zero_undef_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v2i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v4i16: ; RV32-LABEL: vp_ctlz_zero_undef_v4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v4i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v8i16: ; RV32-LABEL: vp_ctlz_zero_undef_v8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v8i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v16i16: ; RV32-LABEL: vp_ctlz_zero_undef_v16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v16i16_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v2i32: ; RV32-LABEL: vp_ctlz_zero_undef_v2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v2i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v4i32: ; RV32-LABEL: vp_ctlz_zero_undef_v4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v4i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v8i32: ; RV32-LABEL: vp_ctlz_zero_undef_v8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v8i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v16i32: ; RV32-LABEL: vp_ctlz_zero_undef_v16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v16i32_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: vsrl.vi v12, v8, 1
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v2i64: ; RV32-LABEL: vp_ctlz_zero_undef_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI60_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI60_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v2i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
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; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v4i64: ; RV32-LABEL: vp_ctlz_zero_undef_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI62_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI62_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v4i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
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; RV64-NEXT: vadd.vv v8, v8, v10 ; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v8i64: ; RV32-LABEL: vp_ctlz_zero_undef_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI64_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI64_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v8i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: vsrl.vi v12, v8, 1
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; RV64-NEXT: vadd.vv v8, v8, v12 ; RV64-NEXT: vadd.vv v8, v8, v12
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v15i64: ; RV32-LABEL: vp_ctlz_zero_undef_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI66_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI66_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v15i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <15 x i1> poison, i1 true, i32 0 %head = insertelement <15 x i1> poison, i1 true, i32 0
%m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer
%v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v16i64: ; RV32-LABEL: vp_ctlz_zero_undef_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
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; RV64-NEXT: ld a1, %lo(.LCPI68_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI68_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v16i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v32i64: ; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t ; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v32i64_unmasked: ; RV32-LABEL: vp_ctlz_zero_undef_v32i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: vmv8r.v v0, v16 ; RV32-NEXT: vmv8r.v v0, v16
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; RV64-NEXT: vsrl.vi v24, v16, 4 ; RV64-NEXT: vsrl.vi v24, v16, 4
; RV64-NEXT: vadd.vv v16, v16, v24 ; RV64-NEXT: vadd.vv v16, v16, v24
; RV64-NEXT: vand.vx v16, v16, a4 ; RV64-NEXT: vand.vx v16, v16, a4
; RV64-NEXT: vmul.vx v16, v16, a5 ; RV64-NEXT: vmul.vx v16, v16, a5
; RV64-NEXT: vsrl.vx v16, v16, a6 ; RV64-NEXT: vsrl.vx v16, v16, a6
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <32 x i1> poison, i1 true, i32 0 %head = insertelement <32 x i1> poison, i1 true, i32 0
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32)
define <2 x i8> @vp_cttz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i8> @vp_cttz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v2i8: ; CHECK-LABEL: vp_cttz_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <2 x i8> @vp_cttz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { define <2 x i8> @vp_cttz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v2i8_unmasked: ; CHECK-LABEL: vp_cttz_v2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32)
define <4 x i8> @vp_cttz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i8> @vp_cttz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v4i8: ; CHECK-LABEL: vp_cttz_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <4 x i8> @vp_cttz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { define <4 x i8> @vp_cttz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v4i8_unmasked: ; CHECK-LABEL: vp_cttz_v4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32)
define <8 x i8> @vp_cttz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i8> @vp_cttz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v8i8: ; CHECK-LABEL: vp_cttz_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <8 x i8> @vp_cttz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { define <8 x i8> @vp_cttz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v8i8_unmasked: ; CHECK-LABEL: vp_cttz_v8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32)
define <16 x i8> @vp_cttz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i8> @vp_cttz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v16i8: ; CHECK-LABEL: vp_cttz_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <16 x i8> @vp_cttz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { define <16 x i8> @vp_cttz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_v16i8_unmasked: ; CHECK-LABEL: vp_cttz_v16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32)
define <2 x i16> @vp_cttz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i16> @vp_cttz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v2i16: ; RV32-LABEL: vp_cttz_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <2 x i16> @vp_cttz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { define <2 x i16> @vp_cttz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v2i16_unmasked: ; RV32-LABEL: vp_cttz_v2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32)
define <4 x i16> @vp_cttz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vp_cttz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v4i16: ; RV32-LABEL: vp_cttz_v4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <4 x i16> @vp_cttz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { define <4 x i16> @vp_cttz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v4i16_unmasked: ; RV32-LABEL: vp_cttz_v4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32)
define <8 x i16> @vp_cttz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i16> @vp_cttz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v8i16: ; RV32-LABEL: vp_cttz_v8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <8 x i16> @vp_cttz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { define <8 x i16> @vp_cttz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v8i16_unmasked: ; RV32-LABEL: vp_cttz_v8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32)
define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v16i16: ; RV32-LABEL: vp_cttz_v16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t ; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <16 x i16> @vp_cttz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { define <16 x i16> @vp_cttz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v16i16_unmasked: ; RV32-LABEL: vp_cttz_v16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32)
define <2 x i32> @vp_cttz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i32> @vp_cttz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v2i32: ; RV32-LABEL: vp_cttz_v2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <2 x i32> @vp_cttz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { define <2 x i32> @vp_cttz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v2i32_unmasked: ; RV32-LABEL: vp_cttz_v2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32)
define <4 x i32> @vp_cttz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i32> @vp_cttz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v4i32: ; RV32-LABEL: vp_cttz_v4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <4 x i32> @vp_cttz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { define <4 x i32> @vp_cttz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v4i32_unmasked: ; RV32-LABEL: vp_cttz_v4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32)
define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v8i32: ; RV32-LABEL: vp_cttz_v8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t ; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <8 x i32> @vp_cttz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { define <8 x i32> @vp_cttz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v8i32_unmasked: ; RV32-LABEL: vp_cttz_v8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32)
define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v16i32: ; RV32-LABEL: vp_cttz_v16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t ; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t ; RV32-NEXT: vnot.v v8, v8, v0.t
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <16 x i32> @vp_cttz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { define <16 x i32> @vp_cttz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v16i32_unmasked: ; RV32-LABEL: vp_cttz_v16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32)
define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v2i64: ; RV32-LABEL: vp_cttz_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsub.vx v9, v8, a1, v0.t ; RV32-NEXT: vsub.vx v9, v8, a1, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI24_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI24_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_cttz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_cttz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v2i64_unmasked: ; RV32-LABEL: vp_cttz_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 false, i32 0 %head = insertelement <2 x i1> poison, i1 false, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32)
define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v4i64: ; RV32-LABEL: vp_cttz_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsub.vx v10, v8, a1, v0.t ; RV32-NEXT: vsub.vx v10, v8, a1, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI26_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI26_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v4i64_unmasked: ; RV32-LABEL: vp_cttz_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 false, i32 0 %head = insertelement <4 x i1> poison, i1 false, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32)
define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v8i64: ; RV32-LABEL: vp_cttz_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsub.vx v12, v8, a1, v0.t ; RV32-NEXT: vsub.vx v12, v8, a1, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI28_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI28_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v8i64_unmasked: ; RV32-LABEL: vp_cttz_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 false, i32 0 %head = insertelement <8 x i1> poison, i1 false, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
declare <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64>, <15 x i1>, i32, i1 immarg) declare <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64>, i1 immarg, <15 x i1>, i32)
define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v15i64: ; RV32-LABEL: vp_cttz_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t ; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
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; RV64-NEXT: ld a1, %lo(.LCPI30_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI30_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v15i64_unmasked: ; RV32-LABEL: vp_cttz_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <15 x i1> poison, i1 false, i32 0 %head = insertelement <15 x i1> poison, i1 false, i32 0
%m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer
%v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32)
define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v16i64: ; RV32-LABEL: vp_cttz_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v8, a1, v0.t ; RV32-NEXT: vsub.vx v16, v8, a1, v0.t
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
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; RV64-NEXT: ld a1, %lo(.LCPI32_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI32_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v16i64_unmasked: ; RV32-LABEL: vp_cttz_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmclr.m v0 ; RV32-NEXT: vmclr.m v0
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; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 false, i32 0 %head = insertelement <16 x i1> poison, i1 false, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
declare <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64>, <32 x i1>, i32, i1 immarg) declare <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64>, i1 immarg, <32 x i1>, i32)
define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v32i64: ; RV32-LABEL: vp_cttz_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 6 ; RV32-NEXT: slli a1, a1, 6
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; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t ; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_v32i64_unmasked: ; RV32-LABEL: vp_cttz_v32i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t ; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t ; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a4, v0.t ; RV64-NEXT: vand.vx v16, v16, a4, v0.t
; RV64-NEXT: vmul.vx v16, v16, a5, v0.t ; RV64-NEXT: vmul.vx v16, v16, a5, v0.t
; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t ; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <32 x i1> poison, i1 false, i32 0 %head = insertelement <32 x i1> poison, i1 false, i32 0
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v2i8: ; CHECK-LABEL: vp_cttz_zero_undef_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v2i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_v2i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i8> %v ret <2 x i8> %v
} }
define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v4i8: ; CHECK-LABEL: vp_cttz_zero_undef_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v4i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_v4i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i8> %v ret <4 x i8> %v
} }
define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v8i8: ; CHECK-LABEL: vp_cttz_zero_undef_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v8i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_v8i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i8> %v ret <8 x i8> %v
} }
define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v16i8: ; CHECK-LABEL: vp_cttz_zero_undef_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t ; CHECK-NEXT: vsub.vx v9, v8, a1, v0.t
; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t ; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vand.vx v9, v8, a0, v0.t ; CHECK-NEXT: vand.vx v9, v8, a0, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t ; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_v16i8_unmasked: ; CHECK-LABEL: vp_cttz_zero_undef_v16i8_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vand.vx v8, v8, a0
; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vsrl.vi v9, v8, 4
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: vand.vi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i8> %v ret <16 x i8> %v
} }
define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v2i16: ; RV32-LABEL: vp_cttz_zero_undef_v2i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v2i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v2i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i16> %v ret <2 x i16> %v
} }
define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v4i16: ; RV32-LABEL: vp_cttz_zero_undef_v4i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v4i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v4i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i16> %v ret <4 x i16> %v
} }
define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v8i16: ; RV32-LABEL: vp_cttz_zero_undef_v8i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v8i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v8i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i16> %v ret <8 x i16> %v
} }
define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v16i16: ; RV32-LABEL: vp_cttz_zero_undef_v16i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: lui a0, 1 ; RV64-NEXT: lui a0, 1
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v16i16_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v16i16_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: li a0, 257 ; RV64-NEXT: li a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsrl.vi v8, v8, 8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i16> %v ret <16 x i16> %v
} }
define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v2i32: ; RV32-LABEL: vp_cttz_zero_undef_v2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v2i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v2i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i32> %v ret <2 x i32> %v
} }
define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v4i32: ; RV32-LABEL: vp_cttz_zero_undef_v4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v4i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v4i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i32> %v ret <4 x i32> %v
} }
define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v8i32: ; RV32-LABEL: vp_cttz_zero_undef_v8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v8i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v8i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i32> %v ret <8 x i32> %v
} }
define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v16i32: ; RV32-LABEL: vp_cttz_zero_undef_v16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
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; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v16i32_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v16i32_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma
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; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: lui a0, 4112
; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: addiw a0, a0, 257
; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 24 ; RV64-NEXT: vsrl.vi v8, v8, 24
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i32> %v ret <16 x i32> %v
} }
define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v2i64: ; RV32-LABEL: vp_cttz_zero_undef_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI60_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI60_3)(a1)
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t ; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v2i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <2 x i1> poison, i1 true, i32 0 %head = insertelement <2 x i1> poison, i1 true, i32 0
%m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v4i64: ; RV32-LABEL: vp_cttz_zero_undef_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI62_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI62_3)(a1)
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t ; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v4i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v10 ; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0 %head = insertelement <4 x i1> poison, i1 true, i32 0
%m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v8i64: ; RV32-LABEL: vp_cttz_zero_undef_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI64_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI64_3)(a1)
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t ; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v8i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v12 ; RV64-NEXT: vadd.vv v8, v8, v12
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <8 x i1> poison, i1 true, i32 0 %head = insertelement <8 x i1> poison, i1 true, i32 0
%m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v15i64: ; RV32-LABEL: vp_cttz_zero_undef_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI66_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI66_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v15i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
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; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <15 x i1> poison, i1 true, i32 0 %head = insertelement <15 x i1> poison, i1 true, i32 0
%m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer
%v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v16i64: ; RV32-LABEL: vp_cttz_zero_undef_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
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; RV64-NEXT: ld a1, %lo(.LCPI68_3)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI68_3)(a1)
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t ; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vmul.vx v8, v8, a1, v0.t ; RV64-NEXT: vmul.vx v8, v8, a1, v0.t
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v16i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vadd.vv v8, v8, v16
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <16 x i1> poison, i1 true, i32 0 %head = insertelement <16 x i1> poison, i1 true, i32 0
%m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v32i64: ; RV32-LABEL: vp_cttz_zero_undef_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t ; RV64-NEXT: vsrl.vx v16, v8, a6, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_cttz_zero_undef_v32i64_unmasked: ; RV32-LABEL: vp_cttz_zero_undef_v32i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: vmv8r.v v0, v16 ; RV32-NEXT: vmv8r.v v0, v16
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; RV64-NEXT: vsrl.vi v24, v16, 4 ; RV64-NEXT: vsrl.vi v24, v16, 4
; RV64-NEXT: vadd.vv v16, v16, v24 ; RV64-NEXT: vadd.vv v16, v16, v24
; RV64-NEXT: vand.vx v16, v16, a4 ; RV64-NEXT: vand.vx v16, v16, a4
; RV64-NEXT: vmul.vx v16, v16, a5 ; RV64-NEXT: vmul.vx v16, v16, a5
; RV64-NEXT: vsrl.vx v16, v16, a6 ; RV64-NEXT: vsrl.vx v16, v16, a6
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <32 x i1> poison, i1 true, i32 0 %head = insertelement <32 x i1> poison, i1 true, i32 0
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/unittests/IR/VPIntrinsicTest.cpp

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines Str << " declare <8 x i32*> @llvm.vp.inttoptr.v8p0i32"
<< ".v8i32(<8 x i32>, <8 x i1>, i32) "; << ".v8i32(<8 x i32>, <8 x i1>, i32) ";
Str << " declare <8 x i1> @llvm.vp.fcmp.v8f32" Str << " declare <8 x i1> @llvm.vp.fcmp.v8f32"
<< "(<8 x float>, <8 x float>, metadata, <8 x i1>, i32) "; << "(<8 x float>, <8 x float>, metadata, <8 x i1>, i32) ";
Str << " declare <8 x i1> @llvm.vp.icmp.v8i16" Str << " declare <8 x i1> @llvm.vp.icmp.v8i16"
<< "(<8 x i16>, <8 x i16>, metadata, <8 x i1>, i32) "; << "(<8 x i16>, <8 x i16>, metadata, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.abs.v8i16" Str << " declare <8 x i16> @llvm.vp.abs.v8i16"
<< "(<8 x i16>, <8 x i1>, i32, i1 immarg) "; << "(<8 x i16>, i1 immarg, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.bitreverse.v8i16" Str << " declare <8 x i16> @llvm.vp.bitreverse.v8i16"
<< "(<8 x i16>, <8 x i1>, i32) "; << "(<8 x i16>, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.bswap.v8i16" Str << " declare <8 x i16> @llvm.vp.bswap.v8i16"
<< "(<8 x i16>, <8 x i1>, i32) "; << "(<8 x i16>, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.ctpop.v8i16" Str << " declare <8 x i16> @llvm.vp.ctpop.v8i16"
<< "(<8 x i16>, <8 x i1>, i32) "; << "(<8 x i16>, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.ctlz.v8i16" Str << " declare <8 x i16> @llvm.vp.ctlz.v8i16"
<< "(<8 x i16>, <8 x i1>, i32, i1 immarg) "; << "(<8 x i16>, i1 immarg, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.cttz.v8i16" Str << " declare <8 x i16> @llvm.vp.cttz.v8i16"
<< "(<8 x i16>, <8 x i1>, i32, i1 immarg) "; << "(<8 x i16>, i1 immarg, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.fshl.v8i16" Str << " declare <8 x i16> @llvm.vp.fshl.v8i16"
<< "(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>, i32) "; << "(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>, i32) ";
Str << " declare <8 x i16> @llvm.vp.fshr.v8i16" Str << " declare <8 x i16> @llvm.vp.fshr.v8i16"
<< "(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>, i32) "; << "(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>, i32) ";
return parseAssemblyString(Str.str(), Err, C); return parseAssemblyString(Str.str(), Err, C);
} }
}; };
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