[RISCV] Select signed and unsigned bitfield extracts for XTHeadBb

[philipp.tomsich]

Summary

The XTHeadBb extension hab both signed and unsigned bitfield
extraction instructions (TH.EXT and TH.EXTU, respectively) which have
previously only been supported for sign extension on byte, halfword,
and word-boundaries.

This adds the infrastructure to use TH.EXT and TH.EXTU for arbitrary
bitfield extraction.

[craig.topper]

llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll

1143 ↗

(On Diff #498179)

This looks worse

llvm/test/CodeGen/RISCV/rv32xtheadbb.ll

404

This looks worse

[philipp.tomsich]

• fix (and X C1) cases for th.extu
  • don't use th.extu if andi can be used
  • ensure it is used for bitfield extractions starting at bit 0 (instead of falling back to (shr (shl X C1) C2))

[philipp.tomsich]

• now depends on D144278 (commutativity fix for THeadMac)
• updated test cases (for this dependency)

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

698

What if LeftShAmt > RightShAmt?

1013

This can overflow is C2 is larger than the number of leading zeros in C1. That's what the if (C2 < Leading) at line 1014 is protecting. I think you want to be below that and probably below the SRLIW check at line 1016.

[philipp.tomsich]

• reject recognition of bitfield-extract if (shr (shl X c1) c2) has c1 > c2, which would leave the extracted bitfield at a bitposition > 0 (and turn the LSB negative...)
• add test-coverage for this case

[philipp.tomsich]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

698

Thanks! I added a test-case as well.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1014

Just to confirm, do you want th.extu preferred over this single SRLIW code?

[philipp.tomsich]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1014

I was about to say "Yes.", but just changed my mind: the standard instruction should always be preferred, if no performance difference (giving the vendor an easier way to eventually deprecate a custom extension by expanding into multiple u-ops).

So I'll change this one more time.

[philipp.tomsich]

• prefer SRLIW over TH.EXTU

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

public:
   bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
   bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
   bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
 
   bool tryShrinkShlLogicImm(SDNode *Node);
+  bool trySignedBitfieldExtract(SDNode *Node);
 
   bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
   bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
   }
   bool selectShiftMask32(SDValue N, SDValue &ShAmt) {
     return selectShiftMask(N, 32, ShAmt);
   }

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

SDNode *BinOp =
                              CurDAG->getTargetConstant(ShiftedVal, DL, VT));
   SDNode *SLLI =
       CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0),
                              CurDAG->getTargetConstant(ShAmt, DL, VT));
   ReplaceNode(Node, SLLI);
   return true;
 }
 
+bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
+  // Only supported with XTHeadBb at the moment.
+  if (!Subtarget->hasVendorXTHeadBb())
+    return false;
+
+  auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
+  if (!N1C)
+    return false;
+
+  SDValue N0 = Node->getOperand(0);
+  if (!N0.hasOneUse())
+    return false;
+
+  auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb, SDLoc DL,
+                             MVT VT) {
+    return CurDAG->getMachineNode(RISCV::TH_EXT, DL, VT, N0.getOperand(0),
+                                  CurDAG->getTargetConstant(Msb, DL, VT),
+                                  CurDAG->getTargetConstant(Lsb, DL, VT));
+  };
+
+  SDLoc DL(Node);
+  MVT VT = Node->getSimpleValueType(0);
+  const unsigned RightShAmt = N1C->getZExtValue();
+
+  // Transform (sra (shl X, C1) C2) with C1 < C2
+  //        -> (TH.EXT X, msb, lsb)
+  if (N0.getOpcode() == ISD::SHL) {
+    auto *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1));
+    if (!N01C)
+      return false;
+
+    const unsigned LeftShAmt = N01C->getZExtValue();
+    // Make sure that this is a bitfield extraction (i.e., the shift-right
+    // amount can not be less than the left-shift).
+    if (LeftShAmt > RightShAmt)
+      return false;
+
+    const unsigned MsbPlusOne = VT.getSizeInBits() - LeftShAmt;
+    const unsigned Msb = MsbPlusOne - 1;
+    const unsigned Lsb = RightShAmt - LeftShAmt;
+
+    SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT);
+    ReplaceNode(Node, TH_EXT);
+    return true;
+  }
+
+  // Transform (sra (sext_inreg X, _), C) ->
+  //           (TH.EXT X, msb, lsb)
+  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    unsigned ExtSize =
+        cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits();
+
+    // ExtSize of 32 should use sraiw via tablegen pattern.
+    if (ExtSize == 32)
+      return false;
+
+    const unsigned Msb = ExtSize - 1;
+    const unsigned Lsb = RightShAmt;
+
+    SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT);
+    ReplaceNode(Node, TH_EXT);
+    return true;
+  }
+
+  return false;
+}
+
 void RISCVDAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we have already selected.
   if (Node->isMachineOpcode()) {
     LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
     Node->setNodeId(-1);
     return;
   }
 
SDNode *SLLI =
                                CurDAG->getTargetConstant(LShAmt, DL, VT));
     SDNode *SRLI = CurDAG->getMachineNode(
         RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
         CurDAG->getTargetConstant(LShAmt + ShAmt, DL, VT));
     ReplaceNode(Node, SRLI);
     return;
   }
   case ISD::SRA: {
+    if (trySignedBitfieldExtract(Node))
+      return;
+
     // Optimize (sra (sext_inreg X, i16), C) ->
     //          (srai (slli X, (XLen-16), (XLen-16) + C)
     // And      (sra (sext_inreg X, i8), C) ->
     //          (srai (slli X, (XLen-8), (XLen-8) + C)
     // This can occur when Zbb is enabled, which makes sext_inreg i16/i8 legal.
     // This transform matches the code we get without Zbb. The shifts are more
     // compressible, and this can help expose CSE opportunities in the sdiv by
     // constant optimization.
case ISD::XOR:
     if (tryShrinkShlLogicImm(Node))
       return;
 
     break;
   case ISD::AND: {
     auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
     if (!N1C)
       break;
+    uint64_t C1 = N1C->getZExtValue();
+    const bool isC1Mask = isMask_64(C1);
+    const bool isC1ANDI = isInt<12>(C1);
 
     SDValue N0 = Node->getOperand(0);
 
+    auto tryUnsignedBitfieldExtract = [&](SDNode *Node, SDLoc DL, MVT VT,
+                                          SDValue X, unsigned Msb,
+                                          unsigned Lsb) {
+      if (!Subtarget->hasVendorXTHeadBb())
+        return false;
+
+      SDNode *TH_EXTU = CurDAG->getMachineNode(
+          RISCV::TH_EXTU, DL, VT, X, CurDAG->getTargetConstant(Msb, DL, VT),
+          CurDAG->getTargetConstant(Lsb, DL, VT));
+      ReplaceNode(Node, TH_EXTU);
+      return true;
+    };
+
     bool LeftShift = N0.getOpcode() == ISD::SHL;
     if (LeftShift || N0.getOpcode() == ISD::SRL) {
       auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
       if (!C)
         break;
       unsigned C2 = C->getZExtValue();
       unsigned XLen = Subtarget->getXLen();
       assert((C2 > 0 && C2 < XLen) && "Unexpected shift amount!");
 
-      uint64_t C1 = N1C->getZExtValue();
-
       // Keep track of whether this is a c.andi. If we can't use c.andi, the
       // shift pair might offer more compression opportunities.
       // TODO: We could check for C extension here, but we don't have many lit
       // tests with the C extension enabled so not checking gets better
       // coverage.
       // TODO: What if ANDI faster than shift?
       bool IsCANDI = isInt<6>(N1C->getSExtValue());
 
       // Clear irrelevant bits in the mask.
       if (LeftShift)
         C1 &= maskTrailingZeros<uint64_t>(C2);
       else
         C1 &= maskTrailingOnes<uint64_t>(XLen - C2);
 
       // Some transforms should only be done if the shift has a single use or
       // the AND would become (srli (slli X, 32), 32)
       bool OneUseOrZExtW = N0.hasOneUse() || C1 == UINT64_C(0xFFFFFFFF);
 
       SDValue X = N0.getOperand(0);
 
       // Turn (and (srl x, c2) c1) -> (srli (slli x, c3-c2), c3) if c1 is a mask
       // with c3 leading zeros.
-      if (!LeftShift && isMask_64(C1)) {
+      if (!LeftShift && isC1Mask) {
         unsigned Leading = XLen - llvm::bit_width(C1);
         if (C2 < Leading) {
           // If the number of leading zeros is C2+32 this can be SRLIW.
           if (C2 + 32 == Leading) {
             SDNode *SRLIW = CurDAG->getMachineNode(
                 RISCV::SRLIW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT));
             ReplaceNode(Node, SRLIW);
             return;
           }
 
           // (and (srl (sexti32 Y), c2), c1) -> (srliw (sraiw Y, 31), c3 - 32)
           // if c1 is a mask with c3 leading zeros and c2 >= 32 and c3-c2==1.
           //
           // This pattern occurs when (i32 (srl (sra 31), c3 - 32)) is type
           // legalized and goes through DAG combine.
           if (C2 >= 32 && (Leading - C2) == 1 && N0.hasOneUse() &&
               X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
               cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) {
             SDNode *SRAIW =
                 CurDAG->getMachineNode(RISCV::SRAIW, DL, VT, X.getOperand(0),
                                        CurDAG->getTargetConstant(31, DL, VT));
             SDNode *SRLIW = CurDAG->getMachineNode(
                 RISCV::SRLIW, DL, VT, SDValue(SRAIW, 0),
                 CurDAG->getTargetConstant(Leading - 32, DL, VT));
             ReplaceNode(Node, SRLIW);
             return;
           }
 
+          // Try to use an unsigned bitfield extract (e.g., th.extu) if
+          // available.
+          // Transform (and (srl x, C2), C1)
+          //        -> (<bfextract> x, msb, lsb)
+          //
+          // Make sure to keep this below the SRLIW cases, as we always want to
+          // prefer the more common instruction.
+          const unsigned Msb = llvm::bit_width(C1) + C2 - 1;
+          const unsigned Lsb = C2;
+          if (tryUnsignedBitfieldExtract(Node, DL, VT, X, Msb, Lsb))
+            return;
+
           // (srli (slli x, c3-c2), c3).
           // Skip if we could use (zext.w (sraiw X, C2)).
           bool Skip = Subtarget->hasStdExtZba() && Leading == 32 &&
                       X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
                       cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32;
           // Also Skip if we can use bexti or th.tst.
           Skip |= HasBitTest && Leading == XLen - 1;
           if (OneUseOrZExtW && !Skip) {
if (LeftShift || N0.getOpcode() == ISD::SRL) {
               RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),
               CurDAG->getTargetConstant(Trailing, DL, VT));
           ReplaceNode(Node, SLLI);
           return;
         }
       }
     }
 
+    // If C1 masks off the upper bits only (but can't be formed as an
+    // ANDI), use an unsigned bitfield extract (e.g., th.extu), if
+    // available.
+    // Transform (and x, C1)
+    //        -> (<bfextract> x, msb, lsb)
+    if (isC1Mask && !isC1ANDI) {
+      const unsigned Msb = llvm::bit_width(C1) - 1;
+      if (tryUnsignedBitfieldExtract(Node, DL, VT, N0, Msb, 0))
+        return;
+    }
+
     if (tryShrinkShlLogicImm(Node))
       return;
 
     break;
   }
   case ISD::MUL: {
     // Special case for calculating (mul (and X, C2), C1) where the full product
     // fits in XLen bits. We can shift X left by the number of leading zeros in

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

 def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
           (TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
 def : Pat<(rotr GPR:$rs1, GPR:$rs2),
            (OR (SRL GPR:$rs1, GPR:$rs2),
                (SLL GPR:$rs1, (SUB X0, GPR:$rs2)))>;
 def : Pat<(rotl GPR:$rs1, GPR:$rs2),
            (OR (SLL GPR:$rs1, GPR:$rs2),
                (SRL GPR:$rs1, (SUB X0, GPR:$rs2)))>;
-//def : Pat<(and GPR:$rs1, 1), (TH_EXTU GPR:$rs1, 0, 0)>;
-//def : Pat<(and GPR:$rs1, 0xff), (TH_EXTU GPR:$rs1, 7, 0)>;
-def : Pat<(and GPR:$rs1, 0xffff), (TH_EXTU GPR:$rs1, 15, 0)>;
-def : Pat<(and GPR:$rs1, 0xffffffff), (TH_EXTU GPR:$rs1, 31, 0)>;
 def : Pat<(sext_inreg GPR:$rs1, i32), (TH_EXT GPR:$rs1, 31, 0)>;
 def : Pat<(sext_inreg GPR:$rs1, i16), (TH_EXT GPR:$rs1, 15, 0)>;
 def : Pat<(sext_inreg GPR:$rs1, i8), (TH_EXT GPR:$rs1, 7, 0)>;
 def : Pat<(sext_inreg GPR:$rs1, i1), (TH_EXT GPR:$rs1, 0, 0)>;
 def : PatGpr<ctlz, TH_FF1>;
 def : Pat<(ctlz (xor GPR:$rs1, -1)), (TH_FF0 GPR:$rs1)>;
 def : PatGpr<bswap, TH_REV>;
 } // Predicates = [HasVendorXTHeadBb]

llvm/test/CodeGen/RISCV/bitextract-mac.ll

 ; RV32ZBB-NEXT:    srli a0, a0, 25
 ; RV32ZBB-NEXT:    mul a0, a1, a0
 ; RV32ZBB-NEXT:    add a0, a0, a2
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: f:
 ; RV32XTHEADBB:       # %bb.0: # %entry
 ; RV32XTHEADBB-NEXT:    mul a0, a1, a0
-; RV32XTHEADBB-NEXT:    slli a1, a0, 26
-; RV32XTHEADBB-NEXT:    srli a1, a1, 28
-; RV32XTHEADBB-NEXT:    slli a0, a0, 20
-; RV32XTHEADBB-NEXT:    srli a0, a0, 25
+; RV32XTHEADBB-NEXT:    th.extu a1, a0, 5, 2
+; RV32XTHEADBB-NEXT:    th.extu a0, a0, 11, 5
 ; RV32XTHEADBB-NEXT:    mul a0, a1, a0
 ; RV32XTHEADBB-NEXT:    add a0, a0, a2
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV32XTHEADMAC-LABEL: f:
 ; RV32XTHEADMAC:       # %bb.0: # %entry
 ; RV32XTHEADMAC-NEXT:    mul a0, a1, a0
 ; RV32XTHEADMAC-NEXT:    slli a1, a0, 26
 ; RV32XTHEADMAC-NEXT:    srli a1, a1, 28
 ; RV32XTHEADMAC-NEXT:    slli a0, a0, 20
 ; RV32XTHEADMAC-NEXT:    srli a0, a0, 25
 ; RV32XTHEADMAC-NEXT:    th.mulah a2, a1, a0
 ; RV32XTHEADMAC-NEXT:    mv a0, a2
 ; RV32XTHEADMAC-NEXT:    ret
 ;
 ; RV32XTHEAD-LABEL: f:
 ; RV32XTHEAD:       # %bb.0: # %entry
 ; RV32XTHEAD-NEXT:    mul a0, a1, a0
-; RV32XTHEAD-NEXT:    slli a1, a0, 26
-; RV32XTHEAD-NEXT:    srli a1, a1, 28
-; RV32XTHEAD-NEXT:    slli a0, a0, 20
-; RV32XTHEAD-NEXT:    srli a0, a0, 25
+; RV32XTHEAD-NEXT:    th.extu a1, a0, 5, 2
+; RV32XTHEAD-NEXT:    th.extu a0, a0, 11, 5
 ; RV32XTHEAD-NEXT:    th.mulah a2, a1, a0
 ; RV32XTHEAD-NEXT:    mv a0, a2
 ; RV32XTHEAD-NEXT:    ret
 ;
 ; RV64I-LABEL: f:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    mulw a0, a1, a0
 ; RV64I-NEXT:    slli a1, a0, 58

 ; RV64XTHEADMAC-NEXT:    slli a0, a0, 52
 ; RV64XTHEADMAC-NEXT:    srli a0, a0, 57
 ; RV64XTHEADMAC-NEXT:    th.mulah a2, a1, a0
 ; RV64XTHEADMAC-NEXT:    mv a0, a2
 ; RV64XTHEADMAC-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: f:
 ; RV64XTHEADBB:       # %bb.0: # %entry
-; RV64XTHEADBB-NEXT:    mulw a0, a1, a0
-; RV64XTHEADBB-NEXT:    slli a1, a0, 58
-; RV64XTHEADBB-NEXT:    srli a1, a1, 60
-; RV64XTHEADBB-NEXT:    slli a0, a0, 52
-; RV64XTHEADBB-NEXT:    srli a0, a0, 57
+; RV64XTHEADBB-NEXT:    mul a0, a1, a0
+; RV64XTHEADBB-NEXT:    th.extu a1, a0, 5, 2
+; RV64XTHEADBB-NEXT:    th.extu a0, a0, 11, 5
 ; RV64XTHEADBB-NEXT:    mulw a0, a1, a0
 ; RV64XTHEADBB-NEXT:    addw a0, a0, a2
 ; RV64XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEAD-LABEL: f:
 ; RV64XTHEAD:       # %bb.0: # %entry
-; RV64XTHEAD-NEXT:    mulw a0, a1, a0
-; RV64XTHEAD-NEXT:    slli a1, a0, 58
-; RV64XTHEAD-NEXT:    srli a1, a1, 60
-; RV64XTHEAD-NEXT:    slli a0, a0, 52
-; RV64XTHEAD-NEXT:    srli a0, a0, 57
+; RV64XTHEAD-NEXT:    mul a0, a1, a0
+; RV64XTHEAD-NEXT:    th.extu a1, a0, 5, 2
+; RV64XTHEAD-NEXT:    th.extu a0, a0, 11, 5
 ; RV64XTHEAD-NEXT:    th.mulah a2, a1, a0
 ; RV64XTHEAD-NEXT:    mv a0, a2
 ; RV64XTHEAD-NEXT:    ret
 entry:
   %mul = mul nsw i32 %B, %A
   %0 = lshr i32 %mul, 2
   %and = and i32 %0, 15
   %1 = lshr i32 %mul, 5
   %and2 = and i32 %1, 127
   %mul3 = mul nuw nsw i32 %and, %and2
   %add = add i32 %mul3, %C
   ret i32 %add
 }

llvm/test/CodeGen/RISCV/rotl-rotr.ll

 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a2
 ; RV64ZBB-NEXT:    sll a1, a1, a2
 ; RV64ZBB-NEXT:    add a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64_mask_shared:
 ; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    slli a5, a4, 26
-; RV32XTHEADBB-NEXT:    srli a5, a5, 31
+; RV32XTHEADBB-NEXT:    th.extu a5, a4, 5, 5
 ; RV32XTHEADBB-NEXT:    mv a7, a0
 ; RV32XTHEADBB-NEXT:    bnez a5, .LBB17_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a7, a1
 ; RV32XTHEADBB-NEXT:  .LBB17_2:
 ; RV32XTHEADBB-NEXT:    andi a6, a4, 63
 ; RV32XTHEADBB-NEXT:    sll t0, a7, a4
 ; RV32XTHEADBB-NEXT:    bnez a5, .LBB17_4

 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a2
 ; RV64ZBB-NEXT:    rol a1, a1, a2
 ; RV64ZBB-NEXT:    add a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64_mask_multiple:
 ; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    slli a5, a4, 26
-; RV32XTHEADBB-NEXT:    srli a5, a5, 31
+; RV32XTHEADBB-NEXT:    th.extu a5, a4, 5, 5
 ; RV32XTHEADBB-NEXT:    mv a6, a1
 ; RV32XTHEADBB-NEXT:    bnez a5, .LBB21_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a6, a0
 ; RV32XTHEADBB-NEXT:  .LBB21_2:
 ; RV32XTHEADBB-NEXT:    bnez a5, .LBB21_4
 ; RV32XTHEADBB-NEXT:  # %bb.3:
 ; RV32XTHEADBB-NEXT:    mv a0, a1

llvm/test/CodeGen/RISCV/rv32xtheadbb.ll

 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    th.ext a0, a0, 15, 0
 ; RV32XTHEADBB-NEXT:    ret
   %shl = shl i32 %a, 16
   %shr = ashr exact i32 %shl, 16
   ret i32 %shr
 }
 
+define i32 @no_sexth_i32(i32 %a) nounwind {
+; RV32I-LABEL: no_sexth_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 17
+; RV32I-NEXT:    srai a0, a0, 16
+; RV32I-NEXT:    ret
+;
+; RV32XTHEADBB-LABEL: no_sexth_i32:
+; RV32XTHEADBB:       # %bb.0:
+; RV32XTHEADBB-NEXT:    slli a0, a0, 17
+; RV32XTHEADBB-NEXT:    srai a0, a0, 16
+; RV32XTHEADBB-NEXT:    ret
+  %shl = shl i32 %a, 17
+  %shr = ashr exact i32 %shl, 16
+  ret i32 %shr
+}
+
 define i64 @sexth_i64(i64 %a) nounwind {
 ; RV32I-LABEL: sexth_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 16
 ; RV32I-NEXT:    srai a0, a1, 16
 ; RV32I-NEXT:    srai a1, a1, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: sexth_i64:
 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    th.ext a0, a0, 15, 0
 ; RV32XTHEADBB-NEXT:    srai a1, a0, 31
 ; RV32XTHEADBB-NEXT:    ret
   %shl = shl i64 %a, 48
   %shr = ashr exact i64 %shl, 48
   ret i64 %shr
 }
 
+define i64 @no_sexth_i64(i64 %a) nounwind {
+; RV32I-LABEL: no_sexth_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a1, a0, 17
+; RV32I-NEXT:    srai a0, a1, 16
+; RV32I-NEXT:    srai a1, a1, 31
+; RV32I-NEXT:    ret
+;
+; RV32XTHEADBB-LABEL: no_sexth_i64:
+; RV32XTHEADBB:       # %bb.0:
+; RV32XTHEADBB-NEXT:    slli a1, a0, 17
+; RV32XTHEADBB-NEXT:    srai a0, a1, 16
+; RV32XTHEADBB-NEXT:    srai a1, a1, 31
+; RV32XTHEADBB-NEXT:    ret
+  %shl = shl i64 %a, 49
+  %shr = ashr exact i64 %shl, 48
+  ret i64 %shr
+}
+
 define i32 @zexth_i32(i32 %a) nounwind {
 ; RV32I-LABEL: zexth_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: zexth_i32:
 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    th.extu a0, a0, 15, 0
 ; RV32XTHEADBB-NEXT:    ret
   %and = and i32 %a, 65535
   ret i32 %and
 }
 
 define i64 @zexth_i64(i64 %a) nounwind {
 ; RV32I-LABEL: zexth_i64:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64xtheadbb.ll

 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    th.ext a0, a0, 15, 0
 ; RV64XTHEADBB-NEXT:    ret
   %shl = shl i32 %a, 16
   %shr = ashr exact i32 %shl, 16
   ret i32 %shr
 }
 
+define signext i32 @no_sexth_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: no_sexth_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 49
+; RV64I-NEXT:    srai a0, a0, 48
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBB-LABEL: no_sexth_i32:
+; RV64XTHEADBB:       # %bb.0:
+; RV64XTHEADBB-NEXT:    slli a0, a0, 49
+; RV64XTHEADBB-NEXT:    srai a0, a0, 48
+; RV64XTHEADBB-NEXT:    ret
+  %shl = shl i32 %a, 17
+  %shr = ashr exact i32 %shl, 16
+  ret i32 %shr
+}
+
 define i64 @sexth_i64(i64 %a) nounwind {
 ; RV64I-LABEL: sexth_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: sexth_i64:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    th.ext a0, a0, 15, 0
 ; RV64XTHEADBB-NEXT:    ret
   %shl = shl i64 %a, 48
   %shr = ashr exact i64 %shl, 48
   ret i64 %shr
 }
 
+define i64 @no_sexth_i64(i64 %a) nounwind {
+; RV64I-LABEL: no_sexth_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 49
+; RV64I-NEXT:    srai a0, a0, 48
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBB-LABEL: no_sexth_i64:
+; RV64XTHEADBB:       # %bb.0:
+; RV64XTHEADBB-NEXT:    slli a0, a0, 49
+; RV64XTHEADBB-NEXT:    srai a0, a0, 48
+; RV64XTHEADBB-NEXT:    ret
+  %shl = shl i64 %a, 49
+  %shr = ashr exact i64 %shl, 48
+  ret i64 %shr
+}
+
 define i32 @zexth_i32(i32 %a) nounwind {
 ; RV64I-LABEL: zexth_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: zexth_i32:

 ; RV64XTHEADBB-LABEL: zexth_i64:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    th.extu a0, a0, 15, 0
 ; RV64XTHEADBB-NEXT:    ret
   %and = and i64 %a, 65535
   ret i64 %and
 }
 
+define i64 @zext_bf_i64(i64 %a) nounwind {
+; RV64I-LABEL: zext_bf_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 47
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBB-LABEL: zext_bf_i64:
+; RV64XTHEADBB:       # %bb.0:
+; RV64XTHEADBB-NEXT:    th.extu a0, a0, 16, 1
+; RV64XTHEADBB-NEXT:    ret
+  %1 = lshr i64 %a, 1
+  %and = and i64 %1, 65535
+  ret i64 %and
+}
+
+define i64 @zext_i64_srliw(i64 %a) nounwind {
+; RV64I-LABEL: zext_i64_srliw:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srliw a0, a0, 16
+; RV64I-NEXT:    ret
+;
+; RV64XTHEADBB-LABEL: zext_i64_srliw:
+; RV64XTHEADBB:       # %bb.0:
+; RV64XTHEADBB-NEXT:    srliw a0, a0, 16
+; RV64XTHEADBB-NEXT:    ret
+  %1 = lshr i64 %a, 16
+  %and = and i64 %1, 65535
+  ret i64 %and
+}
+
 declare i32 @llvm.bswap.i32(i32)
 
 define signext i32 @bswap_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: bswap_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a0, 8
 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256