[AMDGPU] Use buildCopy and isCopy helper functions (NFC).

[arsenm]

Is this still needed?

[cdevadas]

No. A couple more patches need to be abandoned. Will abandon once the final set of SGPR spill patches is upstreamed.

[cdevadas]

No longer needed after D150388.

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
 
   MachineInstr *MI = MO.getParent();
   MachineBasicBlock *BB = MO.getParent()->getParent();
   Register DstReg = MRI->createVirtualRegister(&SubRC);
 
   if (MO.isReg()) {
     unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
     Register Reg = MO.getReg();
-    BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
-            .addReg(Reg, 0, ComposedSubIdx);
+    TII.buildCopy(*BB, MI, MI->getDebugLoc(), DstReg, Reg, 0, ComposedSubIdx);
 
     return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
                                      MO.isKill(), MO.isDead(), MO.isUndef(),
                                      MO.isEarlyClobber(), 0, MO.isDebug(),
                                      MO.isInternalRead());
   }
 
   assert(MO.isImm());
if (isVCC(Dst1Reg, *MRI)) {
     I.addOperand(*MF, MachineOperand::CreateImm(0));
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
   Register Src0Reg = I.getOperand(2).getReg();
   Register Src1Reg = I.getOperand(3).getReg();
 
   if (HasCarryIn) {
-    BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
-      .addReg(I.getOperand(4).getReg());
+    TII.buildCopy(*BB, &I, DL, AMDGPU::SCC, I.getOperand(4).getReg());
   }
 
   unsigned NoCarryOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
   unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
 
   BuildMI(*BB, &I, DL, TII.get(HasCarryIn ? CarryOpc : NoCarryOpc), Dst0Reg)
     .add(I.getOperand(2))
     .add(I.getOperand(3));
-  BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), Dst1Reg)
-    .addReg(AMDGPU::SCC);
+  TII.buildCopy(*BB, &I, DL, Dst1Reg, AMDGPU::SCC);
 
   if (!MRI->getRegClassOrNull(Dst1Reg))
     MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass);
 
   if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) ||
       !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) ||
       !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI))
     return false;
unsigned SubReg = SIRegisterInfo::getSubRegFromChannel(Offset / 32,
                                                          DstSize / 32);
   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg);
   if (!SrcRC)
     return false;
 
   SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I,
                                     *SrcRC, I.getOperand(1));
   const DebugLoc &DL = I.getDebugLoc();
-  BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY), DstReg)
-    .addReg(SrcReg, 0, SubReg);
+  TII.buildCopy(*BB, &I, DL, DstReg, SrcReg, 0, SubReg);
 
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectG_FMA_FMAD(MachineInstr &I) const {
   assert(I.getOpcode() == AMDGPU::G_FMA || I.getOpcode() == AMDGPU::G_FMAD);
 
if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
     return false;
 
   // Note we could have mixed SGPR and VGPR destination banks for an SGPR
   // source, and this relies on the fact that the same subregister indices are
   // used for both.
   ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
   for (int I = 0, E = NumDst; I != E; ++I) {
     MachineOperand &Dst = MI.getOperand(I);
-    BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
-      .addReg(SrcReg, 0, SubRegs[I]);
+    TII.buildCopy(*BB, &MI, DL, Dst.getReg(), SrcReg, 0, SubRegs[I]);
 
     // Make sure the subregister index is valid for the source register.
     SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
     if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
       return false;
 
     const TargetRegisterClass *DstRC =
       TRI.getConstrainedRegClassForOperand(Dst, *MRI);
bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) const {
   // is incorrectly placed before the second instruction.
   //
   // TODO: Match source modifiers.
 
   Register InterpMov = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
   const DebugLoc &DL = MI.getDebugLoc();
   MachineBasicBlock *MBB = MI.getParent();
 
-  BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-    .addReg(M0Val);
+  TII.buildCopy(*MBB, &MI, DL, AMDGPU::M0, M0Val);
   BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_INTERP_MOV_F32), InterpMov)
     .addImm(2)
     .addImm(MI.getOperand(4).getImm())  // $attr
     .addImm(MI.getOperand(3).getImm()); // $attrchan
 
   BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_INTERP_P1LV_F16), Dst)
     .addImm(0)                          // $src0_modifiers
     .addReg(Src0)                       // $src0
if (ConstSelect) {
     } else {
       MIB.addReg(Val);
 
       // If the lane selector was originally in a VGPR and copied with
       // readfirstlane, there's a hazard to read the same SGPR from the
       // VALU. Constrain to a different SGPR to help avoid needing a nop later.
       RBI.constrainGenericRegister(LaneSelect, AMDGPU::SReg_32_XM0RegClass, *MRI);
 
-      BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-        .addReg(LaneSelect);
+      TII.buildCopy(*MBB, *MIB, DL, AMDGPU::M0, LaneSelect);
       MIB.addReg(AMDGPU::M0);
     }
   }
 
   MIB.addReg(VDstIn);
 
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const {
   Register CCReg = I.getOperand(0).getReg();
   if (!isVCC(CCReg, *MRI)) {
     int Opcode = getS_CMPOpcode(Pred, Size);
     if (Opcode == -1)
       return false;
     MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
             .add(I.getOperand(2))
             .add(I.getOperand(3));
-    BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
-      .addReg(AMDGPU::SCC);
+    TII.buildCopy(*BB, &I, DL, CCReg, AMDGPU::SCC);
     bool Ret =
         constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) &&
         RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
     I.eraseFromParent();
     return Ret;
   }
 
   int Opcode = getV_CMPOpcode(Pred, Size, *Subtarget);
bool AMDGPUInstructionSelector::selectBallot(MachineInstr &I) const {
 
   if (Arg) {
     const int64_t Value = Arg->Value.getSExtValue();
     if (Value == 0) {
       unsigned Opcode = Is64 ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
       BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg).addImm(0);
     } else if (Value == -1) { // all ones
       Register SrcReg = Is64 ? AMDGPU::EXEC : AMDGPU::EXEC_LO;
-      BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg);
+      TII.buildCopy(*BB, &I, DL, DstReg, SrcReg);
     } else
       return false;
   } else {
     Register SrcReg = I.getOperand(2).getReg();
-    BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg);
+    TII.buildCopy(*BB, &I, DL, DstReg, SrcReg);
   }
 
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectRelocConstant(MachineInstr &I) const {
   Register DstReg = I.getOperand(0).getReg();
bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
   // There is a call to @llvm.returnaddress in this function
   MFI.setReturnAddressIsTaken(true);
 
   // Get the return address reg and mark it as an implicit live-in
   Register ReturnAddrReg = TRI.getReturnAddressReg(MF);
   Register LiveIn = getFunctionLiveInPhysReg(MF, TII, ReturnAddrReg,
                                              AMDGPU::SReg_64RegClass, DL);
-  BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
-    .addReg(LiveIn);
+  TII.buildCopy(*MBB, &I, DL, DstReg, LiveIn);
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
   // FIXME: Manually selecting to avoid dealing with the SReg_1 trick
   // SelectionDAG uses for wave32 vs wave64.
   MachineBasicBlock *BB = MI.getParent();
if (STI.getGeneration() >= AMDGPUSubtarget::GFX10)
     Offset1 |= (CountDw - 1) << 6;
 
   if (STI.getGeneration() < AMDGPUSubtarget::GFX11)
     Offset1 |= ShaderType << 2;
 
   unsigned Offset = Offset0 | (Offset1 << 8);
 
   Register M0Val = MI.getOperand(2).getReg();
-  BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-    .addReg(M0Val);
+  TII.buildCopy(*MBB, &MI, DL, AMDGPU::M0, M0Val);
 
   Register DstReg = MI.getOperand(0).getReg();
   Register ValReg = MI.getOperand(3).getReg();
   MachineInstrBuilder DS =
     BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_ORDERED_COUNT), DstReg)
       .addReg(ValReg)
       .addImm(Offset)
       .cloneMemRefs(MI);
if (Readfirstlane) {
         return false;
     }
 
     Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
     BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_LSHL_B32), M0Base)
       .addReg(BaseOffset)
       .addImm(16);
 
-    BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-      .addReg(M0Base);
+    TII.buildCopy(*MBB, &MI, DL, AMDGPU::M0, M0Base);
   }
 
   // The resource id offset is computed as (<isa opaque base> + M0[21:16] +
   // offset field) % 64. Some versions of the programming guide omit the m0
   // part, or claim it's from offset 0.
   auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID)));
 
   if (HasVSrc) {
if (!isDSOffsetLegal(PtrBase, Offset)) {
     PtrBase = MI.getOperand(2).getReg();
     Offset = 0;
   }
 
   MachineBasicBlock *MBB = MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
   const unsigned Opc = IsAppend ? AMDGPU::DS_APPEND : AMDGPU::DS_CONSUME;
 
-  BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-    .addReg(PtrBase);
+  TII.buildCopy(*MBB, &MI, DL, AMDGPU::M0, PtrBase);
   if (!RBI.constrainGenericRegister(PtrBase, AMDGPU::SReg_32RegClass, *MRI))
     return false;
 
   auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg())
     .addImm(Offset)
     .addImm(IsGDS ? -1 : 0)
     .cloneMemRefs(MI);
   MI.eraseFromParent();
if (BaseOpcode->AtomicX2) {
       const bool Is64 = MRI->getType(VDataOut).getSizeInBits() == 64;
 
       Register TmpReg = MRI->createVirtualRegister(
         Is64 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass);
       unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;
 
       MIB.addDef(TmpReg);
       if (!MRI->use_empty(VDataOut)) {
-        BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), VDataOut)
-            .addReg(TmpReg, RegState::Kill, SubReg);
+        TII.buildCopy(*MBB, &MI, DL, VDataOut, TmpReg, RegState::Kill, SubReg);
       }
 
     } else {
       MIB.addDef(VDataOut); // vdata output
     }
   }
 
   if (VDataIn)
bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
   Register DstReg = I.getOperand(0).getReg();
   unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
   assert(Size <= 32 || Size == 64);
   const MachineOperand &CCOp = I.getOperand(1);
   Register CCReg = CCOp.getReg();
   if (!isVCC(CCReg, *MRI)) {
     unsigned SelectOpcode = Size == 64 ? AMDGPU::S_CSELECT_B64 :
                                          AMDGPU::S_CSELECT_B32;
-    MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
-            .addReg(CCReg);
+    MachineInstr *CopySCC = TII.buildCopy(*BB, &I, DL, AMDGPU::SCC, CCReg);
 
     // The generic constrainSelectedInstRegOperands doesn't work for the scc register
     // bank, because it does not cover the register class that we used to represent
     // for it.  So we need to manually set the register class here.
     if (!MRI->getRegClassOrNull(CCReg))
         MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
     MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
             .add(I.getOperand(2))
bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
   }
 
   if (DstTy == LLT::fixed_vector(2, 16) && SrcTy == LLT::fixed_vector(2, 32)) {
     MachineBasicBlock *MBB = I.getParent();
     const DebugLoc &DL = I.getDebugLoc();
 
     Register LoReg = MRI->createVirtualRegister(DstRC);
     Register HiReg = MRI->createVirtualRegister(DstRC);
-    BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), LoReg)
-      .addReg(SrcReg, 0, AMDGPU::sub0);
-    BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg)
-      .addReg(SrcReg, 0, AMDGPU::sub1);
+    TII.buildCopy(*MBB, I, DL, LoReg, SrcReg, 0, AMDGPU::sub0);
+    TII.buildCopy(*MBB, I, DL, HiReg, SrcReg, 0, AMDGPU::sub1);
 
     if (IsVALU && STI.hasSDWA()) {
       // Write the low 16-bits of the high element into the high 16-bits of the
       // low element.
       MachineInstr *MovSDWA =
         BuildMI(*MBB, I, DL, TII.get(AMDGPU::V_MOV_B32_sdwa), DstReg)
         .addImm(0)                             // $src0_modifiers
         .addReg(HiReg)                         // $src0
bool AMDGPUInstructionSelector::selectG_FNEG(MachineInstr &MI) const {
 
   MachineBasicBlock *BB = MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
   Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
 
-  BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg)
-    .addReg(Src, 0, AMDGPU::sub0);
-  BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg)
-    .addReg(Src, 0, AMDGPU::sub1);
+  TII.buildCopy(*BB, &MI, DL, LoReg, Src, 0, AMDGPU::sub0);
+  TII.buildCopy(*BB, &MI, DL, HiReg, Src, 0, AMDGPU::sub1);
   BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), ConstReg)
     .addImm(0x80000000);
 
   // Set or toggle sign bit.
   unsigned Opc = Fabs ? AMDGPU::S_OR_B32 : AMDGPU::S_XOR_B32;
   BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg)
     .addReg(HiReg)
     .addReg(ConstReg);
bool AMDGPUInstructionSelector::selectG_FABS(MachineInstr &MI) const {
   Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register ConstReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
   Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
 
   if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) ||
       !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI))
     return false;
 
-  BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg)
-    .addReg(Src, 0, AMDGPU::sub0);
-  BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg)
-    .addReg(Src, 0, AMDGPU::sub1);
+  TII.buildCopy(*BB, &MI, DL, LoReg, Src, 0, AMDGPU::sub0);
+  TII.buildCopy(*BB, &MI, DL, HiReg, Src, 0, AMDGPU::sub1);
   BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), ConstReg)
     .addImm(0x7fffffff);
 
   // Clear sign bit.
   // TODO: Should this used S_BITSET0_*?
   BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg)
     .addReg(HiReg)
     .addReg(ConstReg);

 
 static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
   if (Reg.isPhysical())
     return false;
 
   MachineInstr &MI = *MRI.getUniqueVRegDef(Reg);
   const unsigned Opcode = MI.getOpcode();
 
-  if (Opcode == AMDGPU::COPY)
+  if (MI.isCopy())
     return isVCmpResult(MI.getOperand(1).getReg(), MRI);
 
   if (Opcode == AMDGPU::G_AND || Opcode == AMDGPU::G_OR ||
       Opcode == AMDGPU::G_XOR)
     return isVCmpResult(MI.getOperand(1).getReg(), MRI) &&
            isVCmpResult(MI.getOperand(2).getReg(), MRI);
 
   if (Opcode == TargetOpcode::G_INTRINSIC)
if (!isVCC(CondReg, *MRI)) {
     CondPhysReg = TRI.getVCC();
     BrOpcode = AMDGPU::S_CBRANCH_VCCNZ;
     ConstrainRC = TRI.getBoolRC();
   }
 
   if (!MRI->getRegClassOrNull(CondReg))
     MRI->setRegClass(CondReg, ConstrainRC);
 
-  BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CondPhysReg)
-    .addReg(CondReg);
+  TII.buildCopy(*BB, &I, DL, CondPhysReg, CondReg);
   BuildMI(*BB, &I, DL, TII.get(BrOpcode))
     .addMBB(I.getOperand(1).getMBB());
 
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectG_GLOBAL_VALUE(
if (Ty.getSizeInBits() == 32) {
     I.eraseFromParent();
     return true;
   }
 
   Register HiReg = MRI->createVirtualRegister(&RegRC);
   Register LoReg = MRI->createVirtualRegister(&RegRC);
 
   // Extract the subregisters from the source pointer.
-  BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
-    .addReg(SrcReg, 0, AMDGPU::sub0);
-  BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
-    .addReg(SrcReg, 0, AMDGPU::sub1);
+  TII.buildCopy(*BB, &I, DL, LoReg, SrcReg, 0, AMDGPU::sub0);
+  TII.buildCopy(*BB, &I, DL, HiReg, SrcReg, 0, AMDGPU::sub1);
 
   Register MaskedLo, MaskedHi;
 
   if (CanCopyLow32) {
     // If all the bits in the low half are 1, we only need a copy for it.
     MaskedLo = LoReg;
   } else {
     // Extract the mask subregister and apply the and.
     Register MaskLo = MRI->createVirtualRegister(&RegRC);
     MaskedLo = MRI->createVirtualRegister(&RegRC);
 
-    BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo)
-      .addReg(MaskReg, 0, AMDGPU::sub0);
+    TII.buildCopy(*BB, &I, DL, MaskLo, MaskReg, 0, AMDGPU::sub0);
     BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedLo)
       .addReg(LoReg)
       .addReg(MaskLo);
   }
 
   if (CanCopyHi32) {
     // If all the bits in the high half are 1, we only need a copy for it.
     MaskedHi = HiReg;
   } else {
     Register MaskHi = MRI->createVirtualRegister(&RegRC);
     MaskedHi = MRI->createVirtualRegister(&RegRC);
 
-    BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskHi)
-      .addReg(MaskReg, 0, AMDGPU::sub1);
+    TII.buildCopy(*BB, &I, DL, MaskHi, MaskReg, 0, AMDGPU::sub1);
     BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedHi)
       .addReg(HiReg)
       .addReg(MaskHi);
   }
 
   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
     .addReg(MaskedLo)
     .addImm(AMDGPU::sub0)
bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
   unsigned SubReg;
   std::tie(IdxReg, SubReg) = computeIndirectRegIndex(
       *MRI, TRI, SrcRC, IdxReg, DstTy.getSizeInBits() / 8, *KnownBits);
 
   if (SrcRB->getID() == AMDGPU::SGPRRegBankID) {
     if (DstTy.getSizeInBits() != 32 && !Is64)
       return false;
 
-    BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-      .addReg(IdxReg);
+    TII.buildCopy(*BB, &MI, DL, AMDGPU::M0, IdxReg);
 
     unsigned Opc = Is64 ? AMDGPU::S_MOVRELS_B64 : AMDGPU::S_MOVRELS_B32;
     BuildMI(*BB, &MI, DL, TII.get(Opc), DstReg)
       .addReg(SrcReg, 0, SubReg)
       .addReg(SrcReg, RegState::Implicit);
     MI.eraseFromParent();
     return true;
   }
 
   if (SrcRB->getID() != AMDGPU::VGPRRegBankID || DstTy.getSizeInBits() != 32)
     return false;
 
   if (!STI.useVGPRIndexMode()) {
-    BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-      .addReg(IdxReg);
+    TII.buildCopy(*BB, &MI, DL, AMDGPU::M0, IdxReg);
     BuildMI(*BB, &MI, DL, TII.get(AMDGPU::V_MOVRELS_B32_e32), DstReg)
       .addReg(SrcReg, 0, SubReg)
       .addReg(SrcReg, RegState::Implicit);
     MI.eraseFromParent();
     return true;
   }
 
   const MCInstrDesc &GPRIDXDesc =
bool AMDGPUInstructionSelector::selectG_INSERT_VECTOR_ELT(
 
   const bool IndexMode = VecRB->getID() == AMDGPU::VGPRRegBankID &&
                          STI.useVGPRIndexMode();
 
   MachineBasicBlock *BB = MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
 
   if (!IndexMode) {
-    BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
-      .addReg(IdxReg);
+    TII.buildCopy(*BB, &MI, DL, AMDGPU::M0, IdxReg);
 
     const MCInstrDesc &RegWriteOp = TII.getIndirectRegWriteMovRelPseudo(
         VecSize, ValSize, VecRB->getID() == AMDGPU::SGPRRegBankID);
     BuildMI(*BB, MI, DL, RegWriteOp, DstReg)
         .addReg(VecReg)
         .addReg(ValReg)
         .addImm(SubReg);
     MI.eraseFromParent();
Register AMDGPUInstructionSelector::copyToVGPRIfSrcFolded(
     bool ForceVGPR) const {
   if ((Mods != 0 || ForceVGPR) &&
       RBI.getRegBank(Src, *MRI, TRI)->getID() != AMDGPU::VGPRRegBankID) {
 
     // If we looked through copies to find source modifiers on an SGPR operand,
     // we now have an SGPR register source. To avoid potentially violating the
     // constant bus restriction, we need to insert a copy to a VGPR.
     Register VGPRSrc = MRI->cloneVirtualRegister(Root.getReg());
-    BuildMI(*InsertPt->getParent(), InsertPt, InsertPt->getDebugLoc(),
-            TII.get(AMDGPU::COPY), VGPRSrc)
-        .addReg(Src);
+    TII.buildCopy(*InsertPt->getParent(), InsertPt, InsertPt->getDebugLoc(),
+                  VGPRSrc, Src);
     Src = VGPRSrc;
   }
 
   return Src;
 }
 
 ///
 /// This will select either an SGPR or VGPR operand and will save us from

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

 
 Register AMDGPURegBankCombinerHelper::getAsVgpr(Register Reg) {
   if (isVgprRegBank(Reg))
     return Reg;
 
   // Search for existing copy of Reg to vgpr.
   for (MachineInstr &Use : MRI.use_instructions(Reg)) {
     Register Def = Use.getOperand(0).getReg();
-    if (Use.getOpcode() == AMDGPU::COPY && isVgprRegBank(Def))
+    if (Use.isCopy() && isVgprRegBank(Def))
       return Def;
   }
 
   // Copy Reg to vgpr.
   Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0);
   MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID));
   return VgprReg;
 }

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

case AMDGPU::G_SI_CALL: {
     MachineBasicBlock::iterator Start(&MI);
     MachineBasicBlock::iterator LastCopy = Start;
     MachineBasicBlock *MBB = MI.getParent();
     const SIMachineFunctionInfo *Info =
         MBB->getParent()->getInfo<SIMachineFunctionInfo>();
     while (Start->getOpcode() != FrameSetupOpcode) {
       --Start;
       bool IsCopy = false;
-      if (Start->getOpcode() == AMDGPU::COPY) {
+      if (Start->isCopy()) {
         auto &Dst = Start->getOperand(0);
         if (Dst.isReg()) {
           Register Reg = Dst.getReg();
           if (Reg.isPhysical() && MI.readsRegister(Reg, TRI)) {
             IsCopy = true;
           } else {
             // Also move the copy from the scratch rsrc descriptor into the loop
             // to allow it to be optimized away.
case AMDGPU::G_SI_CALL: {
     // Do the same for copies after the loop
     NonCopyInstrs.clear();
     NonCopyInstrsLen = 0;
     MachineBasicBlock::iterator End(&MI);
     LastCopy = End;
     while (End->getOpcode() != FrameDestroyOpcode) {
       ++End;
       bool IsCopy = false;
-      if (End->getOpcode() == AMDGPU::COPY) {
+      if (End->isCopy()) {
         auto &Src = End->getOperand(1);
         if (Src.isReg()) {
           Register Reg = Src.getReg();
           IsCopy = Reg.isPhysical() && MI.modifiesRegister(Reg, TRI);
         }
       }
 
       if (IsCopy) {

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI,
   return true;
 }
 
 static bool isSafeToFoldImmIntoCopy(const MachineInstr *Copy,
                                     const MachineInstr *MoveImm,
                                     const SIInstrInfo *TII,
                                     unsigned &SMovOp,
                                     int64_t &Imm) {
-  if (Copy->getOpcode() != AMDGPU::COPY)
+  if (!Copy->isCopy())
     return false;
 
   if (!MoveImm->isMoveImmediate())
     return false;
 
   const MachineOperand *ImmOp =
       TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0);
   if (!ImmOp->isImm())
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
               const TargetRegisterClass *DestRC =
                   TRI->getEquivalentSGPRClass(SrcRC);
               Register NewDst = MRI->createVirtualRegister(DestRC);
               MachineBasicBlock *BlockToInsertCopy =
                   MI.isPHI() ? MI.getOperand(MO.getOperandNo() + 1).getMBB()
                              : MBB;
               MachineBasicBlock::iterator PointToInsertCopy =
                   MI.isPHI() ? BlockToInsertCopy->getFirstInstrTerminator() : I;
-              MachineInstr *NewCopy =
-                  BuildMI(*BlockToInsertCopy, PointToInsertCopy,
-                          PointToInsertCopy->getDebugLoc(),
-                          TII->get(AMDGPU::COPY), NewDst)
-                      .addReg(MO.getReg());
+              MachineInstr *NewCopy = TII->buildCopy(
+                  *BlockToInsertCopy, PointToInsertCopy,
+                  PointToInsertCopy->getDebugLoc(), NewDst, MO.getReg());
               MO.setReg(NewDst);
               analyzeVGPRToSGPRCopy(NewCopy);
             }
           }
         }
 
         if (MI.isPHI())
           PHINodes.push_back(&MI);
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
             TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
         I = BuildMI(*MI.getParent(), std::next(MachineBasicBlock::iterator(MI)),
                     MI.getDebugLoc(),
                     TII->get(IsWave32 ? AMDGPU::S_CSELECT_B32
                                       : AMDGPU::S_CSELECT_B64),
                     SCCCopy)
                 .addImm(-1)
                 .addImm(0);
-        I = BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
-                    TII->get(AMDGPU::COPY), DstReg)
-                .addReg(SCCCopy);
+        I = TII->buildCopy(*MI.getParent(), std::next(I), I->getDebugLoc(),
+                           DstReg, SCCCopy);
         MI.eraseFromParent();
         continue;
       }
       if (DstReg == AMDGPU::SCC) {
         unsigned Opcode = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
         Register Exec = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
         Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC());
         I = BuildMI(*MI.getParent(), std::next(MachineBasicBlock::iterator(MI)),

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) {
     bool HaveNonDbgCarryUse = !MRI->use_nodbg_empty(Dst1.getReg());
 
     const TargetRegisterClass *Dst0RC = MRI->getRegClass(Dst0.getReg());
     Register NewReg0 = MRI->createVirtualRegister(Dst0RC);
 
     MachineInstr *Inst32 = TII->buildShrunkInst(*MI, Op32);
 
     if (HaveNonDbgCarryUse) {
-      BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::COPY),
-              Dst1.getReg())
-        .addReg(AMDGPU::VCC, RegState::Kill);
+      TII->buildCopy(*MBB, MI, MI->getDebugLoc(), Dst1.getReg(), AMDGPU::VCC,
+                     RegState::Kill);
     }
 
     // Keep the old instruction around to avoid breaking iterators, but
     // replace it with a dummy instruction to remove uses.
     //
     // FIXME: We should not invert how this pass looks at operands to avoid
     // this. Should track set of foldable movs instead of looking for uses
     // when looking at a use.
if (!TRI->isAGPR(*MRI, CopyIn) || Copy->getOperand(1).getSubReg())
     return false;
 
   const TargetRegisterClass *ARC = MRI->getRegClass(CopyIn);
   Register NewReg = MRI->createVirtualRegister(ARC);
   PHI.getOperand(1).setReg(CopyIn);
   PHI.getOperand(0).setReg(NewReg);
 
   MachineBasicBlock *MBB = PHI.getParent();
-  BuildMI(*MBB, MBB->getFirstNonPHI(), Copy->getDebugLoc(),
-          TII->get(AMDGPU::COPY), PhiOut)
-    .addReg(NewReg, RegState::Kill);
+  TII->buildCopy(*MBB, MBB->getFirstNonPHI(), Copy->getDebugLoc(), PhiOut,
+                 NewReg, RegState::Kill);
   Copy->eraseFromParent(); // We know this copy had a single use.
 
   LLVM_DEBUG(dbgs() << "Folded " << PHI);
 
   return true;
 }
 
 // Attempt to convert VGPR load to an AGPR load.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

for (const MCPhysReg *I = IStart; *I; ++I) {
     else if (AMDGPU::SReg_32RegClass.contains(*I))
       RC = &AMDGPU::SGPR_32RegClass;
     else
       llvm_unreachable("Unexpected register class in CSRsViaCopy!");
 
     Register NewVR = MRI->createVirtualRegister(RC);
     // Create copy from CSR to a virtual register.
     Entry->addLiveIn(*I);
-    BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
-      .addReg(*I);
+    TII->buildCopy(*Entry, MBBI, DebugLoc(), NewVR, *I);
 
     // Insert the copy-back instructions right before the terminator.
     for (auto *Exit : Exits)
-      BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
-              TII->get(TargetOpcode::COPY), *I)
-        .addReg(NewVR);
+      TII->buildCopy(*Exit, Exit->getFirstTerminator(), DebugLoc(), *I, NewVR);
   }
 }
 
 SDValue SITargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
   const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
 
   const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
   assert(ImmOp);
   // FIXME: We could handle FrameIndex values here.
   if (!ImmOp->isImm())
     return false;
 
   unsigned Opc = UseMI.getOpcode();
-  if (Opc == AMDGPU::COPY) {
+  if (UseMI.isCopy()) {
     Register DstReg = UseMI.getOperand(0).getReg();
     bool Is16Bit = getOpSize(UseMI, 0) == 2;
     bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
     unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
     APInt Imm(32, ImmOp->getImm());
 
     if (UseMI.getOperand(1).getSubReg() == AMDGPU::hi16)
       Imm = Imm.ashr(16);
unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
                                          unsigned SubIdx,
                                          const TargetRegisterClass *SubRC)
                                          const {
   MachineBasicBlock *MBB = MI->getParent();
   DebugLoc DL = MI->getDebugLoc();
   Register SubReg = MRI.createVirtualRegister(SubRC);
 
   if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
-    BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
-      .addReg(SuperReg.getReg(), 0, SubIdx);
+    buildCopy(*MBB, MI, DL, SubReg, SuperReg.getReg(), 0, SubIdx);
     return SubReg;
   }
 
   // Just in case the super register is itself a sub-register, copy it to a new
   // value so we don't need to worry about merging its subreg index with the
   // SubIdx passed to this function. The register coalescer should be able to
   // eliminate this extra copy.
   Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
 
-  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
-    .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
+  buildCopy(*MBB, MI, DL, NewSuperReg, SuperReg.getReg(), 0,
+            SuperReg.getSubReg());
 
-  BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
-    .addReg(NewSuperReg, 0, SubIdx);
+  buildCopy(*MBB, MI, DL, SubReg, NewSuperReg, 0, SubIdx);
 
   return SubReg;
 }
 
 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
   MachineBasicBlock::iterator MII,
   MachineRegisterInfo &MRI,
   MachineOperand &Op,
Register SIInstrInfo::readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
   const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
   Register DstReg = MRI.createVirtualRegister(SRC);
   unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
 
   if (RI.hasAGPRs(VRC)) {
     VRC = RI.getEquivalentVGPRClass(VRC);
     Register NewSrcReg = MRI.createVirtualRegister(VRC);
-    BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
-            get(TargetOpcode::COPY), NewSrcReg)
-        .addReg(SrcReg);
+    buildCopy(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), NewSrcReg,
+              SrcReg);
     SrcReg = NewSrcReg;
   }
 
   if (SubRegs == 1) {
     BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
             get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
         .addReg(SrcReg);
     return DstReg;
case AMDGPU::S_SUB_CO_PSEUDO: {
       unsigned Opc = (Inst.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
                          ? AMDGPU::V_ADDC_U32_e64
                          : AMDGPU::V_SUBB_U32_e64;
       const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
 
       Register CarryInReg = Inst.getOperand(4).getReg();
       if (!MRI.constrainRegClass(CarryInReg, CarryRC)) {
         Register NewCarryReg = MRI.createVirtualRegister(CarryRC);
-        BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY), NewCarryReg)
-            .addReg(CarryInReg);
+        buildCopy(*MBB, &Inst, Inst.getDebugLoc(), NewCarryReg, CarryInReg);
       }
 
       Register CarryOutReg = Inst.getOperand(1).getReg();
 
       Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass(
           MRI.getRegClass(Inst.getOperand(0).getReg())));
       MachineInstr *CarryOp =
           BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(Opc), DestReg)
if (IsSCC) {
     // replacing the SCCSource with the COPY source register
     bool CopyFound = false;
     for (MachineInstr &CandI :
          make_range(std::next(MachineBasicBlock::reverse_iterator(Inst)),
                     Inst.getParent()->rend())) {
       if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) !=
           -1) {
         if (CandI.isCopy() && CandI.getOperand(0).getReg() == AMDGPU::SCC) {
-          BuildMI(MBB, MII, DL, get(AMDGPU::COPY), CopySCC)
-              .addReg(CandI.getOperand(1).getReg());
+          buildCopy(MBB, MII, DL, CopySCC, CandI.getOperand(1).getReg());
           CopyFound = true;
         }
         break;
       }
     }
     if (!CopyFound) {
       // SCC def is not a copy
       // Insert a trivial select instead of creating a copy, because a copy from
static const std::pair<MachineMemOperand::Flags, const char *> TargetFlags[] =
       {
           {MONoClobber, "amdgpu-noclobber"},
       };
 
   return ArrayRef(TargetFlags);
 }
 
 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {
-  return !MI.isTerminator() && MI.getOpcode() != AMDGPU::COPY &&
+  return !MI.isTerminator() && !MI.isCopy() &&
          MI.modifiesRegister(AMDGPU::EXEC, &RI);
 }
 
 MachineInstrBuilder
 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator I,
                            const DebugLoc &DL,
                            Register DestReg) const {

 
 MachineInstr *SIInstrInfo::createPHIDestinationCopy(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt,
     const DebugLoc &DL, Register Src, Register Dst) const {
   auto Cur = MBB.begin();
   if (Cur != MBB.end())
     do {
       if (!Cur->isPHI() && Cur->readsRegister(Dst))
-        return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
+        return buildCopy(MBB, Cur, DL, Dst, Src);
       ++Cur;
     } while (Cur != MBB.end() && Cur != LastPHIIt);
 
   return TargetInstrInfo::createPHIDestinationCopy(MBB, LastPHIIt, DL, Src,
                                                    Dst);
 }
 
 MachineInstr *SIInstrInfo::createPHISourceCopy(

llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp

if (SimpleIf) {
     auto UseMI = MRI->use_instr_nodbg_begin(SaveExecReg);
     SimpleIf = !hasKill(MI.getParent(), UseMI->getParent());
   }
 
   // Add an implicit def of exec to discourage scheduling VALU after this which
   // will interfere with trying to form s_and_saveexec_b64 later.
   Register CopyReg = SimpleIf ? SaveExecReg
                        : MRI->createVirtualRegister(BoolRC);
-  MachineInstr *CopyExec =
-    BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
-    .addReg(Exec)
-    .addReg(Exec, RegState::ImplicitDefine);
+  MachineInstrBuilder CopyExec = MachineInstrBuilder(
+      *MBB.getParent(), TII->buildCopy(MBB, I, DL, CopyReg, Exec));
+  CopyExec.addReg(Exec, RegState::ImplicitDefine);
   LoweredIf.insert(CopyReg);
 
   Register Tmp = MRI->createVirtualRegister(BoolRC);
 
   MachineInstr *And =
     BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
     .addReg(CopyReg)
     .add(Cond);

llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

 #endif
 
 bool SILowerI1Copies::lowerCopiesFromI1() {
   bool Changed = false;
   SmallVector<MachineInstr *, 4> DeadCopies;
 
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB) {
-      if (MI.getOpcode() != AMDGPU::COPY)
+      if (!MI.isCopy())
         continue;
 
       Register DstReg = MI.getOperand(0).getReg();
       Register SrcReg = MI.getOperand(1).getReg();
       if (!isVreg1(SrcReg))
         continue;
 
       if (isLaneMaskReg(DstReg) || isVreg1(DstReg))
for (MachineInstr *MI : Vreg1Phis) {
 
     // Collect incoming values.
     for (unsigned i = 1; i < MI->getNumOperands(); i += 2) {
       assert(i + 1 < MI->getNumOperands());
       Register IncomingReg = MI->getOperand(i).getReg();
       MachineBasicBlock *IncomingMBB = MI->getOperand(i + 1).getMBB();
       MachineInstr *IncomingDef = MRI->getUniqueVRegDef(IncomingReg);
 
-      if (IncomingDef->getOpcode() == AMDGPU::COPY) {
+      if (IncomingDef->isCopy()) {
         IncomingReg = IncomingDef->getOperand(1).getReg();
         assert(isLaneMaskReg(IncomingReg) || isVreg1(IncomingReg));
         assert(!IncomingDef->getOperand(1).getSubReg());
       } else if (IncomingDef->getOpcode() == AMDGPU::IMPLICIT_DEF) {
         continue;
       } else {
         assert(IncomingDef->isPHI() || PhiRegisters.count(IncomingReg));
       }
bool SILowerI1Copies::lowerCopiesToI1() {
   MachineSSAUpdater SSAUpdater(*MF);
   LoopFinder LF(*DT, *PDT);
   SmallVector<MachineInstr *, 4> DeadCopies;
 
   for (MachineBasicBlock &MBB : *MF) {
     LF.initialize(MBB);
 
     for (MachineInstr &MI : MBB) {
-      if (MI.getOpcode() != AMDGPU::IMPLICIT_DEF &&
-          MI.getOpcode() != AMDGPU::COPY)
+      if (MI.getOpcode() != AMDGPU::IMPLICIT_DEF && !MI.isCopy())
         continue;
 
       Register DstReg = MI.getOperand(0).getReg();
       if (!isVreg1(DstReg))
         continue;
 
       Changed = true;
 

 
 bool SILowerI1Copies::isConstantLaneMask(Register Reg, bool &Val) const {
   const MachineInstr *MI;
   for (;;) {
     MI = MRI->getUniqueVRegDef(Reg);
     if (MI->getOpcode() == AMDGPU::IMPLICIT_DEF)
       return true;
 
-    if (MI->getOpcode() != AMDGPU::COPY)
+    if (!MI->isCopy())
       break;
 
     Reg = MI->getOperand(1).getReg();
     if (!Reg.isVirtual())
       return false;
     if (!isLaneMaskReg(Reg))
       return false;
   }
void SILowerI1Copies::buildMergeLaneMasks(MachineBasicBlock &MBB,
                                           unsigned PrevReg, unsigned CurReg) {
   bool PrevVal = false;
   bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal);
   bool CurVal = false;
   bool CurConstant = isConstantLaneMask(CurReg, CurVal);
 
   if (PrevConstant && CurConstant) {
     if (PrevVal == CurVal) {
-      BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
+      TII->buildCopy(MBB, I, DL, DstReg, CurReg);
     } else if (CurVal) {
-      BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
+      TII->buildCopy(MBB, I, DL, DstReg, ExecReg);
     } else {
       BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)
           .addReg(ExecReg)
           .addImm(-1);
     }
     return;
   }
 
if (PrevConstant && PrevVal) {
       CurMaskedReg = createLaneMaskReg(*MF);
       BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)
           .addReg(CurReg)
           .addReg(ExecReg);
     }
   }
 
   if (PrevConstant && !PrevVal) {
-    BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
-        .addReg(CurMaskedReg);
+    TII->buildCopy(MBB, I, DL, DstReg, CurMaskedReg);
   } else if (CurConstant && !CurVal) {
-    BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
-        .addReg(PrevMaskedReg);
+    TII->buildCopy(MBB, I, DL, DstReg, PrevMaskedReg);
   } else if (PrevConstant && PrevVal) {
     BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)
         .addReg(CurMaskedReg)
         .addReg(ExecReg);
   } else {
     BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)
         .addReg(PrevMaskedReg)
         .addReg(CurMaskedReg ? CurMaskedReg : ExecReg);
   }
 }

llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp

if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
       }
       LastLowLatencyPos = BestPos;
       if (IsLowLatencyUser)
         LastLowLatencyUser = BestPos;
     } else if (IsLowLatencyUser) {
       LastLowLatencyUser = i;
     // Moves COPY instructions on which depends
     // the low latency instructions too.
-    } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) {
+    } else if (SU->getInstr()->isCopy()) {
       bool CopyForLowLat = false;
       for (SDep& SuccDep : SU->Succs) {
         SUnit *Succ = SuccDep.getSUnit();
         if (SuccDep.isWeak() || Succ->NodeNum >= DAGSize)
           continue;
         if (SITII->isLowLatencyInstruction(*Succ->getInstr())) {
           CopyForLowLat = true;
         }

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST,
   unsigned Src = IsStore ? ValueReg : Reg;
   bool IsVGPR = TRI->isVGPR(MRI, Reg);
   DebugLoc DL = MI->getDebugLoc();
   if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) {
     // Spiller during regalloc may restore a spilled register to its superclass.
     // It could result in AGPR spills restored to VGPRs or the other way around,
     // making the src and dst with identical regclasses at this point. It just
     // needs a copy in such cases.
-    auto CopyMIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), Dst)
-                       .addReg(Src, getKillRegState(IsKill));
+    MachineInstrBuilder CopyMIB =
+        MachineInstrBuilder(*MBB.getParent(), TII->buildCopy(MBB, MI, DL, Dst));
+    CopyMIB.addReg(Src, getKillRegState(IsKill));
     CopyMIB->setAsmPrinterFlag(MachineInstr::ReloadReuse);
     return CopyMIB;
   }
   unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
                                     : AMDGPU::V_ACCVGPR_READ_B32_e64;
 
   auto MIB = BuildMI(MBB, MI, DL, TII->get(Opc), Dst)
                  .addReg(Src, getKillRegState(IsKill));
default: {
 
             BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg)
               .addReg(FrameReg)
               .addImm(ST.getWavefrontSizeLog2());
             BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg)
                 .addReg(ScaledReg, RegState::Kill)
                 .addImm(Offset);
             if (!IsSALU)
-              BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
-                  .addReg(ScaledReg, RegState::Kill);
+              TII->buildCopy(*MBB, MI, DL, ResultReg, ScaledReg,
+                             RegState::Kill);
             else
               ResultReg = ScaledReg;
 
             // If there were truly no free SGPRs, we need to undo everything.
             if (!TmpScaledReg.isValid()) {
               BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg)
                 .addReg(ScaledReg, RegState::Kill)
                 .addImm(-Offset);

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

 // This shall not be done too early not to prevent possible folding which may
 // remove matched moves, and this should preferably be done before RA to
 // release saved registers and also possibly after RA which can insert copies
 // too.
 //
 // This is really just a generic peephole that is not a canonical shrinking,
 // although requirements match the pass placement and it reduces code size too.
 MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
-  assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
-         MovT.getOpcode() == AMDGPU::COPY);
+  assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 || MovT.isCopy());
 
   Register T = MovT.getOperand(0).getReg();
   unsigned Tsub = MovT.getOperand(0).getSubReg();
   MachineOperand &Xop = MovT.getOperand(1);
 
   if (!Xop.isReg())
     return nullptr;
   Register X = Xop.getReg();
MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
   bool KilledT = false;
   for (auto Iter = std::next(MovT.getIterator()),
             E = MovT.getParent()->instr_end();
        Iter != E && Count < SearchLimit && !KilledT; ++Iter, ++Count) {
 
     MachineInstr *MovY = &*Iter;
     KilledT = MovY->killsRegister(T, TRI);
 
-    if ((MovY->getOpcode() != AMDGPU::V_MOV_B32_e32 &&
-         MovY->getOpcode() != AMDGPU::COPY) ||
-        !MovY->getOperand(1).isReg()        ||
-        MovY->getOperand(1).getReg() != T   ||
+    if ((MovY->getOpcode() != AMDGPU::V_MOV_B32_e32 && !MovY->isCopy()) ||
+        !MovY->getOperand(1).isReg() || MovY->getOperand(1).getReg() != T ||
         MovY->getOperand(1).getSubReg() != Tsub)
       continue;
 
     Register Y = MovY->getOperand(0).getReg();
     unsigned Ysub = MovY->getOperand(0).getSubReg();
 
     if (!TRI->isVGPR(*MRI, Y))
       continue;
for (auto IY = MovY->getIterator(), I = std::next(MovT.getIterator());
       }
       if (!instReadsReg(&*I, Y, Ysub)) {
         if (!MovX && instModifiesReg(&*I, X, Xsub)) {
           MovX = nullptr;
           break;
         }
         continue;
       }
-      if (MovX ||
-          (I->getOpcode() != AMDGPU::V_MOV_B32_e32 &&
-           I->getOpcode() != AMDGPU::COPY) ||
+      if (MovX || (I->getOpcode() != AMDGPU::V_MOV_B32_e32 && !I->isCopy()) ||
           I->getOperand(0).getReg() != X ||
           I->getOperand(0).getSubReg() != Xsub) {
         MovX = nullptr;
         break;
       }
 
       if (Size > 1 && (I->getNumImplicitOperands() > (I->isCopy() ? 0U : 1U)))
         continue;
for (I = MBB.begin(); I != MBB.end(); I = Next) {
           if (isReverseInlineImm(Src, ReverseImm)) {
             MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
             Src.setImm(ReverseImm);
             continue;
           }
         }
       }
 
-      if (ST->hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
-                            MI.getOpcode() == AMDGPU::COPY)) {
+      if (ST->hasSwap() &&
+          (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 || MI.isCopy())) {
         if (auto *NextMI = matchSwap(MI)) {
           Next = NextMI->getIterator();
           continue;
         }
       }
 
       // Try to use S_ADDK_I32 and S_MULK_I32.
       if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

 }
 
 MachineBasicBlock::iterator
 SIWholeQuadMode::saveSCC(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator Before) {
   Register SaveReg = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 
   MachineInstr *Save =
-      BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), SaveReg)
-          .addReg(AMDGPU::SCC);
+      TII->buildCopy(MBB, Before, DebugLoc(), SaveReg, AMDGPU::SCC);
   MachineInstr *Restore =
-      BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
-          .addReg(SaveReg);
+      TII->buildCopy(MBB, Before, DebugLoc(), AMDGPU::SCC, SaveReg);
 
   LIS->InsertMachineInstrInMaps(*Save);
   LIS->InsertMachineInstrInMaps(*Restore);
   LIS->createAndComputeVirtRegInterval(SaveReg);
 
   return Restore;
 }
 

 }
 
 void SIWholeQuadMode::toWQM(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator Before,
                             Register SavedWQM) {
   MachineInstr *MI;
 
   if (SavedWQM) {
-    MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), Exec)
-             .addReg(SavedWQM);
+    MI = TII->buildCopy(MBB, Before, DebugLoc(), Exec, SavedWQM);
   } else {
     MI = BuildMI(MBB, Before, DebugLoc(), TII->get(WQMOpc), Exec).addReg(Exec);
   }
 
   LIS->InsertMachineInstrInMaps(*MI);
   StateTransition[MI] = StateWQM;
 }
 
void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, bool IsEntry) {
   bool WQMFromExec = IsEntry;
   char State = (IsEntry || !(BI.InNeeds & StateWQM)) ? StateExact : StateWQM;
   char NonStrictState = 0;
   const TargetRegisterClass *BoolRC = TRI->getBoolRC();
 
   auto II = MBB.getFirstNonPHI(), IE = MBB.end();
   if (IsEntry) {
     // Skip the instruction that saves LiveMask
-    if (II != IE && II->getOpcode() == AMDGPU::COPY)
+    if (II != IE && II->isCopy())
       ++II;
   }
 
   // This stores the first instruction where it's safe to switch from WQM to
   // Exact or vice versa.
   MachineBasicBlock::iterator FirstWQM = IE;
 
   // This stores the first instruction where it's safe to switch from Strict

 }
 
 void SIWholeQuadMode::lowerLiveMaskQueries() {
   for (MachineInstr *MI : LiveMaskQueries) {
     const DebugLoc &DL = MI->getDebugLoc();
     Register Dest = MI->getOperand(0).getReg();
 
     MachineInstr *Copy =
-        BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
-            .addReg(LiveMaskReg);
+        TII->buildCopy(*MI->getParent(), MI, DL, Dest, LiveMaskReg);
 
     LIS->ReplaceMachineInstrInMaps(*MI, *Copy);
     MI->eraseFromParent();
   }
 }
 
 void SIWholeQuadMode::lowerCopyInstrs() {
   for (MachineInstr *MI : LowerToMovInstrs) {
bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
 
   MachineBasicBlock &Entry = MF.front();
   MachineBasicBlock::iterator EntryMI = Entry.getFirstNonPHI();
 
   // Store a copy of the original live mask when required
   if (NeedsLiveMask || (GlobalFlags & StateWQM)) {
     LiveMaskReg = MRI->createVirtualRegister(TRI->getBoolRC());
     MachineInstr *MI =
-        BuildMI(Entry, EntryMI, DebugLoc(), TII->get(AMDGPU::COPY), LiveMaskReg)
-            .addReg(Exec);
+        TII->buildCopy(Entry, EntryMI, DebugLoc(), LiveMaskReg, Exec);
     LIS->InsertMachineInstrInMaps(*MI);
   }
 
   LLVM_DEBUG(printInfo());
 
   lowerLiveMaskQueries();
   lowerCopyInstrs();