[MachineInstr] Use isCopy helper function (NFC).

[cdevadas]

It is not needed with the alternate implementation of Pred-Copy that was enabled only during liverange split D150388.

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

void markDefDead(MachineInstr &MI, MachineInstr &DefMI,
     // and as a result, %3, %2, %1 are dead.
     MachineInstr *PrevMI = &MI;
     while (PrevMI != &DefMI) {
       Register PrevRegSrc = getArtifactSrcReg(*PrevMI);
 
       MachineInstr *TmpDef = MRI.getVRegDef(PrevRegSrc);
       if (MRI.hasOneUse(PrevRegSrc)) {
         if (TmpDef != &DefMI) {
-          assert((TmpDef->getOpcode() == TargetOpcode::COPY ||
-                  isArtifactCast(TmpDef->getOpcode())) &&
+          assert((TmpDef->isCopy() || isArtifactCast(TmpDef->getOpcode())) &&
                  "Expecting copy or artifact cast here");
 
           DeadInsts.push_back(TmpDef);
         }
       } else
         break;
       PrevMI = TmpDef;
     }

llvm/lib/CodeGen/CodeGenCommonISel.cpp

unsigned llvm::getInvertedFPClassTest(unsigned Test) {
   case fcNegFinite:
     return InvertedTest;
   }
   return 0;
 }
 
 static MachineOperand *getSalvageOpsForCopy(const MachineRegisterInfo &MRI,
                                             MachineInstr &Copy) {
-  assert(Copy.getOpcode() == TargetOpcode::COPY && "Must be a COPY");
+  assert(Copy.isCopy() && "Must be a COPY");
 
   return &Copy.getOperand(1);
 }
 
 static MachineOperand *getSalvageOpsForTrunc(const MachineRegisterInfo &MRI,
                                             MachineInstr &Trunc,
                                             SmallVectorImpl<uint64_t> &Ops) {
   assert(Trunc.getOpcode() == TargetOpcode::G_TRUNC && "Must be a G_TRUNC");

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

if (OutInfo.Regs.size() > 1) {
           dbgs() << "... Cannot handle arguments in multiple registers.\n");
       return false;
     }
 
     // Check if we copy the register, walking through copies from virtual
     // registers. Note that getDefIgnoringCopies does not ignore copies from
     // physical registers.
     MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
-    if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
+    if (!RegDef || !RegDef->isCopy()) {
       LLVM_DEBUG(
           dbgs()
           << "... Parameter was not copied into a VReg, cannot tail call.\n");
       return false;
     }
 
     // Got a copy. Verify that it's the same as the register we want.
     Register CopyRHS = RegDef->getOperand(1).getReg();

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

 bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
   if (matchCombineCopy(MI)) {
     applyCombineCopy(MI);
     return true;
   }
   return false;
 }
 bool CombinerHelper::matchCombineCopy(MachineInstr &MI) {
-  if (MI.getOpcode() != TargetOpcode::COPY)
+  if (!MI.isCopy())
     return false;
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
   return canReplaceReg(DstReg, SrcReg, MRI);
 }
 void CombinerHelper::applyCombineCopy(MachineInstr &MI) {
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {
       // register class.
       //
       // We can't use NoSubRegister by name as it's defined by each target but
       // it's always defined to be 0 by tablegen.
       if (SrcReg.isVirtual() && Src.getSubReg() == 0 /*NoSubRegister*/ &&
           MRI.getType(SrcReg).isValid()) {
         // For COPYs we don't do anything, don't increase the depth.
         computeKnownBitsImpl(SrcReg, Known2, DemandedElts,
-                             Depth + (Opcode != TargetOpcode::COPY));
+                             Depth + (!MI.isCopy()));
         Known = KnownBits::commonBits(Known, Known2);
         // If we reach a point where we don't know anything
         // just stop looking through the operands.
         if (Known.One == 0 && Known.Zero == 0)
           break;
       } else {
         // We know nothing.
         Known = KnownBits(BitWidth);

llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
       // Select this instruction.
       MachineInstr &MI = *MII;
 
       // And have our iterator point to the next instruction, if there is one.
       if (MII == Begin)
         ReachedBegin = true;
       else
         --MII;
-      if (MI.getOpcode() != TargetOpcode::COPY)
+      if (!MI.isCopy())
         continue;
       Register SrcReg = MI.getOperand(1).getReg();
       Register DstReg = MI.getOperand(0).getReg();
       if (SrcReg.isVirtual() && DstReg.isVirtual()) {
         auto SrcRC = MRI.getRegClass(SrcReg);
         auto DstRC = MRI.getRegClass(DstReg);
         if (SrcRC == DstRC) {
           MRI.replaceRegWith(DstReg, SrcReg);

llvm/lib/CodeGen/GlobalISel/Utils.cpp

 std::optional<DefinitionAndSourceRegister>
 llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) {
   Register DefSrcReg = Reg;
   auto *DefMI = MRI.getVRegDef(Reg);
   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
   if (!DstTy.isValid())
     return std::nullopt;
   unsigned Opc = DefMI->getOpcode();
-  while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
+  while (DefMI->isCopy() || isPreISelGenericOptimizationHint(Opc)) {
     Register SrcReg = DefMI->getOperand(1).getReg();
     auto SrcTy = MRI.getType(SrcReg);
     if (!SrcTy.isValid())
       break;
     DefMI = MRI.getVRegDef(SrcReg);
     DefSrcReg = SrcReg;
     Opc = DefMI->getOpcode();
   }