[MachineInstr] Introduce TII buildCopy helper functions (NFC).

[qcolombet]

Hey,

What's the long term plan for this helper?

I am not mad at the refactoring itself, but I'm wondering what kind of criteria we should use to decide when we add such helper.

For instance, should we do the same thing for PHI, INSERT_SUBREG, etc. and why or why not.
Also, should these helper be virtual or not?

I guess where I am going is what do you intend to simplify/achieve with them?

The bottom line is without a proper rationale on why we need this helper, I feel that it gets difficult to know which method should be used to construct a copy.
Right now we have BuildMI (and the underlying MachineInstrBuilder object that can be called directly), MachineFunction::CreateMachineInstr, MachineIRBuilder::buildInstr (BTW MachineIRBuilder has its own MachineIRBuilder::buildCopy) and we add a new method here.

I believe we need to disambiguate when this one should be used and why.

Admittedly I'm playing the devil's advocate here (I actually like the patch) but I think it is important to flush out the goals and intended usages to be able to better guide future users of this (and the other) API(s).

Cheers,
-Quentin

[cdevadas]

In D143753#4131294, @qcolombet wrote:

Hey,

What's the long term plan for this helper?

I am not mad at the refactoring itself, but I'm wondering what kind of criteria we should use to decide when we add such helper.

The real motivation for these buildCopy helper functions is to minimize the additional code changes required while introducing getCopyOpcode() as part of D143754.
One could probably say that "still you could have avoided the buildCopy functions, and instead replace TargetOpcode::COPY with getCopyOpcode()".
I think it would be ok to refactor the code if found an opportunity while working around that code.

For instance, should we do the same thing for PHI, INSERT_SUBREG, etc. and why or why not.
Also, should these helper be virtual or not?

As I said earlier, COPY wasn't a random pick, but rather a code refactor for another patch.

I guess where I am going is what do you intend to simplify/achieve with them?

I felt it was better with buildCopy rather than the direct replacement of TargetOpcode::COPY with getCopyOpcode() in their original BuildMI instances. You tend to agree with that towards the end - "(I actually like the patch)".

The bottom line is without a proper rationale on why we need this helper, I feel that it gets difficult to know which method should be used to construct a copy.
Right now we have BuildMI (and the underlying MachineInstrBuilder object that can be called directly), MachineFunction::CreateMachineInstr, MachineIRBuilder::buildInstr (BTW MachineIRBuilder has its own MachineIRBuilder::buildCopy) and we add a new method here.

I agree. All my buildCopy instances currently return MachineInstr*. I wasn't sure they should return MachineInstrBuilder or any other form as you mentioned. It can be worked out if anyone has a better suggestion.
And about MachineIRBuilder::buildCopy, I feel it is better to retain this very specific instance considering the actual function being called ( the generic MachineIRBuilder::buildInstr) and the operands used which are different from the instances I added.

I believe we need to disambiguate when this one should be used and why.

Admittedly I'm playing the devil's advocate here (I actually like the patch) but I think it is important to flush out the goals and intended usages to be able to better guide future users of this (and the other) API(s).

Cheers,
-Quentin

[cdevadas]

Abandoning this patch as well. It is no longer needed after D150388.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
 
   /// True if the instruction is bound to the top of its basic block and no
   /// other instructions shall be inserted before it. This can be implemented
   /// to prevent register allocator to insert spills before such instructions.
   virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
     return false;
   }
 
+  /// Helper function for inserting a COPY to \p Dst at insertion point \p InsPt
+  /// in \p MBB block.
+  MachineInstr *buildCopy(MachineBasicBlock &MBB,
+                          MachineBasicBlock::iterator InsPt, const DebugLoc &DL,
+                          Register Dst) const {
+    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst);
+  }
+
+  /// Helper function for inserting a COPY to \p Dst from \p Src at insertion
+  /// point \p InsPt in \p MBB block.
+  MachineInstr *buildCopy(MachineBasicBlock &MBB,
+                          MachineBasicBlock::iterator InsPt, const DebugLoc &DL,
+                          Register Dst, Register Src, unsigned Flags = 0,
+                          unsigned SubReg = 0) const {
+    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
+        .addReg(Src, Flags, SubReg);
+  }
+
+  /// Helper function for inserting a COPY to \p Dst from \p Src at insertion
+  /// point \p InsPt in \p MBB block. Get the Debug Location from \p MIMD.
+  MachineInstrBuilder buildCopy(MachineBasicBlock &MBB,
+                                MachineBasicBlock::iterator InsPt,
+                                const MIMetadata &MIMD, Register Dst,
+                                Register Src, unsigned Flags = 0,
+                                unsigned SubReg = 0) const {
+    MachineFunction &MF = *MBB.getParent();
+    MachineInstr *MI =
+        MF.CreateMachineInstr(get(TargetOpcode::COPY), MIMD.getDL());
+    MBB.insert(InsPt, MI);
+    return MachineInstrBuilder(MF, MI)
+        .setPCSections(MIMD.getPCSections())
+        .addReg(Dst, RegState::Define)
+        .addReg(Src, Flags, SubReg);
+  }
+
   /// During PHI eleimination lets target to make necessary checks and
   /// insert the copy to the PHI destination register in a target specific
   /// manner.
   virtual MachineInstr *createPHIDestinationCopy(
       MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
       const DebugLoc &DL, Register Src, Register Dst) const {
-    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
-        .addReg(Src);
+    return buildCopy(MBB, InsPt, DL, Dst, Src);
   }
 
   /// During PHI eleimination lets target to make necessary checks and
   /// insert the copy to the PHI destination register in a target specific
   /// manner.
   virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
                                             MachineBasicBlock::iterator InsPt,
                                             const DebugLoc &DL, Register Src,
                                             unsigned SrcSubReg,
                                             Register Dst) const {
-    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
-        .addReg(Src, 0, SrcSubReg);
+    return buildCopy(MBB, InsPt, DL, Dst, Src, 0, SrcSubReg);
   }
 
   /// Returns a \p outliner::OutlinedFunction struct containing target-specific
   /// information for a set of outlining candidates.
   virtual outliner::OutlinedFunction getOutliningCandidateInfo(
       std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
     llvm_unreachable(
         "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");

llvm/lib/CodeGen/EarlyIfConversion.cpp

void SSAIfConv::replacePHIInstrs() {
   // Convert all PHIs to select instructions inserted before FirstTerm.
   for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
     PHIInfo &PI = PHIs[i];
     LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
     Register DstReg = PI.PHI->getOperand(0).getReg();
     if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
       // We do not need the select instruction if both incoming values are
       // equal, but we do need a COPY.
-      BuildMI(*Head, FirstTerm, HeadDL, TII->get(TargetOpcode::COPY), DstReg)
-          .addReg(PI.TReg);
+      TII->buildCopy(*Head, FirstTerm, HeadDL, DstReg, PI.TReg);
     } else {
       TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg,
                         PI.FReg);
     }
     LLVM_DEBUG(dbgs() << "          --> " << *std::prev(FirstTerm));
     PI.PHI->eraseFromParent();
     PI.PHI = nullptr;
   }

llvm/lib/CodeGen/GlobalISel/Utils.cpp

Register llvm::constrainOperandRegClass(
   // If we created a new virtual register because the class is not compatible
   // then create a copy between the new and the old register.
   if (ConstrainedReg != Reg) {
     MachineBasicBlock::iterator InsertIt(&InsertPt);
     MachineBasicBlock &MBB = *InsertPt.getParent();
     // FIXME: The copy needs to have the classes constrained for its operands.
     // Use operand's regbank to get the class for old register (Reg).
     if (RegMO.isUse()) {
-      BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
-              TII.get(TargetOpcode::COPY), ConstrainedReg)
-          .addReg(Reg);
+      TII.buildCopy(MBB, InsertIt, InsertPt.getDebugLoc(), ConstrainedReg, Reg);
     } else {
       assert(RegMO.isDef() && "Must be a definition");
-      BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
-              TII.get(TargetOpcode::COPY), Reg)
-          .addReg(ConstrainedReg);
+      TII.buildCopy(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), Reg,
+                    ConstrainedReg);
     }
     if (GISelChangeObserver *Observer = MF.getObserver()) {
       Observer->changingInstr(*RegMO.getParent());
     }
     RegMO.setReg(ConstrainedReg);
     if (GISelChangeObserver *Observer = MF.getObserver()) {
       Observer->changedInstr(*RegMO.getParent());
     }
if (LiveIn) {
     // re-insert the copy.
   } else {
     // The live in register was not present, so add it.
     LiveIn = MF.addLiveIn(PhysReg, &RC);
     if (RegTy.isValid())
       MRI.setType(LiveIn, RegTy);
   }
 
-  BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
-    .addReg(PhysReg);
+  TII.buildCopy(EntryMBB, EntryMBB.begin(), DL, LiveIn, PhysReg);
   if (!EntryMBB.isLiveIn(PhysReg))
     EntryMBB.addLiveIn(PhysReg);
   return LiveIn;
 }
 
 std::optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode,
                                              const Register Op1, uint64_t Imm,
                                              const MachineRegisterInfo &MRI) {

llvm/lib/CodeGen/MachineBasicBlock.cpp

for (;I != E && I->isCopy(); ++I)
         Register VirtReg = I->getOperand(0).getReg();
         if (!MRI.constrainRegClass(VirtReg, RC))
           llvm_unreachable("Incompatible live-in register class.");
         return VirtReg;
       }
 
   // No luck, create a virtual register.
   Register VirtReg = MRI.createVirtualRegister(RC);
-  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
-    .addReg(PhysReg, RegState::Kill);
+  TII.buildCopy(*this, I, DebugLoc(), VirtReg, PhysReg, RegState::Kill);
   if (!LiveIn)
     addLiveIn(PhysReg);
   return VirtReg;
 }
 
 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
   getParent()->splice(NewAfter->getIterator(), getIterator());
 }

llvm/lib/CodeGen/MachinePipeliner.cpp

for (unsigned i = 1, n = PI.getNumOperands(); i != n; i += 2) {
         continue;
 
       // If the operand uses a subregister, replace it with a new register
       // without subregisters, and generate a copy to the new register.
       Register NewReg = MRI.createVirtualRegister(RC);
       MachineBasicBlock &PredB = *PI.getOperand(i+1).getMBB();
       MachineBasicBlock::iterator At = PredB.getFirstTerminator();
       const DebugLoc &DL = PredB.findDebugLoc(At);
-      auto Copy = BuildMI(PredB, At, DL, TII->get(TargetOpcode::COPY), NewReg)
-                    .addReg(RegOp.getReg(), getRegState(RegOp),
-                            RegOp.getSubReg());
+      auto Copy = TII->buildCopy(PredB, At, DL, NewReg, RegOp.getReg(),
+                                 getRegState(RegOp), RegOp.getSubReg());
       Slots.insertMachineInstrInMaps(*Copy);
       RegOp.setReg(NewReg);
       RegOp.setSubReg(0);
     }
   }
 }
 
 /// The SMS algorithm consists of the following main steps:

llvm/lib/CodeGen/MachineRegisterInfo.cpp

if (LiveIns[i].second) {
         //
         // It would be preferable to have isel avoid creating live-in
         // records for unused arguments in the first place, but it's
         // complicated by the debug info code for arguments.
         LiveIns.erase(LiveIns.begin() + i);
         --i; --e;
       } else {
         // Emit a copy.
-        BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
-                TII.get(TargetOpcode::COPY), LiveIns[i].second)
-          .addReg(LiveIns[i].first);
+        TII.buildCopy(*EntryMBB, EntryMBB->begin(), DebugLoc(),
+                      LiveIns[i].second, LiveIns[i].first);
 
         // Add the register to the entry block live-in set.
         EntryMBB->addLiveIn(LiveIns[i].first);
       }
     } else {
       // Add the register to the entry block live-in set.
       EntryMBB->addLiveIn(LiveIns[i].first);
     }

llvm/lib/CodeGen/ModuloSchedule.cpp

for (MachineRegisterInfo::use_instr_iterator I = MRI.use_instr_begin(Def),
         // definition. If one occurs, then split the lifetime.
         unsigned SplitReg = 0;
         for (auto &BBJ : make_range(MachineBasicBlock::instr_iterator(MI),
                                     KernelBB->instr_end()))
           if (BBJ.readsRegister(Def)) {
             // We split the lifetime when we find the first use.
             if (SplitReg == 0) {
               SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def));
-              BuildMI(*KernelBB, MI, MI->getDebugLoc(),
-                      TII->get(TargetOpcode::COPY), SplitReg)
-                  .addReg(Def);
+              TII->buildCopy(*KernelBB, MI, MI->getDebugLoc(), SplitReg, Def);
             }
             BBJ.substituteRegister(Def, SplitReg, 0, *TRI);
           }
         if (!SplitReg)
           continue;
         // Search through each of the epilog blocks for any uses to be renamed.
         for (auto &Epilog : EpilogBBs)
           for (auto &I : *Epilog)
if (!InProlog && !Phi->isPHI() && StagePhi < StageSched)
       ReplaceReg = NewReg;
     if (ReplaceReg) {
       const TargetRegisterClass *NRC =
           MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg));
       if (NRC)
         UseOp.setReg(ReplaceReg);
       else {
         Register SplitReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
-        BuildMI(*BB, UseMI, UseMI->getDebugLoc(), TII->get(TargetOpcode::COPY),
-                SplitReg)
-            .addReg(ReplaceReg);
+        TII->buildCopy(*BB, UseMI, UseMI->getDebugLoc(), SplitReg, ReplaceReg);
         UseOp.setReg(SplitReg);
       }
     }
   }
 }
 
 bool ModuloScheduleExpander::isLoopCarried(MachineInstr &Phi) {
   if (!Phi.isPHI())

llvm/lib/CodeGen/PeepholeOptimizer.cpp

for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
       // %1:g8rc_and_g8rc_nox0 = EXTSW %0:g8rc
       // %6:gprc_and_gprc_nor0 = COPY %1.sub_32:g8rc_and_g8rc_nox0
       // %3:gprc_and_gprc_nor0 = COPY %6:gprc_and_gprc_nor0
       //
       if (UseSrcSubIdx)
         RC = MRI->getRegClass(UseMI->getOperand(0).getReg());
 
       Register NewVR = MRI->createVirtualRegister(RC);
-      BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
-              TII->get(TargetOpcode::COPY), NewVR)
-        .addReg(DstReg, 0, SubIdx);
+      TII->buildCopy(*UseMBB, UseMI, UseMI->getDebugLoc(), NewVR, DstReg, 0,
+                     SubIdx);
       if (UseSrcSubIdx)
         UseMO->setSubReg(0);
 
       UseMO->setReg(NewVR);
       ++NumReuse;
       Changed = true;
     }
   }
PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
   // Find the new source to use in the COPY rewrite.
   RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
 
   // Insert the COPY.
   const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
   Register NewVReg = MRI->createVirtualRegister(DefRC);
 
   MachineInstr *NewCopy =
-      BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
-              TII->get(TargetOpcode::COPY), NewVReg)
-          .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
+      TII->buildCopy(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
+                     NewVReg, NewSrc.Reg, 0, NewSrc.SubReg);
 
   if (Def.SubReg) {
     NewCopy->getOperand(0).setSubReg(Def.SubReg);
     NewCopy->getOperand(0).setIsUndef();
   }
 
   LLVM_DEBUG(dbgs() << "-- RewriteSource\n");
   LLVM_DEBUG(dbgs() << "   Replacing: " << CopyLike);

llvm/lib/CodeGen/PrologEpilogInserter.cpp

static void insertCSRSaves(MachineBasicBlock &SaveBlock,
 
   MachineBasicBlock::iterator I = SaveBlock.begin();
   if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
     for (const CalleeSavedInfo &CS : CSI) {
       // Insert the spill to the stack frame.
       unsigned Reg = CS.getReg();
 
       if (CS.isSpilledToReg()) {
-        BuildMI(SaveBlock, I, DebugLoc(),
-                TII.get(TargetOpcode::COPY), CS.getDstReg())
-          .addReg(Reg, getKillRegState(true));
+        TII.buildCopy(SaveBlock, I, DebugLoc(), CS.getDstReg(), Reg,
+                      getKillRegState(true));
       } else {
         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
         TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC,
                                 TRI, Register());
       }
     }
   }
 }
static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
   // Restore all registers immediately before the return and any
   // terminators that precede it.
   MachineBasicBlock::iterator I = RestoreBlock.getFirstTerminator();
 
   if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) {
     for (const CalleeSavedInfo &CI : reverse(CSI)) {
       unsigned Reg = CI.getReg();
       if (CI.isSpilledToReg()) {
-        BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
-          .addReg(CI.getDstReg(), getKillRegState(true));
+        TII.buildCopy(RestoreBlock, I, DebugLoc(), Reg, CI.getDstReg(),
+                      getKillRegState(true));
       } else {
         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
         TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC,
                                  TRI, Register());
         assert(I != RestoreBlock.begin() &&
                "loadRegFromStackSlot didn't insert any code!");
         // Insert in reverse order.  loadRegFromStackSlot can insert
         // multiple instructions.

llvm/lib/CodeGen/RegAllocFast.cpp

if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) {
                         << " (tied/earlyclobber resolution)\n");
       freePhysReg(PrevReg);
       LRI->PhysReg = 0;
       allocVirtReg(MI, *LRI, 0, true);
       MachineBasicBlock::iterator InsertBefore =
         std::next((MachineBasicBlock::iterator)MI.getIterator());
       LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
                         << printReg(PrevReg, TRI) << '\n');
-      BuildMI(*MBB, InsertBefore, MI.getDebugLoc(),
-              TII->get(TargetOpcode::COPY), PrevReg)
-        .addReg(LRI->PhysReg, llvm::RegState::Kill);
+      TII->buildCopy(*MBB, InsertBefore, MI.getDebugLoc(), PrevReg,
+                     LRI->PhysReg, llvm::RegState::Kill);
     }
     MachineOperand &MO = MI.getOperand(OpNum);
     if (MO.getSubReg() && !MO.isUndef()) {
       LRI->LastUse = &MI;
     }
   }
   return defineVirtReg(MI, OpNum, VirtReg, true);
 }

llvm/lib/CodeGen/RegisterCoalescer.cpp

if (InsPos != CopyLeftBB->end()) {
       if (IntB.overlaps(InsPosIdx, LIS->getMBBEndIdx(CopyLeftBB)))
         return false;
     }
 
     LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "
                       << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
 
     // Insert new copy to CopyLeftBB.
-    MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
-                                      TII->get(TargetOpcode::COPY), IntB.reg())
-                                  .addReg(IntA.reg());
+    MachineInstr *NewCopyMI = TII->buildCopy(
+        *CopyLeftBB, InsPos, CopyMI.getDebugLoc(), IntB.reg(), IntA.reg());
     SlotIndex NewCopyIdx =
         LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
     IntB.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
     for (LiveInterval::SubRange &SR : IntB.subranges())
       SR.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
 
     // If the newly created Instruction has an address of an instruction that was
     // deleted before (object recycled by the allocator) it needs to be removed from

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

bool FastISel::selectFreeze(const User *I) {
   EVT ETy = TLI.getValueType(DL, I->getOperand(0)->getType());
   if (ETy == MVT::Other || !TLI.isTypeLegal(ETy))
     // Unhandled type, bail out.
     return false;
 
   MVT Ty = ETy.getSimpleVT();
   const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
   Register ResultReg = createResultReg(TyRegClass);
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
-          TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
+  TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg, Reg);
 
   updateValueMap(I, ResultReg);
   return true;
 }
 
 // Remove local value instructions starting from the instruction after
 // SavedLastLocalValue to the current function insert point.
 void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)
Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op,
                                             unsigned OpNum) {
   if (Op.isVirtual()) {
     const TargetRegisterClass *RegClass =
         TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
     if (!MRI.constrainRegClass(Op, RegClass)) {
       // If it's not legal to COPY between the register classes, something
       // has gone very wrong before we got here.
       Register NewOp = createResultReg(RegClass);
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
-              TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
+      TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, NewOp, Op);
       return NewOp;
     }
   }
   return Op;
 }
 
 Register FastISel::fastEmitInst_(unsigned MachineInstOpcode,
                                  const TargetRegisterClass *RC) {
Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addReg(Op0);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
 
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
                                    const TargetRegisterClass *RC, unsigned Op0,
                                    unsigned Op1) {
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   Register ResultReg = createResultReg(RC);
   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addReg(Op0)
         .addReg(Op1);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addReg(Op1);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
                                     const TargetRegisterClass *RC, unsigned Op0,
                                     unsigned Op1, unsigned Op2) {
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   Register ResultReg = createResultReg(RC);
   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
   Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addReg(Op0)
         .addReg(Op1)
         .addReg(Op2);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addReg(Op1)
         .addReg(Op2);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
                                    const TargetRegisterClass *RC, unsigned Op0,
                                    uint64_t Imm) {
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   Register ResultReg = createResultReg(RC);
   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addReg(Op0)
         .addImm(Imm);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addImm(Imm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
                                     const TargetRegisterClass *RC, unsigned Op0,
                                     uint64_t Imm1, uint64_t Imm2) {
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   Register ResultReg = createResultReg(RC);
   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addReg(Op0)
         .addImm(Imm1)
         .addImm(Imm2);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addImm(Imm1)
         .addImm(Imm2);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
                                   const TargetRegisterClass *RC,
                                   const ConstantFP *FPImm) {
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   Register ResultReg = createResultReg(RC);
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addFPImm(FPImm);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addFPImm(FPImm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
                                     const TargetRegisterClass *RC, unsigned Op0,
                                     unsigned Op1, uint64_t Imm) {
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   Register ResultReg = createResultReg(RC);
   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addReg(Op0)
         .addReg(Op1)
         .addImm(Imm);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
         .addReg(Op0)
         .addReg(Op1)
         .addImm(Imm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
                                   const TargetRegisterClass *RC, uint64_t Imm) {
   Register ResultReg = createResultReg(RC);
   const MCInstrDesc &II = TII.get(MachineInstOpcode);
 
   if (II.getNumDefs() >= 1)
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
         .addImm(Imm);
   else {
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II).addImm(Imm);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-            ResultReg)
-        .addReg(II.implicit_defs()[0]);
+    TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg,
+                  II.implicit_defs()[0]);
   }
   return ResultReg;
 }
 
 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
                                               uint32_t Idx) {
   Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
   assert(Register::isVirtualRegister(Op0) &&
          "Cannot yet extract from physregs");
   const TargetRegisterClass *RC = MRI.getRegClass(Op0);
   MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
-          ResultReg).addReg(Op0, 0, Idx);
+  TII.buildCopy(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, ResultReg, Op0, 0, Idx);
   return ResultReg;
 }
 
 /// Emit MachineInstrs to compute the value of Op with all but the least
 /// significant bit set to zero.
 Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) {
   return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);
 }

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
 
   // If all uses are reading from the src physical register and copying the
   // register is either impossible or very expensive, then don't create a copy.
   if (MatchReg && SrcRC->getCopyCost() < 0) {
     VRBase = SrcReg;
   } else {
     // Create the reg, emit the copy.
     VRBase = MRI->createVirtualRegister(DstRC);
-    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
-            VRBase).addReg(SrcReg);
+    TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), VRBase, SrcReg);
   }
 
   SDValue Op(Node, ResNo);
   if (IsClone)
     VRBaseMap.erase(Op);
   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
   (void)isNew; // Silence compiler warning.
   assert(isNew && "Node emitted out of order - early");
if (OpRC) {
         MinNumRegs = 0;
 
       const TargetRegisterClass *ConstrainedRC
         = MRI->constrainRegClass(VReg, OpRC, MinNumRegs);
       if (!ConstrainedRC) {
         OpRC = TRI->getAllocatableClass(OpRC);
         assert(OpRC && "Constraints cannot be fulfilled for allocation");
         Register NewVReg = MRI->createVirtualRegister(OpRC);
-        BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
-                TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
+        TII->buildCopy(*MBB, InsertPos, Op.getNode()->getDebugLoc(), NewVReg,
+                       VReg);
         VReg = NewVReg;
       } else {
         assert(ConstrainedRC->isAllocatable() &&
            "Constraining an allocatable VReg produced an unallocatable class?");
       }
     }
   }
 
const TargetRegisterClass *OpRC =
         TLI->isTypeLegal(OpVT)
             ? TLI->getRegClassFor(OpVT,
                                   Op.getNode()->isDivergent() ||
                                       (IIRC && TRI->isDivergentRegClass(IIRC)))
             : nullptr;
 
     if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
       Register NewVReg = MRI->createVirtualRegister(IIRC);
-      BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
-               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
+      TII->buildCopy(*MBB, InsertPos, Op.getNode()->getDebugLoc(), NewVReg,
+                     VReg);
       VReg = NewVReg;
     }
     // Turn additional physreg operands into implicit uses on non-variadic
     // instructions. This is used by call and return instructions passing
     // arguments in registers.
     bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
     MIB.addReg(VReg, getImplRegState(Imp));
   } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
   if (RC)
     return VReg;
 
   // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
   // register instead.
   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
   assert(RC && "No legal register class for VT supports that SubIdx");
   Register NewReg = MRI->createVirtualRegister(RC);
-  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
-    .addReg(VReg);
+  TII->buildCopy(*MBB, InsertPos, DL, NewReg, VReg);
   return NewReg;
 }
 
 /// EmitSubregNode - Generate machine code for subreg nodes.
 ///
 void InstrEmitter::EmitSubregNode(SDNode *Node,
                                   DenseMap<SDValue, Register> &VRBaseMap,
                                   bool IsClone, bool IsCloned) {
if (DefMI &&
         SubIdx == DefSubIdx &&
         TRC == MRI->getRegClass(SrcReg)) {
       // Optimize these:
       // r1025 = s/zext r1024, 4
       // r1026 = extract_subreg r1025, 4
       // to a copy
       // r1026 = copy r1024
       VRBase = MRI->createVirtualRegister(TRC);
-      BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
-              TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
+      TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), VRBase, SrcReg);
       MRI->clearKillFlags(SrcReg);
     } else {
       // Reg may not support a SubIdx sub-register, and we may need to
       // constrain its register class or issue a COPY to a compatible register
       // class.
       if (Reg.isVirtual())
         Reg = ConstrainForSubReg(Reg, SubIdx,
                                  Node->getOperand(0).getSimpleValueType(),
                                  Node->isDivergent(), Node->getDebugLoc());
       // Create the destreg if it is missing.
       if (!VRBase)
         VRBase = MRI->createVirtualRegister(TRC);
 
       // Create the extract_subreg machine instruction.
-      MachineInstrBuilder CopyMI =
-          BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
-                  TII->get(TargetOpcode::COPY), VRBase);
+      MachineInstrBuilder CopyMI = MachineInstrBuilder(
+          *MBB->getParent(),
+          TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), VRBase));
       if (Reg.isVirtual())
         CopyMI.addReg(Reg, 0, SubIdx);
       else
         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
     }
   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
              Opc == TargetOpcode::SUBREG_TO_REG) {
     SDValue N0 = Node->getOperand(0);
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
                                      DenseMap<SDValue, Register> &VRBaseMap) {
   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 
   // Create the new VReg in the destination class and emit a copy.
   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
   const TargetRegisterClass *DstRC =
     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
   Register NewVReg = MRI->createVirtualRegister(DstRC);
-  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
-    NewVReg).addReg(VReg);
+  TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), NewVReg, VReg);
 
   SDValue Op(Node, 0);
   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
   (void)isNew; // Silence compiler warning.
   assert(isNew && "Node emitted out of order - early");
 }
 
 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
case ISD::CopyToReg: {
     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
       SrcReg = R->getReg();
     else
       SrcReg = getVR(SrcVal, VRBaseMap);
 
     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
       break;
 
-    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
-            DestReg).addReg(SrcReg);
+    TII->buildCopy(*MBB, InsertPos, Node->getDebugLoc(), DestReg, SrcReg);
     break;
   }
   case ISD::CopyFromReg: {
     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
     EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
     break;
   }
   case ISD::EH_LABEL:

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

if (Pred.getSUnit()->CopyDstRC) {
       for (const SDep &Succ : SU->Succs) {
         if (Succ.isCtrl())
           continue; // ignore chain preds
         if (Succ.getReg()) {
           Reg = Succ.getReg();
           break;
         }
       }
-      BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
-        .addReg(VRI->second);
+      TII->buildCopy(*BB, InsertPos, DebugLoc(), Reg, VRI->second);
     } else {
       // Copy from physical register.
       assert(Pred.getReg() && "Unknown physical register!");
       Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
       (void)isNew; // Silence compiler warning.
       assert(isNew && "Node emitted out of order - early");
-      BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
-          .addReg(Pred.getReg());
+      TII->buildCopy(*BB, InsertPos, DebugLoc(), VRBase, Pred.getReg());
     }
     break;
   }
 }
 
 /// EmitSchedule - Emit the machine code in scheduled order. Return the new
 /// InsertPos and MachineBasicBlock that contains this insertion
 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

if (isFuncletEHPersonality(Pers)) {
     if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) {
       if (hasExceptionPointerOrCodeUser(CPI)) {
         // Get or create the virtual register to hold the pointer or code.  Mark
         // the live in physreg and copy into the vreg.
         MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
         assert(EHPhysReg && "target lacks exception pointer register");
         MBB->addLiveIn(EHPhysReg);
         unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
-        BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
-                TII->get(TargetOpcode::COPY), VReg)
-            .addReg(EHPhysReg, RegState::Kill);
+        TII->buildCopy(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), VReg,
+                       EHPhysReg, RegState::Kill);
       }
     }
     return true;
   }
 
   // Add a label to mark the beginning of the landing pad.  Deletion of the
   // landing pad can thus be detected via the MachineModuleInfo.
   MCSymbol *Label = MF->addLandingPad(MBB);

llvm/lib/CodeGen/SplitKit.cpp

if (FirstCopy) {
     Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
   } else {
     CopyMI->bundleWithPred();
   }
   return Def;
 }
 
 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
                                  LaneBitmask LaneMask, MachineBasicBlock &MBB,
-    MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
-  const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
+                                 MachineBasicBlock::iterator InsertBefore,
+                                 bool Late, unsigned RegIdx) {
   SlotIndexes &Indexes = *LIS.getSlotIndexes();
   if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
     // The full vreg is copied.
     MachineInstr *CopyMI =
-        BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
+        TII.buildCopy(MBB, InsertBefore, DebugLoc(), ToReg, FromReg);
     return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
   }
 
   // Only a subset of lanes needs to be copied. The following is a simple
   // heuristic to construct a sequence of COPYs. We could add a target
   // specific callback if this turns out to be suboptimal.
   LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx));
 

llvm/lib/CodeGen/SwiftErrorValueTracking.cpp

for (const auto *SwiftErrorVal : SwiftErrorVals) {
       const auto *TII = MF->getSubtarget().getInstrInfo();
 
       // If we don't need a phi create a copy to the upward exposed vreg.
       if (!needPHI) {
         assert(UpwardsUse);
         assert(!VRegs.empty() &&
                "No predecessors?  Is the Calling Convention correct?");
         Register DestReg = UUseVReg;
-        BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY),
-                DestReg)
-            .addReg(VRegs[0].second);
+        TII->buildCopy(*MBB, MBB->getFirstNonPHI(), DLoc, DestReg,
+                       VRegs[0].second);
         continue;
       }
 
       // We need a phi: if there is an upwards exposed use we already have a
       // destination virtual register number otherwise we generate a new one.
       auto &DL = MF->getDataLayout();
       auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
       Register PHIVReg =

llvm/lib/CodeGen/TailDuplicator.cpp

for (unsigned i = 0, e = NewMI.getNumOperands(); i != e; ++i) {
             // sub-register, we need to compose the sub-register indices.
             MO.setSubReg(
                 TRI->composeSubRegIndices(VI->second.SubReg, MO.getSubReg()));
           } else {
             // The direct replacement is not possible, due to failing register
             // class constraints. An explicit COPY is necessary. Create one
             // that can be reused.
             Register NewReg = MRI->createVirtualRegister(OrigRC);
-            BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(),
-                    TII->get(TargetOpcode::COPY), NewReg)
-                .addReg(VI->second.Reg, 0, VI->second.SubReg);
+            TII->buildCopy(*PredBB, NewMI, NewMI.getDebugLoc(), NewReg,
+                           VI->second.Reg, 0, VI->second.SubReg);
             LocalVRMap.erase(VI);
             LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
             MO.setReg(NewReg);
             // The composed VI.Reg:VI.SubReg is replaced with NewReg, which
             // is equivalent to the whole register Reg. Hence, Reg:subreg
             // is same as NewReg:subreg, so keep the sub-register index
             // unchanged.
           }

 }
 
 /// At the end of the block \p MBB generate COPY instructions between registers
 /// described by \p CopyInfos. Append resulting instructions to \p Copies.
 void TailDuplicator::appendCopies(MachineBasicBlock *MBB,
       SmallVectorImpl<std::pair<Register, RegSubRegPair>> &CopyInfos,
       SmallVectorImpl<MachineInstr*> &Copies) {
   MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
-  const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
   for (auto &CI : CopyInfos) {
-    auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
-                .addReg(CI.second.Reg, 0, CI.second.SubReg);
+    auto C = TII->buildCopy(*MBB, Loc, DebugLoc(), CI.first, CI.second.Reg, 0,
+                            CI.second.SubReg);
     Copies.push_back(C);
   }
 }
 
 /// Remove the specified dead machine basic block from the function, updating
 /// the CFG.
 void TailDuplicator::removeDeadBlock(
     MachineBasicBlock *MBB,

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

#ifndef NDEBUG
     // work. This should never occur because we are in SSA form.
     for (unsigned i = 0; i != MI->getNumOperands(); ++i)
       assert(i == DstIdx ||
              !MI->getOperand(i).isReg() ||
              MI->getOperand(i).getReg() != RegA);
 #endif
 
     // Emit a copy.
-    MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
-                                      TII->get(TargetOpcode::COPY), RegA);
+    MachineInstrBuilder MIB = MachineInstrBuilder(
+        *MI->getParent()->getParent(),
+        TII->buildCopy(*MI->getParent(), MI, MI->getDebugLoc(), RegA));
     // If this operand is folding a truncation, the truncation now moves to the
     // copy so that the register classes remain valid for the operands.
     MIB.addReg(RegB, 0, SubRegB);
     const TargetRegisterClass *RC = MRI->getRegClass(RegB);
     if (SubRegB) {
       if (RegA.isVirtual()) {
         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
                                              SubRegB) &&

llvm/lib/CodeGen/UnreachableBlockElim.cpp

while (phi != BB.end() && phi->isPHI()) {
               !Input.isUndef()) {
             MRI.replaceRegWith(OutputReg, InputReg);
           } else {
             // The input register to the PHI has a subregister or it can't be
             // constrained to the proper register class or it is undef:
             // insert a COPY instead of simply replacing the output
             // with the input.
             const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo();
-            BuildMI(BB, BB.getFirstNonPHI(), phi->getDebugLoc(),
-                    TII->get(TargetOpcode::COPY), OutputReg)
-                .addReg(InputReg, getRegState(Input), InputSub);
+            TII->buildCopy(BB, BB.getFirstNonPHI(), phi->getDebugLoc(),
+                           OutputReg, InputReg, getRegState(Input), InputSub);
           }
           phi++->eraseFromParent();
         }
         continue;
       }
 
       ++phi;
     }
   }
 
   F.RenumberBlocks();
 
   return (!DeadBlocks.empty() || ModifiedPHI);
 }