[RISCV] Remove Features from CPUInfo in RISCVTargetParser.

[craig.topper]

Summary

Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march starting with "rv64".

[fpetrogalli]

LGTM, thanks.

llvm/include/llvm/TargetParser/RISCVTargetParser.h

 //===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 namespace llvm {
 namespace RISCV {
 
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
 
 enum CPUKind : unsigned {
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
+#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
 #define TUNE_PROC(ENUM, NAME) CK_##ENUM,
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
-enum FeatureKind : unsigned {
-  FK_INVALID = 0,
-  FK_NONE = 1,
-  FK_64BIT = 1 << 2,
-};
-
 bool checkCPUKind(CPUKind Kind, bool IsRV64);
 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
 CPUKind parseCPUKind(StringRef CPU);
 CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
 StringRef getMArchFromMcpu(StringRef CPU);
 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
 
 } // namespace RISCV
 } // namespace llvm
 
 #endif

llvm/lib/TargetParser/RISCVTargetParser.cpp

 //===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a target parser to recognise hardware features
 // FOR RISC-V CPUS.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
 
 namespace llvm {
 namespace RISCV {
 
 struct CPUInfo {
   StringLiteral Name;
   CPUKind Kind;
-  unsigned Features;
   StringLiteral DefaultMarch;
-  bool is64Bit() const { return (Features & FK_64BIT); }
+  bool isInvalid() const { return DefaultMarch.empty(); }
+  bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
 };
 
 constexpr CPUInfo RISCVCPUInfo[] = {
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)                              \
-  {NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
+#define PROC(ENUM, NAME, DEFAULT_MARCH)                              \
+  {NAME, CK_##ENUM, DEFAULT_MARCH},
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 };
 
 bool checkCPUKind(CPUKind Kind, bool IsRV64) {
   if (Kind == CK_INVALID)
     return false;
   return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
 }
 
 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
   if (Kind == CK_INVALID)
     return false;
 #define TUNE_PROC(ENUM, NAME)                                                  \
   if (Kind == CK_##ENUM)                                                       \
     return true;
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
   return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
 }
 
 CPUKind parseCPUKind(StringRef CPU) {
   return llvm::StringSwitch<CPUKind>(CPU)
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
+#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
 }
 
 CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
   return llvm::StringSwitch<CPUKind>(TuneCPU)
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
+#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
 #define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
 }
 
 StringRef getMArchFromMcpu(StringRef CPU) {
   CPUKind Kind = parseCPUKind(CPU);
   return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
   }
 #define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 }
 
 // Get all features except standard extension feature
 bool getCPUFeaturesExceptStdExt(CPUKind Kind,
                                 std::vector<StringRef> &Features) {
-  unsigned CPUFeatures = RISCVCPUInfo[static_cast<unsigned>(Kind)].Features;
+  const CPUInfo &Info = RISCVCPUInfo[static_cast<unsigned>(Kind)];
 
-  if (CPUFeatures == FK_INVALID)
+  if (Info.isInvalid())
     return false;
 
-  if (CPUFeatures & FK_64BIT)
+  if (Info.is64Bit())
     Features.push_back("+64bit");
   else
     Features.push_back("-64bit");
 
   return true;
 }
 
 } // namespace RISCV
 } // namespace llvm

llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISCV CPUs -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static std::string getMArch(int XLen, const Record &Rec) {
   if (!ISAInfo)
     report_fatal_error("Invalid features");
 
   // RISCVISAInfo::toString will generate a march string with all the extensions
   // we have added to it.
   return (*ISAInfo)->toString();
 }
 
-static std::string getEnumFeatures(int XLen) {
-  return XLen == 64 ? "FK_64BIT" : "FK_NONE";
-}
-
 void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
   OS << "#ifndef PROC\n"
-     << "#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)\n"
+     << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
      << "#endif\n\n";
 
-  OS << "PROC(INVALID, {\"invalid\"}, FK_INVALID, {\"\"})\n";
+  OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n";
   // Iterate on all definition records.
   for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
     int XLen = getXLen(*Rec);
     std::string MArch = Rec->getValueAsString("DefaultMarch").str();
 
     // Compute MArch from features if we don't specify it.
     if (MArch.empty())
       MArch = getMArch(XLen, *Rec);
 
     OS << "PROC(" << Rec->getName() << ", "
-       << "{\"" << Rec->getValueAsString("Name") << "\"},"
-       << getEnumFeatures(XLen) << ", "
+       << "{\"" << Rec->getValueAsString("Name") << "\"}, "
        << "{\"" << MArch << "\"})\n";
   }
   OS << "\n#undef PROC\n";
   OS << "\n";
   OS << "#ifndef TUNE_PROC\n"
      << "#define TUNE_PROC(ENUM, NAME)\n"
      << "#endif\n\n";
   OS << "TUNE_PROC(GENERIC, \"generic\")\n";