[AArch64] Armv9-A implies FP16

[dmgreen]

Summary

As Armv9-a implies SVE2 it implies SVE (added in D141411) and so it should also imply FP16, which this patch adds. This helps get the target features correct when using target("arch=armv9-a") attributes.

There is also an adjustment to AssertSameExtensionFlags in this patch to make it print cpu names, useful when the TargetParser unit tests are run through lit to distinguish which cpu is failing.

[tmatheson]

LGTM

clang/test/CodeGen/aarch64-targetattr-arch.c

 // RUN: %clang_cc1 -triple aarch64-eabi -target-feature +v8a -verify -DHAS8 -S %s -o -
 // RUN: %clang_cc1 -triple aarch64-eabi -target-feature +v8.1a -verify -DHAS81 -S %s -o -
 // RUN: %clang_cc1 -triple aarch64-eabi -target-feature +v9a -verify -DHAS9 -S %s -o -
 // REQUIRES: aarch64-registered-target
 
 #ifdef HAS9
 // expected-no-diagnostics
 #endif
 
 #include <arm_acle.h>
+#include <arm_fp16.h>
 #include <arm_sve.h>
 
 __attribute__((target("arch=armv8.1-a")))
 int test_crc_attr()
 {
   return __crc32cd(1, 1);
 }
 
 __attribute__((target("arch=armv9-a")))
 svint8_t test_svadd_attr(svbool_t pg, svint8_t op1, svint8_t op2)
 {
   return svadd_s8_z(pg, op1, op2);
 }
 
+__attribute__((target("arch=armv9-a")))
+float16_t test_fp16_on_v9(float16_t x, float16_t y)
+{
+  return vabdh_f16(x, y);
+}
+
 void test_errors()
 {
 #ifdef HAS8
 // expected-error@+2{{always_inline function '__crc32cd' requires target feature 'crc'}}
 #endif
   __crc32cd(1, 1);
 #if defined(HAS8) || defined(HAS81)
 // expected-error@+2{{'svundef_s8' needs target feature sve}}
 #endif
   svundef_s8();
 }

clang/test/CodeGen/aarch64-targetattr.c

 // CHECK-LABEL: @nosimd() #17
 __attribute__((target("no-simd")))
 void nosimd() {}
 
 // CHECK: attributes #0 = { {{.*}} "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #1 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #2 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #3 = { {{.*}} "target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
-// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+i8mm,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" }
+// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" }
 // CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
 // CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
 // CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
 // CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+crc,+crypto,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+spe,+ssbs" "tune-cpu"="cortex-a710" }
 // CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
 // CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+bf16,+crc,+crypto,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+neon,+rand,+ras,+rcpc,+rdm,+spe,+ssbs,+sve,+sve2" }
 // CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+bf16,+crc,+crypto,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+neon,+rand,+ras,+rcpc,+rdm,+spe,+ssbs,-sve" }
 // CHECK: attributes #12 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
 // CHECK: attributes #13 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
 // CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
 // CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+crc,+crypto,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
 // CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" {{.*}} "target-features"="+aes,+bf16,+crc,+crypto,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
 // CHECK: attributes #17 = { {{.*}} "target-features"="-neon" }

llvm/include/llvm/TargetParser/AArch64TargetParser.h

 inline constexpr ArchInfo ARMV8_3A  = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts | AArch64::AEK_RCPC)};
 inline constexpr ArchInfo ARMV8_4A  = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts | AArch64::AEK_DOTPROD)};
 inline constexpr ArchInfo ARMV8_5A  = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
 constexpr unsigned BaseNoCrypto = ARMV8_5A.DefaultExts ^ AArch64::AEK_CRYPTO; // 8.6 onwards has no AEK_CRYPTO
 inline constexpr ArchInfo ARMV8_6A  = { VersionTuple{8, 6}, AProfile, "armv8.6-a", "+v8.6a", (BaseNoCrypto | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)};
 inline constexpr ArchInfo ARMV8_7A  = { VersionTuple{8, 7}, AProfile, "armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
 inline constexpr ArchInfo ARMV8_8A  = { VersionTuple{8, 8}, AProfile, "armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::AEK_MOPS | AArch64::AEK_HBC)};
 inline constexpr ArchInfo ARMV8_9A  = { VersionTuple{8, 9}, AProfile, "armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts)};
-inline constexpr ArchInfo ARMV9A    = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (BaseNoCrypto | AArch64::AEK_SVE | AArch64::AEK_SVE2)};
+inline constexpr ArchInfo ARMV9A    = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (BaseNoCrypto | AArch64::AEK_FP16 | AArch64::AEK_SVE | AArch64::AEK_SVE2)};
 inline constexpr ArchInfo ARMV9_1A  = { VersionTuple{9, 1}, AProfile, "armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | AArch64::AEK_BF16 | AArch64::AEK_I8MM)};
 inline constexpr ArchInfo ARMV9_2A  = { VersionTuple{9, 2}, AProfile, "armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
 inline constexpr ArchInfo ARMV9_3A  = { VersionTuple{9, 3}, AProfile, "armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | AArch64::AEK_MOPS | AArch64::AEK_HBC)};
 inline constexpr ArchInfo ARMV9_4A  = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts)};
 // For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
 inline constexpr ArchInfo ARMV8R    = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", ((BaseNoCrypto ^ AArch64::AEK_LSE) | AArch64::AEK_SSBS | AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_SB), };
 // clang-format on
 

 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
 
 bool isX18ReservedByDefault(const Triple &TT);
 uint64_t getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
 
 } // namespace AArch64
 } // namespace llvm
 
-#endif
+#endif
 

llvm/unittests/TargetParser/TargetParserTest.cpp

Features.erase(std::remove_if(Features.begin(), Features.end(),
                                 [](StringRef extension) {
                                   return extension.startswith("-");
                                 }),
                  Features.end());
 
   return llvm::join(Features, ", ");
 }
 
-template <ARM::ISAKind ISAKind>
-testing::AssertionResult
-AssertSameExtensionFlags(const char *m_expr, const char *n_expr,
-                         uint64_t ExpectedFlags, uint64_t GotFlags) {
+template <ARM::ISAKind ISAKind> struct AssertSameExtensionFlags {
+  AssertSameExtensionFlags(StringRef CPUName) : CPUName(CPUName) {}
+
+  testing::AssertionResult operator()(const char *m_expr, const char *n_expr,
+                                      uint64_t ExpectedFlags,
+                                      uint64_t GotFlags) {
     if (ExpectedFlags == GotFlags)
       return testing::AssertionSuccess();
 
     return testing::AssertionFailure() << llvm::formatv(
+               "CPU: {4}\n"
                "Expected extension flags: {0} ({1:x})\n"
                "     Got extension flags: {2} ({3:x})\n",
                FormatExtensionFlags<ISAKind>(ExpectedFlags), ExpectedFlags,
-             FormatExtensionFlags<ISAKind>(GotFlags), GotFlags);
+               FormatExtensionFlags<ISAKind>(GotFlags), GotFlags, CPUName);
   }
 
+private:
+  StringRef CPUName;
+};
+
 struct ARMCPUTestParams {
   ARMCPUTestParams(StringRef CPUName, StringRef ExpectedArch,
                    StringRef ExpectedFPU, uint64_t ExpectedFlags,
                    StringRef CPUAttr)
       : CPUName(CPUName), ExpectedArch(ExpectedArch), ExpectedFPU(ExpectedFPU),
         ExpectedFlags(ExpectedFlags), CPUAttr(CPUAttr) {}
 
   friend std::ostream &operator<<(std::ostream &os,
TEST_P(ARMCPUTestFixture, ARMCPUTests) {
 
   ARM::ArchKind AK = ARM::parseCPUArch(params.CPUName);
   EXPECT_EQ(params.ExpectedArch, ARM::getArchName(AK));
 
   unsigned FPUKind = ARM::getDefaultFPU(params.CPUName, AK);
   EXPECT_EQ(params.ExpectedFPU, ARM::getFPUName(FPUKind));
 
   uint64_t default_extensions = ARM::getDefaultExtensions(params.CPUName, AK);
-  EXPECT_PRED_FORMAT2(AssertSameExtensionFlags<ARM::ISAKind::ARM>,
-                      params.ExpectedFlags, default_extensions);
+  EXPECT_PRED_FORMAT2(
+      AssertSameExtensionFlags<ARM::ISAKind::ARM>(params.CPUName),
 
   EXPECT_EQ(params.CPUAttr, ARM::getCPUAttr(AK));
 }
 
 // Note that we include ARM::AEK_NONE even when there are other extensions
 // we expect. This is because the default extensions for a CPU are the sum
 // of the default extensions for its architecture and for the CPU.
 // So if a CPU has no extra extensions, it adds AEK_NONE.

 TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
   ARMCPUTestParams params = GetParam();
 
   const AArch64::ArchInfo &AI = AArch64::parseCpu(params.CPUName).Arch;
   EXPECT_EQ(params.ExpectedArch, AI.Name);
 
   uint64_t default_extensions =
       AArch64::getDefaultExtensions(params.CPUName, AI);
-  EXPECT_PRED_FORMAT2(AssertSameExtensionFlags<ARM::ISAKind::AARCH64>,
-                      params.ExpectedFlags, default_extensions);
+  EXPECT_PRED_FORMAT2(
+      AssertSameExtensionFlags<ARM::ISAKind::AARCH64>(params.CPUName),
 }
 
 INSTANTIATE_TEST_SUITE_P(
     AArch64CPUTests, AArch64CPUTestFixture,
     ::testing::Values(
         ARMCPUTestParams("invalid", "invalid", "invalid", AArch64::AEK_NONE,
                          ""),
         ARMCPUTestParams("generic", "invalid", "none", AArch64::AEK_NONE, ""),
::testing::Values(
                          AArch64::AEK_CRC | AArch64::AEK_FP |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS |
                              AArch64::AEK_LSE | AArch64::AEK_RDM |
                              AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
                              AArch64::AEK_BF16 | AArch64::AEK_I8MM |
                              AArch64::AEK_SVE | AArch64::AEK_SVE2 |
                              AArch64::AEK_SVE2BITPERM | AArch64::AEK_PAUTH |
                              AArch64::AEK_MTE | AArch64::AEK_SSBS |
-                             AArch64::AEK_FP16FML | AArch64::AEK_SB,
+                             AArch64::AEK_FP16 | AArch64::AEK_FP16FML |
+                             AArch64::AEK_SB,
                          "9-A"),
         ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
                              AArch64::AEK_FP | AArch64::AEK_SIMD,
                          "8-A"),
         ARMCPUTestParams("cortex-a65", "armv8.2-a", "crypto-neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
                              AArch64::AEK_DOTPROD | AArch64::AEK_FP |
::testing::Values(
                              AArch64::AEK_CRYPTO | AArch64::AEK_FP |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS |
                              AArch64::AEK_LSE | AArch64::AEK_RDM |
                              AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
                              AArch64::AEK_RCPC | AArch64::AEK_SSBS |
                              AArch64::AEK_PROFILE | AArch64::AEK_FLAGM |
                              AArch64::AEK_PAUTH | AArch64::AEK_FP16FML,
                          "8.2-A"),
-        ARMCPUTestParams("cortex-a710", "armv9-a", "neon-fp-armv8",
-                         AArch64::AEK_CRC | AArch64::AEK_FP |
-                             AArch64::AEK_SIMD | AArch64::AEK_RAS |
-                             AArch64::AEK_LSE | AArch64::AEK_RDM |
-                             AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
-                             AArch64::AEK_MTE | AArch64::AEK_FP16FML |
-                             AArch64::AEK_SVE | AArch64::AEK_SVE2 |
-                             AArch64::AEK_SVE2BITPERM | AArch64::AEK_PAUTH |
-                             AArch64::AEK_FLAGM | AArch64::AEK_SB |
-                             AArch64::AEK_I8MM | AArch64::AEK_BF16,
-                         "9-A"),
+        ARMCPUTestParams(
+            "cortex-a710", "armv9-a", "neon-fp-armv8",
+            AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD |
+                AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM |
+                AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_MTE |
+                AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_SVE |
+                AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
+                AArch64::AEK_PAUTH | AArch64::AEK_FLAGM | AArch64::AEK_SB |
         ARMCPUTestParams("cortex-a715", "armv9-a", "neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_BF16 |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS |
                              AArch64::AEK_LSE | AArch64::AEK_RDM |
                              AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
                              AArch64::AEK_MTE | AArch64::AEK_PAUTH |
                              AArch64::AEK_SVE | AArch64::AEK_SVE2 |
                              AArch64::AEK_SVE2BITPERM | AArch64::AEK_SSBS |
::testing::Values(
                          AArch64::AEK_CRC | AArch64::AEK_FP |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS |
                              AArch64::AEK_LSE | AArch64::AEK_RDM |
                              AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
                              AArch64::AEK_MTE | AArch64::AEK_PAUTH |
                              AArch64::AEK_I8MM | AArch64::AEK_BF16 |
                              AArch64::AEK_SVE | AArch64::AEK_SVE2 |
                              AArch64::AEK_SVE2BITPERM | AArch64::AEK_SSBS |
-                             AArch64::AEK_SB | AArch64::AEK_FP16FML,
+                             AArch64::AEK_SB | AArch64::AEK_FP16 |
+                             AArch64::AEK_FP16FML,
                          "9-A"),
         ARMCPUTestParams("cortex-x3", "armv9-a", "neon-fp-armv8",
                          AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_BF16 |
                              AArch64::AEK_SIMD | AArch64::AEK_RAS |
                              AArch64::AEK_LSE | AArch64::AEK_RDM |
                              AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
                              AArch64::AEK_MTE | AArch64::AEK_PAUTH |
                              AArch64::AEK_SVE | AArch64::AEK_SVE2 |