[DAG] Peek through ZEXT/TRUNC in foldAddSubMasked1

[deadalnix]

Summary

Fix a regression in D141883

Depends on D141883

[lebedev.ri]

Looks fine to me, but this one could use a second opinion.

[deadalnix]

If you are not sure, I'm not going to land this right away to give anyone who has concern the opportunity to comment.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
   return SDValue();
 }
 
 /// Given the operands of an add/sub operation, see if the 2nd operand is a
 /// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
 /// the opcode and bypass the mask operation.
 static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
                                  SelectionDAG &DAG, const SDLoc &DL) {
+  if (N1.getOpcode() == ISD::ZERO_EXTEND)
+    N1 = N1.getOperand(0);
+
   if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
     return SDValue();
 
   EVT VT = N0.getValueType();
-  if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
+  SDValue N10 = N1.getOperand(0);
+  if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE)
+    N10 = N10.getOperand(0);
+
+  if (N10.getValueType() != VT)
+    return SDValue();
+
+  if (DAG.ComputeNumSignBits(N10) != VT.getScalarSizeInBits())
     return SDValue();
 
   // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
   // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
-  return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
+  return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N10);
 }
 
 /// Helper for doing combines based on N0 and N1 being added to each other.
 SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
                                           SDNode *LocReference) {
   EVT VT = N0.getValueType();
   SDLoc DL(LocReference);
 

llvm/test/CodeGen/X86/known-signbits-vector.ll

 ; X86-NEXT:    negl %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: signbits_cmpsd:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vcmpeqsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vmovq %xmm0, %rax
-; X64-NEXT:    andl $1, %eax
-; X64-NEXT:    negq %rax
 ; X64-NEXT:    retq
   %3 = fcmp oeq double %0, %1
   %4 = sext i1 %3 to i64
   ret i64 %4
 }
 
 define i64 @signbits_cmpsd_int(<2 x double> %0, <2 x double> %1) {
 ; X86-LABEL: signbits_cmpsd_int: