[X86] `canonicalizeShuffleWithBinOps()`: support `VS[HR][LA]I` opcodes, binary shuffles part

[lebedev.ri]

Summary

Builds upon D141806, and adds support for binary shuffles too.

[lebedev.ri]

Rebased.

llvm/lib/Target/X86/X86ISelLowering.cpp

static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
   case X86ISD::UNPCKH:
   case X86ISD::UNPCKL: {
     if (N->isOnlyUserOf(N.getOperand(0).getNode()) &&
         N->isOnlyUserOf(N.getOperand(1).getNode())) {
       std::array<SDValue, 2> OpsOfShuf;
       for (auto I : zip(N->ops(), OpsOfShuf))
         std::get<1>(I) = peekThroughOneUseBitcasts(std::get<0>(I));
       unsigned SrcOpcode = OpsOfShuf[0].getOpcode();
-      if (TLI.isBinOp(SrcOpcode) && OpsOfShuf[1].getOpcode() == SrcOpcode &&
+      if (isBinOp(SrcOpcode, TLI) && OpsOfShuf[1].getOpcode() == SrcOpcode &&
           IsSafeToMoveShuffle(OpsOfShuf[0], SrcOpcode) &&
           IsSafeToMoveShuffle(OpsOfShuf[1], SrcOpcode)) {
         std::array<std::array<SDValue, 2>, 2> NthOpsOfShufOps;
         for (unsigned OpIdx : seq_inclusive(0, 1)) {
           for (unsigned ShufOpIdx : seq_inclusive(0, 1)) {
             NthOpsOfShufOps[OpIdx][ShufOpIdx] = peekThroughOneUseBitcasts(
                 OpsOfShuf[ShufOpIdx].getOperand(OpIdx));
           }
         }
         // Ensure the total number of shuffles doesn't increase by folding this
         // shuffle through to the source ops.
-        if (any_of(enumerate(NthOpsOfShufOps),
+        if ((any_of(enumerate(NthOpsOfShufOps),
                     [&](auto I) {
                       return AreAllOperandMergeableWithShuffle(
                           SrcOpcode, I.index(), I.value());
                     }) ||
+             all_of(enumerate(NthOpsOfShufOps),
+                    [&](auto I) {
+                      return AreAnyOperandMergeableWithShuffle(
+                          SrcOpcode, I.index(), I.value());
+                    })) &&
             all_of(enumerate(NthOpsOfShufOps), [&](auto I) {
-              return AreAnyOperandMergeableWithShuffle(SrcOpcode, I.index(),
-                                                       I.value());
+              return !shouldIgnoreSpecificOperandForOpcode(SrcOpcode,
+                                                           I.index()) ||
+                     all_equal(I.value());
             })) {
           EVT OpVT = OpsOfShuf[0].getValueType();
           std::array<SDValue, 2> NewOps;
           for (auto I : enumerate(zip(NthOpsOfShufOps, NewOps))) {
+            unsigned OpNo = I.index();
             MutableArrayRef<SDValue> NthOpsOfOpsOfShufOp =
                 std::get<0>(I.value());
             SDValue &NewOp = std::get<1>(I.value());
+            if (shouldIgnoreSpecificOperandForOpcode(SrcOpcode, OpNo)) {
+              assert(all_equal(NthOpsOfOpsOfShufOp) &&
+                     "Expected to see identical values of ignored operand.");
+              NewOp = NthOpsOfOpsOfShufOp[0];
+              continue;
+            }
             for (SDValue &V : NthOpsOfOpsOfShufOp)
               V = DAG.getBitcast(ShuffleVT, V);
             if (N.getNumOperands() == 3)
               NewOp = DAG.getNode(Opc, DL, ShuffleVT, NthOpsOfOpsOfShufOp[0],
                                   NthOpsOfOpsOfShufOp[1], N.getOperand(2));
             else
               NewOp = DAG.getNode(Opc, DL, ShuffleVT, NthOpsOfOpsOfShufOp[0],
                                   NthOpsOfOpsOfShufOp[1]);

llvm/test/CodeGen/X86/blend-of-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2,X64,X64-SSE2
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2,X64,X64-AVX2
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2,X86,X86-SSE2
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2,X86,X86-AVX2
 
 ;------------------------------ 32-bit shuffles -------------------------------;
 
 define <4 x i32> @shuffle_i32_of_shl_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; SSE2-LABEL: shuffle_i32_of_shl_i16:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psllw $15, %xmm0
-; SSE2-NEXT:    psllw $15, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psllw $15, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i32_of_shl_i16:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpsllw $15, %xmm0, %xmm0
-; AVX2-NEXT:    vpsllw $15, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
+; AVX2-NEXT:    vpsllw $15, %xmm0, %xmm0
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 15)
   %i2 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %y, i32 15)
   %i3 = bitcast <8 x i16> %i1 to <4 x i32>
   %i4 = bitcast <8 x i16> %i2 to <4 x i32>
   %i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
   ret <4 x i32> %i5
 }
 define <4 x i32> @shuffle_i32_of_lshr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; SSE2-LABEL: shuffle_i32_of_lshr_i16:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrlw $15, %xmm0
-; SSE2-NEXT:    psrlw $15, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrlw $15, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i32_of_lshr_i16:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpsrlw $15, %xmm0, %xmm0
-; AVX2-NEXT:    vpsrlw $15, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
+; AVX2-NEXT:    vpsrlw $15, %xmm0, %xmm0
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %x, i32 15)
   %i2 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %y, i32 15)
   %i3 = bitcast <8 x i16> %i1 to <4 x i32>
   %i4 = bitcast <8 x i16> %i2 to <4 x i32>
   %i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
   ret <4 x i32> %i5
 }
 define <4 x i32> @shuffle_i32_of_ashr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; SSE2-LABEL: shuffle_i32_of_ashr_i16:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psraw $15, %xmm0
-; SSE2-NEXT:    psraw $15, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psraw $15, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i32_of_ashr_i16:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpsraw $15, %xmm0, %xmm0
-; AVX2-NEXT:    vpsraw $15, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
+; AVX2-NEXT:    vpsraw $15, %xmm0, %xmm0
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %x, i32 15)
   %i2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %y, i32 15)
   %i3 = bitcast <8 x i16> %i1 to <4 x i32>
   %i4 = bitcast <8 x i16> %i2 to <4 x i32>
   %i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
   ret <4 x i32> %i5
 }
 
 define <4 x i32> @shuffle_i32_of_shl_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; SSE2-LABEL: shuffle_i32_of_shl_i32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pslld $31, %xmm0
-; SSE2-NEXT:    pslld $31, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    pslld $31, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i32_of_shl_i32:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpslld $31, %xmm0, %xmm0
-; AVX2-NEXT:    vpslld $31, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
+; AVX2-NEXT:    vpslld $31, %xmm0, %xmm0
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %x, i32 31)
   %i2 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %y, i32 31)
   %i3 = shufflevector <4 x i32> %i1, <4 x i32> %i2, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
   ret <4 x i32> %i3
 }
 define <4 x i32> @shuffle_i32_of_lshr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; SSE2-LABEL: shuffle_i32_of_lshr_i32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrld $31, %xmm0
-; SSE2-NEXT:    psrld $31, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrld $31, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i32_of_lshr_i32:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpsrld $31, %xmm0, %xmm0
-; AVX2-NEXT:    vpsrld $31, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
+; AVX2-NEXT:    vpsrld $31, %xmm0, %xmm0
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %x, i32 31)
   %i2 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %y, i32 31)
   %i3 = shufflevector <4 x i32> %i1, <4 x i32> %i2, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
   ret <4 x i32> %i3
 }
 define <4 x i32> @shuffle_i32_of_ashr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; SSE2-LABEL: shuffle_i32_of_ashr_i32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrad $31, %xmm0
-; SSE2-NEXT:    psrad $31, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i32_of_ashr_i32:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpsrad $31, %xmm0, %xmm0
-; AVX2-NEXT:    vpsrad $31, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
+; AVX2-NEXT:    vpsrad $31, %xmm0, %xmm0
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %x, i32 31)
   %i2 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %y, i32 31)
   %i3 = shufflevector <4 x i32> %i1, <4 x i32> %i2, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
   ret <4 x i32> %i3
 }
 
 define <4 x i32> @shuffle_i32_of_shl_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; X86-AVX2-NEXT:    retl
   ret <4 x i32> %i5
 }
 
 ;------------------------------ 64-bit shuffles -------------------------------;
 
 define <2 x i64> @shuffle_i64_of_shl_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_shl_i16:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psllw $15, %xmm0
-; SSE2-NEXT:    psllw $15, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psllw $15, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_shl_i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsllw $15, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsllw $15, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 15)
   %i2 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %y, i32 15)
   %i3 = bitcast <8 x i16> %i1 to <2 x i64>
   %i4 = bitcast <8 x i16> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 define <2 x i64> @shuffle_i64_of_lshr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_lshr_i16:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrlw $15, %xmm0
-; SSE2-NEXT:    psrlw $15, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrlw $15, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_lshr_i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsrlw $15, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsrlw $15, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %x, i32 15)
   %i2 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %y, i32 15)
   %i3 = bitcast <8 x i16> %i1 to <2 x i64>
   %i4 = bitcast <8 x i16> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 define <2 x i64> @shuffle_i64_of_ashr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_ashr_i16:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psraw $15, %xmm0
-; SSE2-NEXT:    psraw $15, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psraw $15, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_ashr_i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsraw $15, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsraw $15, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %x, i32 15)
   %i2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %y, i32 15)
   %i3 = bitcast <8 x i16> %i1 to <2 x i64>
   %i4 = bitcast <8 x i16> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 
 define <2 x i64> @shuffle_i64_of_shl_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_shl_i32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    pslld $31, %xmm0
-; SSE2-NEXT:    pslld $31, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    pslld $31, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_shl_i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpslld $31, %xmm0, %xmm0
 ; AVX2-NEXT:    vpslld $31, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %x, i32 31)
   %i2 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %y, i32 31)
   %i3 = bitcast <4 x i32> %i1 to <2 x i64>
   %i4 = bitcast <4 x i32> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 define <2 x i64> @shuffle_i64_of_lshr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_lshr_i32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrld $31, %xmm0
-; SSE2-NEXT:    psrld $31, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrld $31, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_lshr_i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsrld $31, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsrld $31, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %x, i32 31)
   %i2 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %y, i32 31)
   %i3 = bitcast <4 x i32> %i1 to <2 x i64>
   %i4 = bitcast <4 x i32> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 define <2 x i64> @shuffle_i64_of_ashr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_ashr_i32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrad $31, %xmm0
-; SSE2-NEXT:    psrad $31, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrad $31, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_ashr_i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsrad $31, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsrad $31, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %x, i32 31)
   %i2 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %y, i32 31)
   %i3 = bitcast <4 x i32> %i1 to <2 x i64>
   %i4 = bitcast <4 x i32> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 
 define <2 x i64> @shuffle_i64_of_shl_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_shl_i64:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psllq $63, %xmm0
-; SSE2-NEXT:    psllq $63, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psllq $63, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_shl_i64:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsllq $63, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}
   %i1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %x, i32 63)
   %i2 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %y, i32 63)
   %i3 = bitcast <2 x i64> %i1 to <2 x i64>
   %i4 = bitcast <2 x i64> %i2 to <2 x i64>
   %i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %i5
 }
 define <2 x i64> @shuffle_i64_of_lshr_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; SSE2-LABEL: shuffle_i64_of_lshr_i64:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    psrlq $63, %xmm0
-; SSE2-NEXT:    psrlq $63, %xmm1
 ; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
-; SSE2-NEXT:    movaps %xmm1, %xmm0
+; SSE2-NEXT:    psrlq $63, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    ret{{[l|q]}}
 ;
 ; AVX2-LABEL: shuffle_i64_of_lshr_i64:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpsrlq $63, %xmm0, %xmm0
 ; AVX2-NEXT:    vpsrlq $63, %xmm1, %xmm1
 ; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
 ; AVX2-NEXT:    ret{{[l|q]}}

llvm/test/CodeGen/X86/concat-cast.ll

; AVX-NEXT:    retq
   store <2 x float> %s1, ptr %p
   %r = shufflevector <2 x float> %s0, <2 x float> %s1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %r
 }
 
 define <4 x float> @PR45794(<2 x i64> %x, <2 x i64> %y) {
 ; SSE-LABEL: PR45794:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    psrad $16, %xmm0
-; SSE-NEXT:    psrad $16, %xmm1
 ; SSE-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; SSE-NEXT:    psrad $16, %xmm0
 ; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: PR45794:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vpsrad $16, %xmm0, %xmm0
-; AVX1-NEXT:    vpsrad $16, %xmm1, %xmm1
 ; AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; AVX1-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; AVX1-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: PR45794:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpsrad $16, %xmm0, %xmm0
-; AVX2-NEXT:    vpsrad $16, %xmm1, %xmm1
 ; AVX2-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; AVX2-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; AVX2-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512F-LABEL: PR45794:
 ; AVX512F:       # %bb.0:
 ; AVX512F-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
 ; AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; AVX512F-NEXT:    vpsraq $48, %zmm0, %zmm0

llvm/test/CodeGen/X86/known-signbits-vector.ll

; X64-AVX2-NEXT:    retq
   ret <4 x double> %2
 }
 
 ; PR45794
 define <4 x float> @signbits_ashr_sitofp_1(<4 x i64> %a0) nounwind {
 ; X86-LABEL: signbits_ashr_sitofp_1:
 ; X86:       # %bb.0:
 ; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; X86-NEXT:    vpsrad $16, %xmm1, %xmm1
-; X86-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; X86-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; X86-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-AVX1-LABEL: signbits_ashr_sitofp_1:
 ; X64-AVX1:       # %bb.0:
 ; X64-AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; X64-AVX1-NEXT:    vpsrad $16, %xmm1, %xmm1
-; X64-AVX1-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; X64-AVX1-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
+; X64-AVX1-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; X64-AVX1-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X64-AVX1-NEXT:    vzeroupper
 ; X64-AVX1-NEXT:    retq
 ;
 ; X64-AVX2-LABEL: signbits_ashr_sitofp_1:
 ; X64-AVX2:       # %bb.0:
 ; X64-AVX2-NEXT:    vpsrad $16, %ymm0, %ymm0
 ; X64-AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1