[RISCV][NFC] Use uncompressInst to relax instructions

[• pcwang-thead]

Summary

As the TODO said, we can just use generated uncompressInst to
relax instructions.

[kito-cheng]

LGTM with a nit, seems like it also improve the debug info (loc).

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

178–180

nit: Assert check return value of uncompressInst.

[• pcwang-thead]

Address comment.

[craig.topper]

Can we do this in a way that doesn't replicate the uncompressInst function in two different cpp files.

[kito-cheng]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

179

Another nit, you need add (void)Success; to suppress unused variable warning for disable assertion build.

[• pcwang-thead]

Address comments.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

178–180

Where is RISCRVC defined?

[• pcwang-thead]

In D141834#4057500, @craig.topper wrote:

Can we do this in a way that doesn't replicate the uncompressInst function in two different cpp files.

Thanks, I have thought about it too yesterday. :)
So I moved compressInst/uncompressInst to RISCVBaseInfo (D141897) and removed all other duplicated code.
Additionally, because there are redefinition errors of RISCVValidateMCOperand, so I added postfix to these validators (D141896).

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

178–180

Never mind I didn’t see the other patch

[asb]

LGTM, thanks for doing this cleanup.

[craig.topper]

I've posted https://reviews.llvm.org/D141951 to removed the uncompressInst's dependency on MCRegisterInfo which should simplify this patch.

[• pcwang-thead]

Rebase.

[• pcwang-thead]

In D141834#4059646, @craig.topper wrote:

I've posted https://reviews.llvm.org/D141951 to removed the uncompressInst's dependency on MCRegisterInfo which should simplify this patch.

Thanks! It's much more concise now. :-)

[craig.topper]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

case RISCV::fixup_riscv_rvc_jump:
     // For compressed jump instructions the immediate must be
     // in the range [-2048, 2046].
     return Offset > 2046 || Offset < -2048;
   }
 }
 
 void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
                                        const MCSubtargetInfo &STI) const {
-  // TODO: replace this with call to auto generated uncompressinstr() function.
   MCInst Res;
   switch (Inst.getOpcode()) {
   default:
     llvm_unreachable("Opcode not expected!");
   case RISCV::C_BEQZ:
-    // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
-    Res.setOpcode(RISCV::BEQ);
-    Res.addOperand(Inst.getOperand(0));
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(1));
-    break;
   case RISCV::C_BNEZ:
-    // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
-    Res.setOpcode(RISCV::BNE);
-    Res.addOperand(Inst.getOperand(0));
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(1));
-    break;
   case RISCV::C_J:
-    // c.j $imm -> jal X0, $imm.
-    Res.setOpcode(RISCV::JAL);
-    Res.addOperand(MCOperand::createReg(RISCV::X0));
-    Res.addOperand(Inst.getOperand(0));
-    break;
   case RISCV::C_JAL:
-    // c.jal $imm -> jal X1, $imm.
-    Res.setOpcode(RISCV::JAL);
-    Res.addOperand(MCOperand::createReg(RISCV::X1));
-    Res.addOperand(Inst.getOperand(0));
+    bool Success = RISCVRVC::uncompress(Res, Inst, STI);
+    assert(Success && "Can't uncompress instruction");
+    (void)Success;
     break;
   }
   Inst = std::move(Res);
 }
 
 bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,
                                          MCAsmLayout &Layout,
                                          bool &WasRelaxed) const {