[X86] Prefer fpext(splat(X)) to splat(fpext(x)).

[FreddyYe]

Summary

This patch is to fix regression of D122875. X86 has fpext instructions
supporting rmb form, which takes advantage of fpext(fplat(X)) than
splat(fpext(X)).

[FreddyYe]

This patch is to fix regression below: https://gcc.godbolt.org/z/v3nnbKP1j

[skan]

In D141657#4050436, @FreddyYe wrote:

This patch is to fix regression below: https://reviews.llvm.org/D141657

You are using the link of this revision...

[pengfei]

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

1

Pre-commit the test to show the problem?

[RKSimon]

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

6

remove the global constant and use a function argument:

define <4 x double> @prefer(float* %p) {
entry:
  %0 = load float, float* %p, align 4

[FreddyYe]

Address comments. THX for review!

[skan]

llvm/lib/Target/X86/X86ISelLowering.cpp

6017

Why not return Opc != ISD::FP_EXTEND?

[FreddyYe]

Address comments. THX for review!

[FreddyYe]

Rebase pre-commit test.

[skan]

LGTM

[RKSimon]

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

2

Please can you add sse/avx1/avx2 test coverage as well just to ensure non-avx512 targets prefer this as well?

[lebedev.ri]

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

4

While there, please add i8/i16/i32/i64/double/half tests

[pengfei]

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

10

Change to ptr.

[skan]

Minor suggestion: could you add more comments in the description? The title is kind of abstract.

[RKSimon]

@FreddyYe I've added additional tests - please can you rebase?

[FreddyYe]

Rebase new pre-commit tests.

[lebedev.ri]

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

6

Precommit please

[FreddyYe]

Rebase FP16 tests.

[RKSimon]

LGTM

llvm/lib/Target/X86/X86ISelLowering.h

public:
 
     bool hasBitTest(SDValue X, SDValue Y) const override;
 
     bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
         SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
         unsigned OldShiftOpcode, unsigned NewShiftOpcode,
         SelectionDAG &DAG) const override;
 
+    bool preferScalarizeSplat(unsigned Opc) const override;
+
     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                            CombineLevel Level) const override;
 
     bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
 
     bool
     shouldTransformSignedTruncationCheck(EVT XVT,
                                          unsigned KeptBits) const override {

llvm/lib/Target/X86/X86ISelLowering.cpp

if (DAG.isSplatValue(Y, /*AllowUndefs=*/true))
     return true;
   // If we have AVX2 with it's powerful shift operations, then it's also good.
   if (Subtarget.hasAVX2())
     return true;
   // Pre-AVX2 vector codegen for this pattern is best for variant with 'shl'.
   return NewShiftOpcode == ISD::SHL;
 }
 
+bool X86TargetLowering::preferScalarizeSplat(unsigned Opc) const {
+  return Opc != ISD::FP_EXTEND;
+}
+
 bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
     const SDNode *N, CombineLevel Level) const {
   assert(((N->getOpcode() == ISD::SHL &&
            N->getOperand(0).getOpcode() == ISD::SRL) ||
           (N->getOpcode() == ISD::SRL &&
            N->getOperand(0).getOpcode() == ISD::SHL)) &&
          "Expected shift-shift mask");
   // TODO: Should we always create i64 masks? Or only folded immediates?

llvm/test/CodeGen/X86/prefer-fpext-splat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s
 
 define <4 x double> @prefer(float* %p) {
 ; CHECK-LABEL: prefer:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT:    vcvtss2sd %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:    vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT:    vcvtps2pd (%rdi){1to4}, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = load float, float* %p, align 4
   %vecinit.i = insertelement <4 x float> undef, float %0, i64 0
   %vecinit3.i = shufflevector <4 x float> %vecinit.i, <4 x float> poison, <4 x i32> zeroinitializer
   %conv.i = fpext <4 x float> %vecinit3.i to <4 x double>
   ret <4 x double> %conv.i
 }