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Differential D141484

[RISCV] Add zvl65536b to the target feature list
ClosedPublic

Authored by kito-cheng on Jan 11 2023, 5:28 AM.

Details

Reviewers
asb
craig.topper
reames
Commits
rGd6ab9cae4b68: [RISCV] Add zvl65536b to the target feature list
Summary

We have zvl65536b listed in RISCVISAInfo.cpp, but we don't have
corresponding target feature in td file.

Diff Detail

Unit TestsFailed

TimeTest
60,250 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded::vloxseg.c
60,280 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded::vluxseg.c
60,250 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded::vloxseg.c
60,260 msx64 debian > Clang.CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded::vluxseg.c
60,070 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

kito-cheng created this revision.Jan 11 2023, 5:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 11 2023, 5:28 AM
Herald added subscribers: sunshaoce, VincentWu, vkmr and 26 others. · View Herald Transcript
kito-cheng requested review of this revision.Jan 11 2023, 5:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 11 2023, 5:28 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
kito-cheng added a child revision: D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march.Jan 11 2023, 5:37 AM
Harbormaster completed remote builds in B207054: Diff 488165.Jan 11 2023, 6:39 AM
reames accepted this revision.Jan 11 2023, 7:15 AM

LGTM

This revision is now accepted and ready to land.Jan 11 2023, 7:15 AM
This revision was landed with ongoing or failed builds.Jan 12 2023, 7:52 AM
Closed by commit rGd6ab9cae4b68: [RISCV] Add zvl65536b to the target feature list (authored by kito-cheng). · Explain Why
This revision was automatically updated to reflect the committed changes.
kito-cheng added a commit: rGd6ab9cae4b68: [RISCV] Add zvl65536b to the target feature list.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines

Diff 488165

llvm/lib/Target/RISCV/RISCV.td

Show First 20 Lines • Show All 325 Lines • ▼ Show 20 Lines : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">; "Disable RVC Hint Instructions.">;
def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
AssemblerPredicate<(all_of(not FeatureNoRVCHints)), AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
"RVC Hint Instructions">; "RVC Hint Instructions">;
def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32", def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
"'Zvl' (Minimum Vector Length) 32">; "'Zvl' (Minimum Vector Length) 32">;
foreach i = { 6-15 } in { foreach i = { 6-16 } in {
defvar I = !shl(1, i); defvar I = !shl(1, i);
def FeatureStdExtZvl#I#b : def FeatureStdExtZvl#I#b :
SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I), SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
"'Zvl' (Minimum Vector Length) "#I, "'Zvl' (Minimum Vector Length) "#I,
[!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>; [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
} }
def FeatureStdExtZve32x def FeatureStdExtZve32x
▲ Show 20 Lines • Show All 418 Lines • Show Last 20 Lines