[SelectionDAG] Implicitly truncate known bits in SPLAT_VECTOR

[luke]

Summary

Now that D139525 fixes the Hexagon infinite loop, the stopgap can be
removed to provide more information about known bits in SPLAT_VECTOR
whose operands are smaller than the bit width (which is most of the
time)

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2984

Why extractBits instead of trunc?

[reames]

Test case?

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2980

It looks like you've got some extra white space here.

[luke]

Address feedback

[luke]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

2984

Thanks, that was exactly the function I was looking for

[luke]

Update test cases

[luke]

Rebase on top of D141120

[luke]

Update test

[reames]

LGTM

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
 
   unsigned Opcode = Op.getOpcode();
   switch (Opcode) {
   case ISD::MERGE_VALUES:
     return computeKnownBits(Op.getOperand(Op.getResNo()), DemandedElts,
                             Depth + 1);
   case ISD::SPLAT_VECTOR: {
     SDValue SrcOp = Op.getOperand(0);
-    if (SrcOp.getValueSizeInBits() != BitWidth) {
-      assert(SrcOp.getValueSizeInBits() > BitWidth &&
+      assert(SrcOp.getValueSizeInBits() >= BitWidth &&
              "Expected SPLAT_VECTOR implicit truncation");
-      // FIXME: We should be able to truncate the known bits here to match
-      // the official semantics of SPLAT_VECTOR, but doing so exposes a
-      // Hexagon target bug which results in an infinite loop during
-      // DAGCombine.  (See D137140 for repo).  Once that's fixed, we can
-      // strengthen this.
-      break;
-    }
-    Known = computeKnownBits(SrcOp, Depth + 1);
+    // Implicitly truncate the bits to match the official semantics of
+    // SPLAT_VECTOR.
+    Known = computeKnownBits(SrcOp, Depth + 1).extractBits(BitWidth, 0);
     break;
   }
   case ISD::BUILD_VECTOR:
     assert(!Op.getValueType().isScalableVector());
     // Collect the known bits that are shared by every demanded vector element.
     Known.Zero.setAllBits(); Known.One.setAllBits();
     for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
       if (!DemandedElts[i])