Add implementation isTargetCanonicalConstantNode for hexagon.

[hokein]

Summary

This fixes an infinite compiling loop caused by https://reviews.llvm.org/D137140

[dmgreen]

Can you add the test cases from D137140?

[hokein]

add a testcase

[hokein]

In D139525#3977799, @dmgreen wrote:

Can you add the test cases from D137140?

Added one (I'm not familiar with this part of code, suggestions are welcome).

[bkramer]

Mind moving the test case from llvm/test/CodeGen/AArch64 to llvm/test/CodeGen/Hexagon?

[hokein]

move to a new directory

[hokein]

In D139525#3977834, @bkramer wrote:

Mind moving the test case from llvm/test/CodeGen/AArch64 to llvm/test/CodeGen/Hexagon?

sure, done!

[bkramer]

Looks good, thanks. Let's land this now to unbreak things.

[hokein]

llvm/test/CodeGen/Hexagon/infinite-loop.ll

1

oops, forget to fix typo here (to verify the test), fixed in 3abdd9b91bc17541e78de6251043e178efe0e3ee.

llvm/lib/Target/Hexagon/HexagonISelLowering.h

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &,
                                   EVT) const override;
 
   // Should we expand the build vector with shuffles?
   bool shouldExpandBuildVectorWithShuffles(EVT VT,
       unsigned DefinedValues) const override;
   bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
       unsigned Index) const override;
 
+  bool isTargetCanonicalConstantNode(SDValue Op) const override;
+
   bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
   LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
   LegalizeAction getCustomOperationAction(SDNode &Op) const override;
 
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
                              SelectionDAG &DAG) const override;
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
   MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT();
   if (ResTy.getVectorElementType() != MVT::i1)
     return true;
 
   // Non-HVX bool vectors are relatively cheap.
   return SrcTy.getVectorNumElements() <= 8;
 }
 
+bool HexagonTargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
+  return Op.getOpcode() == ISD::CONCAT_VECTORS ||
+         TargetLowering::isTargetCanonicalConstantNode(Op);
+}
+
 bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
                                                EVT VT) const {
   return true;
 }
 
 TargetLoweringBase::LegalizeTypeAction
 HexagonTargetLowering::getPreferredVectorAction(MVT VT) const {
   unsigned VecLen = VT.getVectorMinNumElements();

llvm/test/CodeGen/Hexagon/infinite-loop.ll

+; RUN: ll < %s
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon-unknown--elf"
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
+declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0
+
+define i32 @offload_rpc_output_s0___outermost_par_for_output_s0_y_line_chunk_chunk(<64 x i32> %0, ptr %linearized) #1 {
+entry:
+  br label %"for linearized.s0.x.x"
+
+"for linearized.s0.x.x":                          ; preds = %"for linearized.s0.x.x", %entry
+  %1 = add <64 x i32> %0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  %2 = call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %1)
+  store <32 x i32> %2, ptr %linearized, align 128
+  br label %"for linearized.s0.x.x"
+}
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #1 = { "target-features"="+hvx-length128b,+long-calls,+hvxv62" }