[LoongArch] Add intrinsics for MOVFCSR2GR and MOVGR2FCSR instructions

[XiaodongLoong]

Summary

Instruction formats:
movgr2fcsr fcsr, rj
movfcsr2gr rd, fcsr
MOVGR2FCSR modifies the value of the software writable field
corresponding to the FCSR (floating-point control and status
register) fcsr according to the value of the lower 32 bits of
the GR (general purpose register) rj.
MOVFCSR2GR sign extends the 32-bit value of the FCSR fcsr
and writes it into the GR rd.

Add "i32 @llvm.loongarch.movfcsr2gr(i32)" intrinsic for MOVFCSR2GR
instruction. The argument is FCSR register number. The return value
is the value in the FCSR.
Add "void @llvm.loongarch.movgr2fcsr(i32, i32)" intrinsic for MOVGR2FCSR
instruction. The first argument is the FCSR number, the second argument
is the value in GR.

[xen0n]

MOVGR2FCSR modifies the value of the software writable field
corresponding to the FCSR (floating-point control and status
register) fcsr according to the value of the lower 32 bits of
the GR (general purpose register) rj.

The description of movgr2fcsr is incorrect, it implies GPR[rj]is read, but in fact it's only the ui5 immediate in rj slot, i.e. FCSR[rj]. I didn't look very closely but the test case changes seem good.

(It's probably more appropriate to name the instructions fcsrrd and fcsrwr (as done in loongarch-opcodes) but it may be hard to officially revise the ISA manual according to some of Loongson insiders. Maybe we can use the corrected names in the internals and expose the official name for now? This is just a suggestion for your teammates to consider though.)

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

53

Be consistent with the surrounding code and spell out the instruction mnemonic fully? Like SDT_LoongArchMovfcsr2gr?

[XiaodongLoong]

rebase code and change code for @xen0n's comments.

[XiaodongLoong]

@xen0n Thanks for your suggestion.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

53

Thanks, I changed that.

[XiaodongLoong]

rebase code.

[xen0n]

In D140685#4017381, @xen0n wrote:

MOVGR2FCSR modifies the value of the software writable field
corresponding to the FCSR (floating-point control and status
register) fcsr according to the value of the lower 32 bits of
the GR (general purpose register) rj.

The description of movgr2fcsr is incorrect, it implies GPR[rj]is read, but in fact it's only the ui5 immediate in rj slot, i.e. FCSR[rj]. I didn't look very closely but the test case changes seem good.

On a closer look it turns out the description is correct after all, the description is very much non-intuitive (uses just fcsr without any position marker) so I've mistaken the GPR operand for the FCSR slot. This is very unfortunate but luckily users of the intrinsics won't have to think about it.

clang/include/clang/Basic/BuiltinsLoongArch.def

 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 // TODO: Support more builtins.
 // TODO: Added feature constraints.
 TARGET_BUILTIN(__builtin_loongarch_dbar, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_ibar, "vIUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_movfcsr2gr, "UiIUi", "nc", "f")
+TARGET_BUILTIN(__builtin_loongarch_movgr2fcsr, "vIUiUi", "nc", "f")
 TARGET_BUILTIN(__builtin_loongarch_break, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_syscall, "vIUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_cpucfg, "UiUi", "nc", "")
 TARGET_BUILTIN(__builtin_loongarch_asrtle_d, "vLiLi", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_asrtgt_d, "vLiLi", "nc", "64bit")
 
 TARGET_BUILTIN(__builtin_loongarch_crc_w_b_w, "iii", "nc", "64bit")
 TARGET_BUILTIN(__builtin_loongarch_crc_w_h_w, "iii", "nc", "64bit")

clang/lib/CodeGen/CGBuiltin.cpp

case LoongArch::BI__builtin_loongarch_dbar:
     ID = Intrinsic::loongarch_dbar;
     break;
   case LoongArch::BI__builtin_loongarch_break:
     ID = Intrinsic::loongarch_break;
     break;
   case LoongArch::BI__builtin_loongarch_ibar:
     ID = Intrinsic::loongarch_ibar;
     break;
+  case LoongArch::BI__builtin_loongarch_movfcsr2gr:
+    ID = Intrinsic::loongarch_movfcsr2gr;
+    break;
+  case LoongArch::BI__builtin_loongarch_movgr2fcsr:
+    ID = Intrinsic::loongarch_movgr2fcsr;
+    break;
   case LoongArch::BI__builtin_loongarch_syscall:
     ID = Intrinsic::loongarch_syscall;
     break;
   case LoongArch::BI__builtin_loongarch_crc_w_b_w:
     ID = Intrinsic::loongarch_crc_w_b_w;
     break;
   case LoongArch::BI__builtin_loongarch_crc_w_h_w:
     ID = Intrinsic::loongarch_crc_w_h_w;

clang/lib/Headers/larchintrin.h

 #endif
 
 #define __break(/*ui15*/ _1) __builtin_loongarch_break((_1))
 
 #define __dbar(/*ui15*/ _1) __builtin_loongarch_dbar((_1))
 
 #define __ibar(/*ui15*/ _1) __builtin_loongarch_ibar((_1))
 
+#define __movfcsr2gr(/*ui5*/ _1) __builtin_loongarch_movfcsr2gr((_1));
+
+#define __movgr2fcsr(/*ui5*/ _1, _2)                                           \
+  __builtin_loongarch_movgr2fcsr((_1), (unsigned int)_2);
+
 #define __syscall(/*ui15*/ _1) __builtin_loongarch_syscall((_1))
 
 #define __csrrd_w(/*ui14*/ _1) ((unsigned int)__builtin_loongarch_csrrd_w((_1)))
 
 #define __csrwr_w(/*unsigned int*/ _1, /*ui14*/ _2)                            \
   ((unsigned int)__builtin_loongarch_csrwr_w((unsigned int)(_1), (_2)))
 
 #define __csrxchg_w(/*unsigned int*/ _1, /*unsigned int*/ _2, /*ui14*/ _3)     \

clang/lib/Sema/SemaChecking.cpp

case LoongArch::BI__builtin_loongarch_csrxchg_d:
     return SemaBuiltinConstantArgRange(TheCall, 2, 0, 16383);
   case LoongArch::BI__builtin_loongarch_lddir_d:
   case LoongArch::BI__builtin_loongarch_ldpte_d:
     if (!TI.hasFeature("64bit"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_loongarch_builtin_requires_la64)
              << TheCall->getSourceRange();
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
+  case LoongArch::BI__builtin_loongarch_movfcsr2gr:
+  case LoongArch::BI__builtin_loongarch_movgr2fcsr:
+    return SemaBuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(2));
   }
 
   return false;
 }
 
 bool Sema::CheckMipsBuiltinFunctionCall(const TargetInfo &TI,
                                         unsigned BuiltinID, CallExpr *TheCall) {
   return CheckMipsBuiltinCpu(TI, BuiltinID, TheCall) ||

clang/test/CodeGen/LoongArch/intrinsic-la32-error.c

 }
 
 void loongarch_break(int a) {
   __builtin_loongarch_break(32769); // expected-error {{argument value 32769 is outside the valid range [0, 32767]}}
   __builtin_loongarch_break(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
   __builtin_loongarch_break(a); // expected-error {{argument to '__builtin_loongarch_break' must be a constant integer}}
 }
 
+int movfcsr2gr_out_of_lo_range(int a) {
+  int b =  __builtin_loongarch_movfcsr2gr(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 3]}}
+  int c = __builtin_loongarch_movfcsr2gr(32); // expected-error {{argument value 32 is outside the valid range [0, 3]}}
+  int d = __builtin_loongarch_movfcsr2gr(a); // expected-error {{argument to '__builtin_loongarch_movfcsr2gr' must be a constant integer}}
+  return 0;
+}
+
+void movgr2fcsr(int a, int b) {
+  __builtin_loongarch_movgr2fcsr(-1, b); // expected-error {{argument value 4294967295 is outside the valid range [0, 3]}}
+  __builtin_loongarch_movgr2fcsr(32, b); // expected-error {{argument value 32 is outside the valid range [0, 3]}}
+  __builtin_loongarch_movgr2fcsr(a, b); // expected-error {{argument to '__builtin_loongarch_movgr2fcsr' must be a constant integer}}
+}
+
 void syscall(int a) {
   __builtin_loongarch_syscall(32769); // expected-error {{argument value 32769 is outside the valid range [0, 32767]}}
   __builtin_loongarch_syscall(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
   __builtin_loongarch_syscall(a); // expected-error {{argument to '__builtin_loongarch_syscall' must be a constant integer}}
 }
 
 int crc_w_b_w(char a, int b) {
   return __builtin_loongarch_crc_w_b_w(a, b); // expected-error {{this builtin requires target: loongarch64}}

clang/test/CodeGen/LoongArch/intrinsic-la32.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - \
+// RUN: %clang_cc1 -triple loongarch32 -target-feature +f -O2 -emit-llvm %s -o - \
 // RUN:     | FileCheck %s -check-prefix=LA32
 
 #include <larchintrin.h>
 
 // LA32-LABEL: @dbar(
 // LA32-NEXT:  entry:
 // LA32-NEXT:    tail call void @llvm.loongarch.dbar(i32 0)
 // LA32-NEXT:    tail call void @llvm.loongarch.dbar(i32 0)

 // LA32-NEXT:    [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
 // LA32-NEXT:    [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
 // LA32-NEXT:    ret void
 //
 void rdtime() {
   __rdtimeh_w();
   __rdtimel_w();
 }
+
+// LA32-LABEL: @loongarch_movfcsr2gr(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+// LA32-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+// LA32-NEXT:    ret i32 0
+//
+int loongarch_movfcsr2gr() {
+  int a =  __movfcsr2gr(1);
+  int b = __builtin_loongarch_movfcsr2gr(1);
+  return 0;
+}
+
+// LA32-LABEL: @loongarch_movgr2fcsr(
+// LA32-NEXT:  entry:
+// LA32-NEXT:    tail call void @llvm.loongarch.movgr2fcsr(i32 1, i32 [[A:%.*]])
+// LA32-NEXT:    tail call void @llvm.loongarch.movgr2fcsr(i32 1, i32 [[A]])
+// LA32-NEXT:    ret void
+//
+void loongarch_movgr2fcsr(int a) {
+  __movgr2fcsr(1, a);
+  __builtin_loongarch_movgr2fcsr(1, a);
+}

clang/test/CodeGen/LoongArch/intrinsic-la64-error.c

void lddir_d(long int a, int b) {
   __builtin_loongarch_lddir_d(a, b); // expected-error {{argument to '__builtin_loongarch_lddir_d' must be a constant integer}}
 }
 
 void ldpte_d(long int a, int b) {
   __builtin_loongarch_ldpte_d(a, 32); // expected-error {{argument value 32 is outside the valid range [0, 31]}}
   __builtin_loongarch_ldpte_d(a, -1); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 31]}}
   __builtin_loongarch_ldpte_d(a, b); // expected-error {{argument to '__builtin_loongarch_ldpte_d' must be a constant integer}}
 }
+
+int movfcsr2gr_out_of_lo_range(int a) {
+  int b = __builtin_loongarch_movfcsr2gr(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 3]}}
+  int c = __builtin_loongarch_movfcsr2gr(32); // expected-error {{argument value 32 is outside the valid range [0, 3]}}
+  int d = __builtin_loongarch_movfcsr2gr(a); // expected-error {{argument to '__builtin_loongarch_movfcsr2gr' must be a constant integer}}
+  return 0;
+}
+
+void movgr2fcsr(int a, int b) {
+  __builtin_loongarch_movgr2fcsr(-1, b); // expected-error {{argument value 4294967295 is outside the valid range [0, 3]}}
+  __builtin_loongarch_movgr2fcsr(32, b); // expected-error {{argument value 32 is outside the valid range [0, 3]}}
+  __builtin_loongarch_movgr2fcsr(a, b); // expected-error {{argument to '__builtin_loongarch_movgr2fcsr' must be a constant integer}}
+}

clang/test/CodeGen/LoongArch/intrinsic-la64.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple loongarch64 -target-feature +f -O2 -emit-llvm %s -o - | FileCheck %s
 
 #include <larchintrin.h>
 
 // CHECK-LABEL: @dbar(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void @llvm.loongarch.dbar(i32 0)
 // CHECK-NEXT:    tail call void @llvm.loongarch.dbar(i32 0)
 // CHECK-NEXT:    ret void

 // CHECK-NEXT:    [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
 // CHECK-NEXT:    [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
 // CHECK-NEXT:    ret void
 //
 void rdtime() {
   __rdtimeh_w();
   __rdtimel_w();
 }
+
+// CHECK-LABEL: @loongarch_movfcsr2gr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+// CHECK-NEXT:    [[TMP1:%.*]] = tail call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+// CHECK-NEXT:    ret i32 0
+//
+int loongarch_movfcsr2gr() {
+  int a =  __movfcsr2gr(1);
+  int b = __builtin_loongarch_movfcsr2gr(1);
+  return 0;
+}
+
+// CHECK-LABEL: @loongarch_movgr2fcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    tail call void @llvm.loongarch.movgr2fcsr(i32 1, i32 [[A:%.*]])
+// CHECK-NEXT:    tail call void @llvm.loongarch.movgr2fcsr(i32 1, i32 [[A]])
+// CHECK-NEXT:    ret void
+//
+void loongarch_movgr2fcsr(int a) {
+  __movgr2fcsr(1, a);
+  __builtin_loongarch_movgr2fcsr(1, a);
+}

llvm/include/llvm/IR/IntrinsicsLoongArch.td

 defm int_loongarch_masked_cmpxchg : MaskedAtomicRMWFiveOpIntrinsics;
 
 //===----------------------------------------------------------------------===//
 // LoongArch BASE
 
 def int_loongarch_break : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 def int_loongarch_dbar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 def int_loongarch_ibar : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
+def int_loongarch_movfcsr2gr : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
+                               [ImmArg<ArgIndex<0>>]>;
+def int_loongarch_movgr2fcsr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty],
+                               [ImmArg<ArgIndex<0>>]>;
 def int_loongarch_syscall : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 
 def int_loongarch_crc_w_b_w : Intrinsic<[llvm_i32_ty],
                                         [llvm_i32_ty, llvm_i32_ty]>;
 def int_loongarch_crc_w_h_w : Intrinsic<[llvm_i32_ty],
                                         [llvm_i32_ty, llvm_i32_ty]>;
 def int_loongarch_crc_w_w_w : Intrinsic<[llvm_i32_ty],
                                         [llvm_i32_ty, llvm_i32_ty]>;

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, "ftintrne.w.s", FPR32,
                            FPR32>;
 def FRINT_S      : FP_CONV<0b0000000100011110010001, "frint.s", FPR32, FPR32>;
 
 // Move Instructions
 def FSEL_S : FP_SEL<0b00001101000000, "fsel", FPR32>;
 def FMOV_S     : FP_MOV<0b0000000100010100100101, "fmov.s", FPR32, FPR32>;
 def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, "movgr2fr.w", FPR32, GPR>;
 def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, "movfr2gr.s", GPR, FPR32>;
-def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, "movgr2fcsr", FCSR, GPR>;
+def MOVGR2FCSR : FPFmtMOV<0b0000000100010100110000, (outs), (ins FCSR:$dst, GPR:$src),
+    "movgr2fcsr", "$dst, $src">;
 def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, "movfcsr2gr", GPR, FCSR>;
 def MOVFR2CF_S : FP_MOV<0b0000000100010100110100, "movfr2cf", CFR, FPR32>;
 def MOVCF2FR_S : FP_MOV<0b0000000100010100110101, "movcf2fr", FPR32, CFR>;
 def MOVGR2CF   : FP_MOV<0b0000000100010100110110, "movgr2cf", CFR, GPR>;
 def MOVCF2GR   : FP_MOV<0b0000000100010100110111, "movcf2gr", GPR, CFR>;
 
 // Branch Instructions
 def BCEQZ : FP_BRANCH<0b01001000, "bceqz">;

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

enum NodeType : unsigned {
   SRL_W,
 
   ROTL_W,
   ROTR_W,
 
   // FPR<->GPR transfer operations
   MOVGR2FR_W_LA64,
   MOVFR2GR_S_LA64,
+  MOVFCSR2GR,
+  MOVGR2FCSR,
 
   FTINT,
 
   // Bit counting operations
   CLZ_W,
   CTZ_W,
 
   BSTRINS,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

case Intrinsic::loongarch_lddir_d: {
     if (!isUInt<8>(Imm)) {
       DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) +
                                   "' out of range");
       return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL);
     }
 
     return Op;
   }
+  case Intrinsic::loongarch_movfcsr2gr: {
+    if (!Subtarget.hasBasicF()) {
+      DAG.getContext()->emitError(
+          "llvm.loongarch.movfcsr2gr expects basic f target feature");
+      return DAG.getMergeValues(
+          {DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)}, SDLoc(Op));
+    }
+    unsigned Imm = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
+    if (!isUInt<2>(Imm)) {
+      DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) +
+                                  "' " + ErrorMsgOOR);
+      return DAG.getMergeValues(
+          {DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)}, SDLoc(Op));
+    }
+    return DAG.getMergeValues(
+        {DAG.getNode(LoongArchISD::MOVFCSR2GR, DL, Op.getValueType(),
+                     DAG.getRegister(LoongArch::FCSR0 + Imm, MVT::i32)),
+         Op.getOperand(0)},
+        DL);
+  }
   }
 }
 
 // Helper function that emits error message for intrinsics with void return
 // value.
 static SDValue emitIntrinsicErrorMessage(SDValue Op, StringRef ErrorMsg,
                                          SelectionDAG &DAG) {
 
SDValue LoongArchTargetLowering::lowerINTRINSIC_VOID(SDValue Op,
   case Intrinsic::loongarch_break: {
     unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
     if (!isUInt<15>(Imm))
       return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
 
     return DAG.getNode(LoongArchISD::BREAK, DL, MVT::Other, Op0,
                        DAG.getConstant(Imm, DL, GRLenVT));
   }
+  case Intrinsic::loongarch_movgr2fcsr: {
+    if (!Subtarget.hasBasicF()) {
+      DAG.getContext()->emitError(
+          "llvm.loongarch.movgr2fcsr expects basic f target feature");
+      return Op0;
+    }
+    unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
+    if (!isUInt<2>(Imm))
+      return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
+
+    return DAG.getNode(
+        LoongArchISD::MOVGR2FCSR, DL, MVT::Other, Op0,
+        DAG.getRegister(LoongArch::FCSR0 + Imm, MVT::i32),
+        DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Op.getOperand(3)));
+  }
   case Intrinsic::loongarch_syscall: {
     unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
     if (!isUInt<15>(Imm))
       return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
 
     return DAG.getNode(LoongArchISD::SYSCALL, DL, MVT::Other, Op0,
                        DAG.getConstant(Imm, DL, GRLenVT));
   }
void LoongArchTargetLowering::ReplaceNodeResults(
   case ISD::CTTZ: {
     assert(VT == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     Results.push_back(customLegalizeToWOp(N, DAG, 1));
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
     SDValue Op0 = N->getOperand(0);
+    EVT VT = N->getValueType(0);
+    uint64_t Op1 = N->getConstantOperandVal(1);
+    if (Op1 == Intrinsic::loongarch_movfcsr2gr) {
+      if (!Subtarget.hasBasicF()) {
+        DAG.getContext()->emitError(
+            "llvm.loongarch.movfcsr2gr expects basic f target feature");
+        Results.push_back(DAG.getMergeValues(
+            {DAG.getUNDEF(N->getValueType(0)), N->getOperand(0)}, SDLoc(N)));
+        Results.push_back(N->getOperand(0));
+        return;
+      }
+      unsigned Imm = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+      if (!isUInt<2>(Imm)) {
+        DAG.getContext()->emitError("argument to '" + N->getOperationName(0) +
+                                    "' " + "out of range");
+        Results.push_back(DAG.getMergeValues(
+            {DAG.getUNDEF(N->getValueType(0)), N->getOperand(0)}, SDLoc(N)));
+        Results.push_back(N->getOperand(0));
+        return;
+      }
+      Results.push_back(DAG.getNode(
+          ISD::TRUNCATE, DL, VT,
+          DAG.getNode(LoongArchISD::MOVFCSR2GR, SDLoc(N), MVT::i64,
+                      DAG.getRegister(LoongArch::FCSR0 + Imm, MVT::i32))));
+      Results.push_back(N->getOperand(0));
+      return;
+    }
     SDValue Op2 = N->getOperand(2);
     MVT GRLenVT = Subtarget.getGRLenVT();
     std::string Name = N->getOperationName(0);
 
-    switch (N->getConstantOperandVal(1)) {
+    switch (Op1) {
     default:
       llvm_unreachable("Unexpected Intrinsic.");
 #define CRC_CASE_EXT_BINARYOP(NAME, NODE)                                      \
   case Intrinsic::loongarch_##NAME: {                                          \
     Results.push_back(DAG.getNode(                                             \
         ISD::TRUNCATE, DL, VT,                                                 \
         DAG.getNode(                                                           \
             LoongArchISD::NODE, DL, MVT::i64,                                  \
case LoongArchISD::node:                                                     \
     NODE_NAME_CASE(IOCSRRD_H)
     NODE_NAME_CASE(IOCSRRD_W)
     NODE_NAME_CASE(IOCSRRD_D)
     NODE_NAME_CASE(IOCSRWR_B)
     NODE_NAME_CASE(IOCSRWR_H)
     NODE_NAME_CASE(IOCSRWR_W)
     NODE_NAME_CASE(IOCSRWR_D)
     NODE_NAME_CASE(CPUCFG)
+    NODE_NAME_CASE(MOVGR2FCSR)
+    NODE_NAME_CASE(MOVFCSR2GR)
   }
 #undef NODE_NAME_CASE
   return nullptr;
 }
 
 //===----------------------------------------------------------------------===//
 //                     Calling Convention Implementation
 //===----------------------------------------------------------------------===//

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
                                               SDTCisVT<2, GRLenVT>]>;
 def SDT_LoongArchCsrxchg : SDTypeProfile<1, 3, [SDTCisInt<0>,
                                                 SDTCisSameAs<0, 1>,
                                                 SDTCisSameAs<0, 2>,
                                                 SDTCisVT<3, GRLenVT>]>;
 def SDT_LoongArchIocsrwr : SDTypeProfile<0, 2, [SDTCisInt<0>,
                                                 SDTCisSameAs<0, 1>]>;
+def SDT_LoongArchGR2FCSR : SDTypeProfile<0, 2, [SDTCisVT<0, i32>,
+    SDTCisVT<1, GRLenVT>]>;
+def SDT_LoongArchFCSR2GR : SDTypeProfile<1, 1, [SDTCisVT<0, GRLenVT>,
+    SDTCisVT<1, i32>]>;
 
 // TODO: Add LoongArch specific DAG Nodes
 // Target-independent nodes, but with target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
                            [SDNPHasChain, SDNPOutGlue]>;
 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 

 def loongarch_clzw : SDNode<"LoongArchISD::CLZ_W", SDTIntBitCountUnaryOp>;
 def loongarch_ctzw : SDNode<"LoongArchISD::CTZ_W", SDTIntBitCountUnaryOp>;
 def loongarch_dbar : SDNode<"LoongArchISD::DBAR", SDT_LoongArchVI,
                              [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_ibar : SDNode<"LoongArchISD::IBAR", SDT_LoongArchVI,
                              [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_break : SDNode<"LoongArchISD::BREAK", SDT_LoongArchVI,
                               [SDNPHasChain, SDNPSideEffect]>;
+def loongarch_movfcsr2gr : SDNode<"LoongArchISD::MOVFCSR2GR", SDT_LoongArchFCSR2GR>;
+def loongarch_movgr2fcsr : SDNode<"LoongArchISD::MOVGR2FCSR", SDT_LoongArchGR2FCSR,
+                                   [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_syscall : SDNode<"LoongArchISD::SYSCALL", SDT_LoongArchVI,
                                 [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_csrrd : SDNode<"LoongArchISD::CSRRD", SDT_LoongArchCsrrd,
                               [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_csrwr : SDNode<"LoongArchISD::CSRWR", SDT_LoongArchCsrwr,
                               [SDNPHasChain, SDNPSideEffect]>;
 def loongarch_csrxchg : SDNode<"LoongArchISD::CSRXCHG",
                                 SDT_LoongArchCsrxchg,

 
 //===----------------------------------------------------------------------===//
 // Basic Floating-Point Instructions
 //===----------------------------------------------------------------------===//
 
 include "LoongArchFloat32InstrInfo.td"
 include "LoongArchFloat64InstrInfo.td"
 
+let Predicates = [HasBasicF] in {
+def : Pat<(loongarch_movfcsr2gr i32:$fcsr),
+          (MOVFCSR2GR FCSR:$fcsr)>;
+def : Pat<(loongarch_movgr2fcsr i32:$fcsr, GRLenVT:$rj),
+          (MOVGR2FCSR FCSR:$fcsr, GPR:$rj)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Privilege Instructions
 //===----------------------------------------------------------------------===//
 
 // CSR Access Instructions
 def CSRRD : FmtCSR<0b0000010000000, (outs GPR:$rd), (ins uimm14:$csr_num),
                    "csrrd", "$rd, $csr_num">;
 let Constraints = "$rd = $dst" in {

llvm/test/CodeGen/LoongArch/intrinsic-error.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
 ; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
-define void @dbar_imm_out_of_hi_range() nounwind {
+define void @dbar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
-define void @dbar_imm_out_of_lo_range() nounwind {
+define void @dbar_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 -1)
   ret void
 }
 
-define void @ibar_imm_out_of_hi_range() nounwind {
+define void @ibar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.ibar' out of range
 entry:
   call void @llvm.loongarch.ibar(i32 32769)
   ret void
 }
 
-define void @ibar_imm_out_of_lo_range() nounwind {
+define void @ibar_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.ibar' out of range
 entry:
   call void @llvm.loongarch.ibar(i32 -1)
   ret void
 }
 
-define void @break_imm_out_of_hi_range() nounwind {
+define void @break_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.break' out of range
 entry:
   call void @llvm.loongarch.break(i32 32769)
   ret void
 }
 
-define void @break_imm_out_of_lo_range() nounwind {
+define void @break_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.break' out of range
 entry:
   call void @llvm.loongarch.break(i32 -1)
   ret void
 }
 
-define void @syscall_imm_out_of_hi_range() nounwind {
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK: llvm.loongarch.movgr2fcsr expects basic f target feature
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
+  ret void
+}
+
+define void @movgr2fcsr_imm_out_of_hi_range(i32 %a) #0 {
+; CHECK: argument to 'llvm.loongarch.movgr2fcsr' out of range
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 32, i32 %a)
+  ret void
+}
+
+define void @movgr2fcsr_imm_out_of_lo_range(i32 %a) #0 {
+; CHECK: argument to 'llvm.loongarch.movgr2fcsr' out of range
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 -1, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr() nounwind {
+; CHECK: llvm.loongarch.movfcsr2gr expects basic f target feature
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+  ret i32 %res
+}
+
+define i32 @movfcsr2gr_imm_out_of_hi_range() #0 {
+; CHECK: argument to 'llvm.loongarch.movfcsr2gr' out of range
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 32)
+  ret i32 %res
+}
+
+define i32 @movfcsr2gr_imm_out_of_lo_range() #0 {
+; CHECK: argument to 'llvm.loongarch.movfcsr2gr' out of range
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 -1)
+  ret i32 %res
+}
+
+define void @syscall_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.syscall' out of range
 entry:
   call void @llvm.loongarch.syscall(i32 32769)
   ret void
 }
 
-define void @syscall_imm_out_of_lo_range() nounwind {
+define void @syscall_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.syscall' out of range
 entry:
   call void @llvm.loongarch.syscall(i32 -1)
   ret void
 }
 
-define i32 @csrrd_w_imm_out_of_hi_range() nounwind {
+define i32 @csrrd_w_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.csrrd.w' out of range
 entry:
   %0 = call i32 @llvm.loongarch.csrrd.w(i32 16384)
   ret i32 %0
 }
 
-define i32 @csrrd_w_imm_out_of_lo_range() nounwind {
+define i32 @csrrd_w_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.csrrd.w' out of range
 entry:
   %0 = call i32 @llvm.loongarch.csrrd.w(i32 -1)
   ret i32 %0
 }
 
-define i32 @csrwr_w_imm_out_of_hi_range(i32 %a) nounwind {
+define i32 @csrwr_w_imm_out_of_hi_range(i32 %a) #0 {
 ; CHECK: argument to 'llvm.loongarch.csrwr.w' out of range
 entry:
   %0 = call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 16384)
   ret i32 %0
 }
 
-define i32 @csrwr_w_imm_out_of_lo_range(i32 %a) nounwind {
+define i32 @csrwr_w_imm_out_of_lo_range(i32 %a) #0 {
 ; CHECK: argument to 'llvm.loongarch.csrwr.w' out of range
 entry:
   %0 = call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 -1)
   ret i32 %0
 }
 
-define i32 @csrxchg_w_imm_out_of_hi_range(i32 %a, i32 %b) nounwind {
+define i32 @csrxchg_w_imm_out_of_hi_range(i32 %a, i32 %b) #0 {
 ; CHECK: argument to 'llvm.loongarch.csrxchg.w' out of range
 entry:
   %0 = call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 16384)
   ret i32 %0
 }
 
-define i32 @csrxchg_w_imm_out_of_lo_range(i32 %a, i32 %b) nounwind {
+define i32 @csrxchg_w_imm_out_of_lo_range(i32 %a, i32 %b) #0 {
 ; CHECK: argument to 'llvm.loongarch.csrxchg.w' out of range
 entry:
   %0 = call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 -1)
   ret i32 %0
 }
+
+attributes #0 = { nounwind "target-features"="+f" }

llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll

 ; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
 ; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_not_constant(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
   call void @llvm.loongarch.dbar(i32 %x)
   ret void
 }
 
 define void @ibar(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
   call void @llvm.loongarch.ibar(i32 %x)
   ret void
 }
 
 define void @break(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
   call void @llvm.loongarch.break(i32 %x)
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 %a, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 %a)
+  ret i32 %res
+}
+
 define void @syscall(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
   call void @llvm.loongarch.syscall(i32 %x)
   ret void
 }

llvm/test/CodeGen/LoongArch/intrinsic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+f < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+f < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 declare i32 @llvm.loongarch.iocsrrd.b(i32)
 declare i32 @llvm.loongarch.iocsrrd.h(i32)
 declare i32 @llvm.loongarch.iocsrrd.w(i32)
 declare void @llvm.loongarch.iocsrwr.b(i32, i32)

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    break 1
 ; CHECK-NEXT:    ret
 entry:
   call void @llvm.loongarch.break(i32 1)
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK-LABEL: movgr2fcsr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movgr2fcsr $fcsr1, $a0
+; CHECK-NEXT:    ret
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr() nounwind {
+; CHECK-LABEL: movfcsr2gr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movfcsr2gr $a0, $fcsr1
+; CHECK-NEXT:    ret
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+  ret i32 %res
+}
+
 define void @syscall() nounwind {
 ; CHECK-LABEL: syscall:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    syscall 1
 ; CHECK-NEXT:    ret
 entry:
   call void @llvm.loongarch.syscall(i32 1)
   ret void