[AArch64][MachineScheduler] Set no side effect for movprfx

[Allen]

Summary

The movprfx is a vector copy, so it doesn't access memory. Set the
value of hasSideEffects 0 to avoid return true for the hasUnmodeledSideEffects(),
which will block the machine scheduler which load/store instructions.

[Allen]

update testcase

[paulwalker-arm]

Patch looks good to me but it looks like we're missing this information for all SVE instructions. Not sure if it used to default to 0 and we missed the switch to ? but the information is missing regardless. @Allen Is this something you plan to follow up on? or should I add it to my list?

llvm/test/CodeGen/AArch64/sched-movprfx.ll

11–12

Not sure you need this test given the llvm-mca explicitly emits this bit and based on my general comment do we really want tests like this for every instruction?

[Allen]

In D140680#4017320, @paulwalker-arm wrote:

Patch looks good to me but it looks like we're missing this information for all SVE instructions. Not sure if it used to default to 0 and we missed the switch to ? but the information is missing regardless. @Allen Is this something you plan to follow up on? or should I add it to my list?

Thanks, If you have time to complete, I am very welcome, I am not skilled in the function of instructions, need to query documents one by one, so it may be too slow to finish that.

llvm/test/CodeGen/AArch64/sched-movprfx.ll

11–12

Thanks, I think this case can be saved as demo for the improvement of schedule.
Yes, it is not needed for every instruction in the following batch modifying.

[dewen]

llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

5039 ↗

(On Diff #485385)

I think this place also needs to be corrected. I'm going to put up a patch to fix

llvm/lib/Target/AArch64/SVEInstrFormats.td

   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = opc{7-6};
   let Inst{21}    = 0b1;
   let Inst{20-16} = opc{5-1};
   let Inst{15-11} = 0b10111;
   let Inst{10}    = opc{0};
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zd;
+
+  let hasSideEffects = 0;
 }
 
 multiclass sve_int_bin_cons_misc_0_c_fexpa<string asm, SDPatternOperator op> {
   def _H : sve_int_bin_cons_misc_0_c<0b01000000, asm, ZPR16>;
   def _S : sve_int_bin_cons_misc_0_c<0b10000000, asm, ZPR32>;
   def _D : sve_int_bin_cons_misc_0_c<0b11000000, asm, ZPR64>;
 
   def : SVE_1_Op_Pat<nxv8f16, op, nxv8i16, !cast<Instruction>(NAME # _H)>;

llvm/test/CodeGen/AArch64/sched-movprfx.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple aarch64 -mcpu=tsv110 -mattr=+sve < %s  | FileCheck %s
+
+; Check that the movprfx intrinsic does not prevent load instructions from
+; being scheduled together. As load instructions have long latency, expected
+; be preferentially issued.
+
+
+; NOTE: The unused paramter ensures z0/z1 is free, avoiding the antidependence for schedule.
+define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64>* %base) {
+; CHECK-LABEL: and_i64_zero:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0]
+; CHECK-NEXT:    ptrue p1.d
+; CHECK-NEXT:    movprfx z0, z2
+; CHECK-NEXT:    abs z0.d, p1/m, z2.d
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %data0 = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %c, i1 0)
+  %data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base,
+                                                            i32 1,
+                                                            <vscale x 2 x i1> %pg,
+                                                            <vscale x 2 x i64> undef)
+  %out = add <vscale x 2 x i64> %data0, %data1
+  ret <vscale x 2 x i64> %out
+}
+
+declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
+declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>*, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)