[AArch64][MachineScheduler] Set no side effect for movprfx

[Allen]

Summary

The movprfx is a vector copy, so it doesn't access memory. Set the
value of hasSideEffects 0 to avoid return true for the hasUnmodeledSideEffects(),
which will block the machine scheduler which load/store instructions.

[Allen]

update testcase

[paulwalker-arm]

Patch looks good to me but it looks like we're missing this information for all SVE instructions. Not sure if it used to default to 0 and we missed the switch to ? but the information is missing regardless. @Allen Is this something you plan to follow up on? or should I add it to my list?

llvm/test/CodeGen/AArch64/sched-movprfx.ll

11–12

Not sure you need this test given the llvm-mca explicitly emits this bit and based on my general comment do we really want tests like this for every instruction?

[Allen]

In D140680#4017320, @paulwalker-arm wrote:

Patch looks good to me but it looks like we're missing this information for all SVE instructions. Not sure if it used to default to 0 and we missed the switch to ? but the information is missing regardless. @Allen Is this something you plan to follow up on? or should I add it to my list?

Thanks, If you have time to complete, I am very welcome, I am not skilled in the function of instructions, need to query documents one by one, so it may be too slow to finish that.

llvm/test/CodeGen/AArch64/sched-movprfx.ll

11–12

Thanks, I think this case can be saved as demo for the improvement of schedule.
Yes, it is not needed for every instruction in the following batch modifying.

[dewen]

llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

5039

I think this place also needs to be corrected. I'm going to put up a patch to fix

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs zprty:$Zd), (ins zprty:$Zn),
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = opc{7-6};
   let Inst{21}    = 0b1;
   let Inst{20-16} = opc{5-1};
   let Inst{15-11} = 0b10111;
   let Inst{10}    = opc{0};
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zd;
+
+  let hasSideEffects = 0;
 }
 
 multiclass sve_int_bin_cons_misc_0_c_fexpa<string asm, SDPatternOperator op> {
   def _H : sve_int_bin_cons_misc_0_c<0b01000000, asm, ZPR16>;
   def _S : sve_int_bin_cons_misc_0_c<0b10000000, asm, ZPR32>;
   def _D : sve_int_bin_cons_misc_0_c<0b11000000, asm, ZPR64>;
 
   def : SVE_1_Op_Pat<nxv8f16, op, nxv8i16, !cast<Instruction>(NAME # _H)>;

llvm/test/CodeGen/AArch64/sched-movprfx.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple aarch64 -mcpu=tsv110 -mattr=+sve < %s  | FileCheck %s
+
+; Check that the movprfx intrinsic does not prevent load instructions from
+; being scheduled together. As load instructions have long latency, expected
+; be preferentially issued.
+
+
+; NOTE: The unused paramter ensures z0/z1 is free, avoiding the antidependence for schedule.
+define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64>* %base) {
+; CHECK-LABEL: and_i64_zero:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0]
+; CHECK-NEXT:    ptrue p1.d
+; CHECK-NEXT:    movprfx z0, z2
+; CHECK-NEXT:    abs z0.d, p1/m, z2.d
+; CHECK-NEXT:    add z0.d, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %data0 = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %c, i1 0)
+  %data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base,
+                                                            i32 1,
+                                                            <vscale x 2 x i1> %pg,
+                                                            <vscale x 2 x i64> undef)
+  %out = add <vscale x 2 x i64> %data0, %data1
+  ret <vscale x 2 x i64> %out
+}
+
+declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
+declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>*, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)

llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

 
 define void @srem_v16i32(ptr %a, ptr %b) #0 {
 ; VBITS_GE_128-LABEL: srem_v16i32:
 ; VBITS_GE_128:       // %bb.0:
 ; VBITS_GE_128-NEXT:    ldp q0, q1, [x0, #32]
 ; VBITS_GE_128-NEXT:    ptrue p0.s, vl4
 ; VBITS_GE_128-NEXT:    ldp q2, q3, [x0]
 ; VBITS_GE_128-NEXT:    ldp q4, q5, [x1, #32]
-; VBITS_GE_128-NEXT:    ldp q7, q6, [x1]
 ; VBITS_GE_128-NEXT:    movprfx z16, z0
 ; VBITS_GE_128-NEXT:    sdiv z16.s, p0/m, z16.s, z4.s
 ; VBITS_GE_128-NEXT:    mls v0.4s, v16.4s, v4.4s
-; VBITS_GE_128-NEXT:    movprfx z4, z3
-; VBITS_GE_128-NEXT:    sdiv z4.s, p0/m, z4.s, z6.s
 ; VBITS_GE_128-NEXT:    movprfx z16, z1
 ; VBITS_GE_128-NEXT:    sdiv z16.s, p0/m, z16.s, z5.s
+; VBITS_GE_128-NEXT:    ldp q7, q6, [x1]
+; VBITS_GE_128-NEXT:    movprfx z4, z3
+; VBITS_GE_128-NEXT:    sdiv z4.s, p0/m, z4.s, z6.s
 ; VBITS_GE_128-NEXT:    mls v1.4s, v16.4s, v5.4s
 ; VBITS_GE_128-NEXT:    movprfx z5, z2
 ; VBITS_GE_128-NEXT:    sdiv z5.s, p0/m, z5.s, z7.s
 ; VBITS_GE_128-NEXT:    mls v2.4s, v5.4s, v7.4s
 ; VBITS_GE_128-NEXT:    mls v3.4s, v4.4s, v6.4s
 ; VBITS_GE_128-NEXT:    stp q0, q1, [x0, #32]
 ; VBITS_GE_128-NEXT:    stp q2, q3, [x0]
 ; VBITS_GE_128-NEXT:    ret

 
 define void @urem_v16i32(ptr %a, ptr %b) #0 {
 ; VBITS_GE_128-LABEL: urem_v16i32:
 ; VBITS_GE_128:       // %bb.0:
 ; VBITS_GE_128-NEXT:    ldp q0, q1, [x0, #32]
 ; VBITS_GE_128-NEXT:    ptrue p0.s, vl4
 ; VBITS_GE_128-NEXT:    ldp q2, q3, [x0]
 ; VBITS_GE_128-NEXT:    ldp q4, q5, [x1, #32]
-; VBITS_GE_128-NEXT:    ldp q7, q6, [x1]
 ; VBITS_GE_128-NEXT:    movprfx z16, z0
 ; VBITS_GE_128-NEXT:    udiv z16.s, p0/m, z16.s, z4.s
 ; VBITS_GE_128-NEXT:    mls v0.4s, v16.4s, v4.4s
-; VBITS_GE_128-NEXT:    movprfx z4, z3
-; VBITS_GE_128-NEXT:    udiv z4.s, p0/m, z4.s, z6.s
 ; VBITS_GE_128-NEXT:    movprfx z16, z1
 ; VBITS_GE_128-NEXT:    udiv z16.s, p0/m, z16.s, z5.s
+; VBITS_GE_128-NEXT:    ldp q7, q6, [x1]
+; VBITS_GE_128-NEXT:    movprfx z4, z3
+; VBITS_GE_128-NEXT:    udiv z4.s, p0/m, z4.s, z6.s
 ; VBITS_GE_128-NEXT:    mls v1.4s, v16.4s, v5.4s
 ; VBITS_GE_128-NEXT:    movprfx z5, z2
 ; VBITS_GE_128-NEXT:    udiv z5.s, p0/m, z5.s, z7.s
 ; VBITS_GE_128-NEXT:    mls v2.4s, v5.4s, v7.4s
 ; VBITS_GE_128-NEXT:    mls v3.4s, v4.4s, v6.4s
 ; VBITS_GE_128-NEXT:    stp q0, q1, [x0, #32]
 ; VBITS_GE_128-NEXT:    stp q2, q3, [x0]
 ; VBITS_GE_128-NEXT:    ret

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll

 ; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
 ; CHECK-NEXT:    fmov w9, s2
 ; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
 ; CHECK-NEXT:    fmov w8, s3
 ; CHECK-NEXT:    mov z6.s, z3.s[1]
 ; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
 ; CHECK-NEXT:    mov z3.s, z2.s[1]
 ; CHECK-NEXT:    uzp1 z4.s, z4.s, z4.s
-; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
 ; CHECK-NEXT:    ldp q0, q1, [x0, #64]
+; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
 ; CHECK-NEXT:    uzp1 z5.s, z5.s, z5.s
 ; CHECK-NEXT:    fmov w10, s5
 ; CHECK-NEXT:    mov z5.s, z5.s[1]
 ; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
 ; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
 ; CHECK-NEXT:    ldp q2, q7, [x0, #96]
 ; CHECK-NEXT:    strh w8, [sp, #12]
 ; CHECK-NEXT:    fmov w8, s4
 ; CHECK-NEXT:    strh w9, [sp, #8]
 ; CHECK-NEXT:    fmov w9, s6
-; CHECK-NEXT:    strh w10, [sp, #4]
 ; CHECK-NEXT:    mov z4.s, z4.s[1]
+; CHECK-NEXT:    strh w10, [sp, #4]
 ; CHECK-NEXT:    strh w8, [sp]
 ; CHECK-NEXT:    fmov w8, s3
-; CHECK-NEXT:    strh w9, [sp, #14]
 ; CHECK-NEXT:    movprfx z3, z7
 ; CHECK-NEXT:    fcvtzs z3.d, p0/m, z7.d
-; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
 ; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
+; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
 ; CHECK-NEXT:    strh w8, [sp, #10]
 ; CHECK-NEXT:    fmov w8, s3
-; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
+; CHECK-NEXT:    strh w9, [sp, #14]
 ; CHECK-NEXT:    fmov w9, s5
 ; CHECK-NEXT:    fmov w10, s4
 ; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
 ; CHECK-NEXT:    strh w8, [sp, #28]
 ; CHECK-NEXT:    fmov w8, s2
 ; CHECK-NEXT:    mov z3.s, z3.s[1]
 ; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
 ; CHECK-NEXT:    strh w9, [sp, #6]

 ; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
 ; CHECK-NEXT:    fmov w9, s2
 ; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
 ; CHECK-NEXT:    fmov w8, s3
 ; CHECK-NEXT:    mov z6.s, z3.s[1]
 ; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
 ; CHECK-NEXT:    mov z3.s, z2.s[1]
 ; CHECK-NEXT:    uzp1 z4.s, z4.s, z4.s
-; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
 ; CHECK-NEXT:    ldp q0, q1, [x0, #64]
+; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
 ; CHECK-NEXT:    uzp1 z5.s, z5.s, z5.s
 ; CHECK-NEXT:    fmov w10, s5
 ; CHECK-NEXT:    mov z5.s, z5.s[1]
 ; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
 ; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
 ; CHECK-NEXT:    ldp q2, q7, [x0, #96]
 ; CHECK-NEXT:    strh w8, [sp, #12]
 ; CHECK-NEXT:    fmov w8, s4
 ; CHECK-NEXT:    strh w9, [sp, #8]
 ; CHECK-NEXT:    fmov w9, s6
-; CHECK-NEXT:    strh w10, [sp, #4]
 ; CHECK-NEXT:    mov z4.s, z4.s[1]
+; CHECK-NEXT:    strh w10, [sp, #4]
 ; CHECK-NEXT:    strh w8, [sp]
 ; CHECK-NEXT:    fmov w8, s3
-; CHECK-NEXT:    strh w9, [sp, #14]
 ; CHECK-NEXT:    movprfx z3, z7
 ; CHECK-NEXT:    fcvtzs z3.d, p0/m, z7.d
-; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
 ; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
+; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
 ; CHECK-NEXT:    strh w8, [sp, #10]
 ; CHECK-NEXT:    fmov w8, s3
-; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
+; CHECK-NEXT:    strh w9, [sp, #14]
 ; CHECK-NEXT:    fmov w9, s5
 ; CHECK-NEXT:    fmov w10, s4
 ; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
 ; CHECK-NEXT:    strh w8, [sp, #28]
 ; CHECK-NEXT:    fmov w8, s2
 ; CHECK-NEXT:    mov z3.s, z3.s[1]
 ; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
 ; CHECK-NEXT:    strh w9, [sp, #6]

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll

; CHECK-NEXT:    ret
   ret <4 x i32> %res
 }
 
 define void @bswap_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: bswap_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    movprfx z2, z0
-; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, #24
 ; CHECK-NEXT:    movprfx z3, z0
 ; CHECK-NEXT:    lsr z3.s, p0/m, z3.s, #8
-; CHECK-NEXT:    movprfx z4, z1
-; CHECK-NEXT:    lsr z4.s, p0/m, z4.s, #24
 ; CHECK-NEXT:    movprfx z5, z1
 ; CHECK-NEXT:    lsr z5.s, p0/m, z5.s, #8
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, #24
+; CHECK-NEXT:    movprfx z4, z1
+; CHECK-NEXT:    lsr z4.s, p0/m, z4.s, #24
 ; CHECK-NEXT:    and z3.s, z3.s, #0xff00
 ; CHECK-NEXT:    and z5.s, z5.s, #0xff00
 ; CHECK-NEXT:    orr z2.d, z3.d, z2.d
 ; CHECK-NEXT:    movprfx z3, z0
 ; CHECK-NEXT:    lsl z3.s, p0/m, z3.s, #24
 ; CHECK-NEXT:    orr z4.d, z5.d, z4.d
 ; CHECK-NEXT:    movprfx z5, z1
 ; CHECK-NEXT:    lsl z5.s, p0/m, z5.s, #24
; CHECK-NEXT:    ret
   ret void
 }
 
 define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
 ; CHECK-LABEL: bswap_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl1
-; CHECK-NEXT:    movprfx z1, z0
-; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #56
 ; CHECK-NEXT:    movprfx z2, z0
 ; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #40
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #56
 ; CHECK-NEXT:    movprfx z3, z0
 ; CHECK-NEXT:    lsr z3.d, p0/m, z3.d, #24
 ; CHECK-NEXT:    movprfx z4, z0
 ; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #8
 ; CHECK-NEXT:    mov z5.d, z0.d
 ; CHECK-NEXT:    and z2.d, z2.d, #0xff00
 ; CHECK-NEXT:    and z3.d, z3.d, #0xff0000
 ; CHECK-NEXT:    orr z1.d, z2.d, z1.d
; CHECK-NEXT:    ret
   ret <1 x i64> %res
 }
 
 define <2 x i64> @bswap_v2i64(<2 x i64> %op) #0 {
 ; CHECK-LABEL: bswap_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    movprfx z1, z0
-; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #56
 ; CHECK-NEXT:    movprfx z2, z0
 ; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #40
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #56
 ; CHECK-NEXT:    movprfx z3, z0
 ; CHECK-NEXT:    lsr z3.d, p0/m, z3.d, #24
 ; CHECK-NEXT:    movprfx z4, z0
 ; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #8
 ; CHECK-NEXT:    mov z5.d, z0.d
 ; CHECK-NEXT:    and z2.d, z2.d, #0xff00
 ; CHECK-NEXT:    and z3.d, z3.d, #0xff0000
 ; CHECK-NEXT:    orr z1.d, z2.d, z1.d
; CHECK-NEXT:    ret
   ret <2 x i64> %res
 }
 
 define void @bswap_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: bswap_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    movprfx z2, z0
-; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #56
 ; CHECK-NEXT:    movprfx z3, z0
 ; CHECK-NEXT:    lsr z3.d, p0/m, z3.d, #40
 ; CHECK-NEXT:    movprfx z4, z0
 ; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #24
 ; CHECK-NEXT:    movprfx z5, z0
 ; CHECK-NEXT:    lsr z5.d, p0/m, z5.d, #8
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #56
 ; CHECK-NEXT:    and z3.d, z3.d, #0xff00
 ; CHECK-NEXT:    and z4.d, z4.d, #0xff0000
 ; CHECK-NEXT:    and z5.d, z5.d, #0xff000000
 ; CHECK-NEXT:    orr z2.d, z3.d, z2.d
 ; CHECK-NEXT:    orr z3.d, z5.d, z4.d
 ; CHECK-NEXT:    mov z6.d, z0.d
 ; CHECK-NEXT:    mov z7.d, z0.d
-; CHECK-NEXT:    movprfx z16, z0
-; CHECK-NEXT:    lsl z16.d, p0/m, z16.d, #56
 ; CHECK-NEXT:    orr z2.d, z3.d, z2.d
 ; CHECK-NEXT:    and z6.d, z6.d, #0xff000000
 ; CHECK-NEXT:    and z7.d, z7.d, #0xff0000
 ; CHECK-NEXT:    movprfx z3, z6
 ; CHECK-NEXT:    lsl z3.d, p0/m, z3.d, #8
 ; CHECK-NEXT:    movprfx z4, z7
 ; CHECK-NEXT:    lsl z4.d, p0/m, z4.d, #24
 ; CHECK-NEXT:    orr z3.d, z4.d, z3.d
 ; CHECK-NEXT:    movprfx z4, z1
 ; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #40
+; CHECK-NEXT:    movprfx z16, z0
+; CHECK-NEXT:    lsl z16.d, p0/m, z16.d, #56
 ; CHECK-NEXT:    and z0.d, z0.d, #0xff00
 ; CHECK-NEXT:    movprfx z5, z1
 ; CHECK-NEXT:    lsr z5.d, p0/m, z5.d, #56
 ; CHECK-NEXT:    and z4.d, z4.d, #0xff00
 ; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #40
 ; CHECK-NEXT:    orr z4.d, z4.d, z5.d
 ; CHECK-NEXT:    movprfx z5, z1
 ; CHECK-NEXT:    lsr z5.d, p0/m, z5.d, #24

llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s

 # CHECK-NEXT:  1      4     1.00                        mov z21.s, p0/z, #-128
 # CHECK-NEXT:  1      4     1.00                        mov z21.s, p0/z, #-32768
 # CHECK-NEXT:  1      4     1.00                        mov z21.s, p0/z, #127
 # CHECK-NEXT:  1      4     1.00                        mov z21.s, p0/z, #32512
 # CHECK-NEXT:  1      4     1.00                        mov z21.s, p15/m, #-128
 # CHECK-NEXT:  1      4     1.00                        mov z21.s, p15/m, #-32768
 # CHECK-NEXT:  1      4     0.50                        mov z31.b, p15/m, z31.b
 # CHECK-NEXT:  1      6     1.00                  U     mov z31.b, p7/m, b31
-# CHECK-NEXT:  1      1     0.17                  U     movprfx z31, z6
+# CHECK-NEXT:  1      1     0.17                        movprfx z31, z6
 # CHECK-NEXT:  1      8     1.00                        mov z31.b, p7/m, wsp
 # CHECK-NEXT:  1      6     1.00                        mov z31.b, wsp
 # CHECK-NEXT:  1      4     1.00                        mov z31.b, z31.b[63]
 # CHECK-NEXT:  1      4     0.50                        mov z31.d, p15/m, z31.d
 # CHECK-NEXT:  1      6     1.00                        mov z31.d, p7/m, d31
 # CHECK-NEXT:  1      1     0.17                  U     movprfx z31.d, p7/z, z6.d
 # CHECK-NEXT:  1      8     1.00                        mov z31.d, p7/m, sp
 # CHECK-NEXT:  1      6     1.00                        mov z31.d, sp

llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

 # CHECK-NEXT:  1      2     0.50                        mov z21.s, p0/z, #-128
 # CHECK-NEXT:  1      2     0.50                        mov z21.s, p0/z, #-32768
 # CHECK-NEXT:  1      2     0.50                        mov z21.s, p0/z, #127
 # CHECK-NEXT:  1      2     0.50                        mov z21.s, p0/z, #32512
 # CHECK-NEXT:  1      2     0.50                        mov z21.s, p15/m, #-128
 # CHECK-NEXT:  1      2     0.50                        mov z21.s, p15/m, #-32768
 # CHECK-NEXT:  1      2     0.50                        mov z31.b, p15/m, z31.b
 # CHECK-NEXT:  1      2     0.50                  U     mov z31.b, p7/m, b31
-# CHECK-NEXT:  1      2     0.50                  U     movprfx z31, z6
+# CHECK-NEXT:  1      2     0.50                        movprfx z31, z6
 # CHECK-NEXT:  2      5     1.00                        mov z31.b, p7/m, wsp
 # CHECK-NEXT:  1      3     3.00                        mov z31.b, wsp
 # CHECK-NEXT:  1      2     0.50                        mov z31.b, z31.b[63]
 # CHECK-NEXT:  1      2     0.50                        mov z31.d, p15/m, z31.d
 # CHECK-NEXT:  1      2     0.50                        mov z31.d, p7/m, d31
 # CHECK-NEXT:  1      2     0.50                  U     movprfx z31.d, p7/z, z6.d
 # CHECK-NEXT:  2      5     1.00                        mov z31.d, p7/m, sp
 # CHECK-NEXT:  1      3     3.00                        mov z31.d, sp
 # CHECK-NEXT:  1      2     0.50                        mov z31.d, z0.d
 # CHECK-NEXT:  1      2     0.50                        mov z31.d, z31.d[7]
 # CHECK-NEXT:  1      2     0.50                        mov z31.h, p15/m, z31.h
 # CHECK-NEXT:  1      2     0.50                        mov z31.h, p7/m, h31
 # CHECK-NEXT:  2      5     1.00                        mov z31.h, p7/m, wsp
 # CHECK-NEXT:  1      3     3.00                        mov z31.h, wsp