[AArch64][SME] Avoid going through memory for streaming-compatible splats

[david-arm]

LGTM! Tres bien!

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

11976–11983

This doesn't look like the correct play to me. We don't support ISD::BUILD_VECTOR for SVE vectors and this extends to the fixed length variety.

I think what's actually missing is custom lowering for ISD::SPLAT_VECTOR for 64/128-bit fixed length vector types, presumably with logic to not low the NumElements == 1 case given that's best scalarised?

This might not yield exactly the same code but is a better starting point.

[sdesmalen]

Address review comment.

[paulwalker-arm]

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll

722–723

This is an example of where we likely want some special NumElements == 1 handling when lowering splat_vector but that can be done separately.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
 
   return false;
 }
 
 void AArch64TargetLowering::addTypeForStreamingSVE(MVT VT) {
   setOperationAction(ISD::ANY_EXTEND, VT, Custom);
   setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
   setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
+  setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
   setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
   setOperationAction(ISD::AND, VT, Custom);
   setOperationAction(ISD::ADD, VT, Custom);
   setOperationAction(ISD::SUB, VT, Custom);
   setOperationAction(ISD::MUL, VT, Custom);
   setOperationAction(ISD::MULHS, VT, Custom);
   setOperationAction(ISD::MULHU, VT, Custom);
   setOperationAction(ISD::ABS, VT, Custom);
SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
 
   return GenerateTBL(Op, ShuffleMask, DAG);
 }
 
 SDValue AArch64TargetLowering::LowerSPLAT_VECTOR(SDValue Op,
                                                  SelectionDAG &DAG) const {
   EVT VT = Op.getValueType();
 
-  if (useSVEForFixedLengthVectorVT(VT))
+  if (useSVEForFixedLengthVectorVT(VT,
+                                   Subtarget->forceStreamingCompatibleSVE()))
     return LowerToScalableOp(Op, DAG);
 
   assert(VT.isScalableVector() && VT.getVectorElementType() == MVT::i1 &&
          "Unexpected vector type!");
 
   // We can handle the constant cases during isel.
   if (isa<ConstantSDNode>(Op.getOperand(0)))
     return Op;
if (auto SeqInfo = cast<BuildVectorSDNode>(Op)->isConstantSequence()) {
       SDLoc DL(Op);
       EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
       SDValue Start = DAG.getConstant(SeqInfo->first, DL, ContainerVT);
       SDValue Steps = DAG.getStepVector(DL, ContainerVT, SeqInfo->second);
       SDValue Seq = DAG.getNode(ISD::ADD, DL, ContainerVT, Start, Steps);
       return convertFromScalableVector(DAG, Op.getValueType(), Seq);
     }
 
     // Revert to common legalisation for all other variants.
     return SDValue();
   }
 
   // Try to build a simple constant vector.
   Op = NormalizeBuildVector(Op, DAG);
   // Thought this might return a non-BUILD_VECTOR (e.g. CONCAT_VECTORS), if so,
   // abort.
   if (Op.getOpcode() != ISD::BUILD_VECTOR)
     return SDValue();
 
   if (VT.isInteger()) {
     // Certain vector constants, used to express things like logical NOT and
     // arithmetic NEG, are passed through unmodified.  This allows special
     // patterns for these operations to match, which will lower these constants
     // to whatever is proven necessary.

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; CLZ
 ;
 
 define <4 x i8> @ctlz_v4i8(<4 x i8> %op) #0 {
 ; CHECK-LABEL: ctlz_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    adrp x9, .LCPI0_1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    ldr d2, [x9, :lo12:.LCPI0_1]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
 ; CHECK-NEXT:    clz z0.h, p0/m, z0.h
-; CHECK-NEXT:    sub z0.h, z0.h, z2.h
+; CHECK-NEXT:    sub z0.h, z0.h, #8 // =0x8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i8> @llvm.ctlz.v4i8(<4 x i8> %op)
   ret <4 x i8> %res
 }
 
 define <8 x i8> @ctlz_v8i8(<8 x i8> %op) #0 {
 ; CHECK-LABEL: ctlz_v8i8:
; CHECK-NEXT:    ret
   %res = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %op)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define <2 x i16> @ctlz_v2i16(<2 x i16> %op) #0 {
 ; CHECK-LABEL: ctlz_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
-; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr d2, [x9, :lo12:.LCPI4_1]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
 ; CHECK-NEXT:    clz z0.s, p0/m, z0.s
-; CHECK-NEXT:    sub z0.s, z0.s, z2.s
+; CHECK-NEXT:    sub z0.s, z0.s, #16 // =0x10
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i16> @llvm.ctlz.v2i16(<2 x i16> %op)
   ret <2 x i16> %res
 }
 
 define <4 x i16> @ctlz_v4i16(<4 x i16> %op) #0 {
 ; CHECK-LABEL: ctlz_v4i16:

 
 ;
 ; CNT
 ;
 
 define <4 x i8> @ctpop_v4i8(<4 x i8> %op) #0 {
 ; CHECK-LABEL: ctpop_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI14_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
 ; CHECK-NEXT:    cnt z0.h, p0/m, z0.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %op)
   ret <4 x i8> %res
 }
 
 define <8 x i8> @ctpop_v8i8(<8 x i8> %op) #0 {
; CHECK-NEXT:    ret
   %res = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %op)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define <2 x i16> @ctpop_v2i16(<2 x i16> %op) #0 {
 ; CHECK-LABEL: ctpop_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI18_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI18_0]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
 ; CHECK-NEXT:    cnt z0.s, p0/m, z0.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i16> @llvm.ctpop.v2i16(<2 x i16> %op)
   ret <2 x i16> %res
 }
 
 define <4 x i16> @ctpop_v4i16(<4 x i16> %op) #0 {

 
 ;
 ; Count trailing zeros
 ;
 
 define <4 x i8> @cttz_v4i8(<4 x i8> %op) #0 {
 ; CHECK-LABEL: cttz_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI28_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI28_0]
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
+; CHECK-NEXT:    orr z0.h, z0.h, #0x100
 ; CHECK-NEXT:    rbit z0.h, p0/m, z0.h
 ; CHECK-NEXT:    clz z0.h, p0/m, z0.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %op)
   ret <4 x i8> %res
 }
 
; CHECK-NEXT:    ret
   %res = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %op)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define <2 x i16> @cttz_v2i16(<2 x i16> %op) #0 {
 ; CHECK-LABEL: cttz_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI32_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI32_0]
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
+; CHECK-NEXT:    orr z0.s, z0.s, #0x10000
 ; CHECK-NEXT:    rbit z0.s, p0/m, z0.s
 ; CHECK-NEXT:    clz z0.s, p0/m, z0.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %op)
   ret <2 x i16> %res
 }
 

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64"
 
 ;
 ; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
 ;       don't currently expect the code below to lower to BSL/BIT/BIF. Once
 ;       this is implemented, this test will be fleshed out.
 ;
 
 define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) #0 {
 ; CHECK-LABEL: fixed_bitselect_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    ldp q1, q0, [x0]
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    adrp x8, .LCPI0_1
-; CHECK-NEXT:    ldp q3, q4, [x1]
-; CHECK-NEXT:    sub z6.s, z2.s, z1.s
-; CHECK-NEXT:    sub z2.s, z2.s, z0.s
-; CHECK-NEXT:    and z3.d, z6.d, z3.d
-; CHECK-NEXT:    ldp q7, q16, [x2]
+; CHECK-NEXT:    ldp q3, q2, [x0]
+; CHECK-NEXT:    mov z0.s, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    add z7.s, z3.s, z0.s
+; CHECK-NEXT:    subr z3.s, z3.s, #0 // =0x0
+; CHECK-NEXT:    ldp q1, q4, [x1]
+; CHECK-NEXT:    add z0.s, z2.s, z0.s
+; CHECK-NEXT:    subr z2.s, z2.s, #0 // =0x0
+; CHECK-NEXT:    and z1.d, z3.d, z1.d
+; CHECK-NEXT:    ldp q5, q6, [x2]
 ; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    ldr q5, [x8, :lo12:.LCPI0_1]
-; CHECK-NEXT:    add z1.s, z1.s, z5.s
-; CHECK-NEXT:    add z0.s, z0.s, z5.s
-; CHECK-NEXT:    and z4.d, z0.d, z16.d
-; CHECK-NEXT:    and z0.d, z1.d, z7.d
-; CHECK-NEXT:    orr z0.d, z0.d, z3.d
-; CHECK-NEXT:    orr z1.d, z4.d, z2.d
+; CHECK-NEXT:    and z3.d, z0.d, z6.d
+; CHECK-NEXT:    and z0.d, z7.d, z5.d
+; CHECK-NEXT:    orr z0.d, z0.d, z1.d
+; CHECK-NEXT:    orr z1.d, z3.d, z2.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
 ; CHECK-NEXT:    ret
   %pre_cond = load <8 x i32>, ptr %pre_cond_ptr
   %left = load <8 x i32>, ptr %left_ptr
   %right = load <8 x i32>, ptr %right_ptr
 
   %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
   %min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
   %left_bits_0 = and <8 x i32> %neg_cond, %left
   %right_bits_0 = and <8 x i32> %min_cond, %right
   %bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
   ret <8 x i32> %bsl0000
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll

; CHECK-NEXT:    ret
   %a = load <2 x i32>, <2 x i32>* %ap
   %val = zext <2 x i32> %a to <2 x i64>
   ret <2 x i64> %val
 }
 
 define <2 x i256> @load_zext_v2i64i256(<2 x i64>* %ap) #0 {
 ; CHECK-LABEL: load_zext_v2i64i256:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI3_0
-; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    mov x1, xzr
-; CHECK-NEXT:    mov x5, xzr
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
+; CHECK-NEXT:    ldr q1, [x0]
 ; CHECK-NEXT:    mov z2.d, z0.d[1]
-; CHECK-NEXT:    fmov x0, d0
-; CHECK-NEXT:    fmov x4, d2
+; CHECK-NEXT:    fmov x2, d0
+; CHECK-NEXT:    fmov x3, d2
+; CHECK-NEXT:    mov x1, xzr
 ; CHECK-NEXT:    mov z0.d, z1.d[1]
-; CHECK-NEXT:    fmov x2, d1
-; CHECK-NEXT:    fmov x3, d0
+; CHECK-NEXT:    fmov x0, d1
+; CHECK-NEXT:    fmov x4, d0
+; CHECK-NEXT:    mov x5, xzr
 ; CHECK-NEXT:    mov x6, x2
 ; CHECK-NEXT:    mov x7, x3
 ; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %ap
   %val = zext <2 x i64> %a to <2 x i256>
   ret <2 x i256> %val
 }
 
; CHECK-NEXT:    ret
   %a = load <4 x i32>, <4 x i32>* %ap
   %val = sext <4 x i32> %a to <4 x i256>
   ret <4 x i256> %val
 }
 
 define <2 x i256> @load_sext_v2i64i256(<2 x i64>* %ap) #0 {
 ; CHECK-LABEL: load_sext_v2i64i256:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    fmov x8, d0
 ; CHECK-NEXT:    mov z0.d, z0.d[1]
+; CHECK-NEXT:    fmov x10, d0
 ; CHECK-NEXT:    asr x9, x8, #63
-; CHECK-NEXT:    stp x8, x9, [sp, #16]
-; CHECK-NEXT:    fmov x8, d0
-; CHECK-NEXT:    stp x9, x9, [sp]
-; CHECK-NEXT:    ldp q1, q0, [sp]
-; CHECK-NEXT:    asr x10, x8, #63
-; CHECK-NEXT:    stp x8, x10, [sp, #48]
-; CHECK-NEXT:    fmov x2, d1
-; CHECK-NEXT:    stp x10, x10, [sp, #32]
-; CHECK-NEXT:    ldp q3, q2, [sp, #32]
-; CHECK-NEXT:    mov z4.d, z0.d[1]
-; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    asr x11, x10, #63
+; CHECK-NEXT:    stp x8, x9, [sp, #-32]!
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    mov z0.d, x9
+; CHECK-NEXT:    stp x10, x11, [sp, #16]
+; CHECK-NEXT:    mov z1.d, z0.d[1]
+; CHECK-NEXT:    fmov x2, d0
+; CHECK-NEXT:    mov z0.d, x11
+; CHECK-NEXT:    fmov x3, d1
+; CHECK-NEXT:    ldp q1, q3, [sp], #32
+; CHECK-NEXT:    mov z2.d, z0.d[1]
+; CHECK-NEXT:    fmov x6, d0
 ; CHECK-NEXT:    mov z0.d, z1.d[1]
-; CHECK-NEXT:    fmov x1, d4
-; CHECK-NEXT:    fmov x3, d0
-; CHECK-NEXT:    fmov x6, d3
-; CHECK-NEXT:    mov z1.d, z2.d[1]
-; CHECK-NEXT:    fmov x4, d2
-; CHECK-NEXT:    mov z2.d, z3.d[1]
-; CHECK-NEXT:    fmov x5, d1
+; CHECK-NEXT:    fmov x0, d1
+; CHECK-NEXT:    mov z1.d, z3.d[1]
 ; CHECK-NEXT:    fmov x7, d2
-; CHECK-NEXT:    add sp, sp, #64
+; CHECK-NEXT:    fmov x4, d3
+; CHECK-NEXT:    fmov x1, d0
+; CHECK-NEXT:    fmov x5, d1
 ; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %ap
   %val = sext <2 x i64> %a to <2 x i256>
   ret <2 x i256> %val
 }
 
 define <16 x i64> @load_zext_v16i16i64(<16 x i16>* %ap)  #0 {
 ; CHECK-LABEL: load_zext_v16i16i64:

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll

 ;
 ; FCMP UGT
 ;
 
 define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; CHECK-LABEL: fcmp_ugt_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI14_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q1, q2, [x0]
 ; CHECK-NEXT:    fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI14_0]
+; CHECK-NEXT:    mov z0.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z1.h, p1/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    fcmge p0.h, p0/z, z3.h, z2.h
-; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z4.d
-; CHECK-NEXT:    eor z1.d, z1.d, z4.d
-; CHECK-NEXT:    stp q0, q1, [x2]
+; CHECK-NEXT:    eor z1.d, z1.d, z0.d
+; CHECK-NEXT:    mov z2.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    eor z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %cmp = fcmp ugt <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, ptr %c
   ret void
 }

 ;
 ; FCMP ULT
 ;
 
 define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; CHECK-LABEL: fcmp_ult_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI16_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q1, q2, [x0]
 ; CHECK-NEXT:    fcmge p1.h, p0/z, z1.h, z0.h
-; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI16_0]
+; CHECK-NEXT:    mov z0.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z1.h, p1/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    fcmge p0.h, p0/z, z2.h, z3.h
-; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z4.d
-; CHECK-NEXT:    eor z1.d, z1.d, z4.d
-; CHECK-NEXT:    stp q0, q1, [x2]
+; CHECK-NEXT:    eor z1.d, z1.d, z0.d
+; CHECK-NEXT:    mov z2.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    eor z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %cmp = fcmp ult <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, ptr %c
   ret void
 }

 ;
 ; FCMP UGE
 ;
 
 define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; CHECK-LABEL: fcmp_uge_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI18_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q1, q2, [x0]
 ; CHECK-NEXT:    fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI18_0]
+; CHECK-NEXT:    mov z0.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z1.h, p1/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    fcmgt p0.h, p0/z, z3.h, z2.h
-; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z4.d
-; CHECK-NEXT:    eor z1.d, z1.d, z4.d
-; CHECK-NEXT:    stp q0, q1, [x2]
+; CHECK-NEXT:    eor z1.d, z1.d, z0.d
+; CHECK-NEXT:    mov z2.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    eor z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %cmp = fcmp uge <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, ptr %c
   ret void
 }

 ;
 ; FCMP ULE
 ;
 
 define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; CHECK-LABEL: fcmp_ule_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI20_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q1, q2, [x0]
 ; CHECK-NEXT:    fcmgt p1.h, p0/z, z1.h, z0.h
-; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI20_0]
+; CHECK-NEXT:    mov z0.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z1.h, p1/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    fcmgt p0.h, p0/z, z2.h, z3.h
-; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z4.d
-; CHECK-NEXT:    eor z1.d, z1.d, z4.d
-; CHECK-NEXT:    stp q0, q1, [x2]
+; CHECK-NEXT:    eor z1.d, z1.d, z0.d
+; CHECK-NEXT:    mov z2.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    eor z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %cmp = fcmp ule <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, ptr %c
   ret void
 }

 ;
 ; FCMP ORD
 ;
 
 define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) #0 {
 ; CHECK-LABEL: fcmp_ord_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q3, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI22_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q1, q2, [x0]
 ; CHECK-NEXT:    fcmuo p1.h, p0/z, z1.h, z0.h
-; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI22_0]
+; CHECK-NEXT:    mov z0.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z1.h, p1/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    fcmuo p0.h, p0/z, z2.h, z3.h
-; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    eor z0.d, z0.d, z4.d
-; CHECK-NEXT:    eor z1.d, z1.d, z4.d
-; CHECK-NEXT:    stp q0, q1, [x2]
+; CHECK-NEXT:    eor z1.d, z1.d, z0.d
+; CHECK-NEXT:    mov z2.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    eor z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x2]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %cmp = fcmp ord <16 x half> %op1, %op2
   %sext = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %sext, ptr %c
   ret void
 }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ; Ensure we don't crash when trying to combine fp<->int conversions
 define void @fp_convert_combine_crash(<8 x float> *%a, <8 x i32> *%b) #0 {
 ; CHECK-LABEL: fp_convert_combine_crash:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    fmov z2.s, #8.00000000
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q0, q2, [x0]
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    fmul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    fmul z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    fmul z0.s, p0/m, z0.s, z2.s
 ; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT:    fmul z1.s, p0/m, z1.s, z2.s
 ; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.s
 ; CHECK-NEXT:    stp q0, q1, [x1]
 ; CHECK-NEXT:    ret
   %f = load <8 x float>, <8 x float>* %a
   %mul.i = fmul <8 x float> %f, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00,
                                  float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
   %vcvt.i = fptosi <8 x float> %mul.i to <8 x i32>
   store <8 x i32> %vcvt.i, <8 x i32>* %b
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v2f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI0_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI0_0]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.h, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <2 x half> %op1, <2 x half> %op2
   ret <2 x half> %sel
 }
 
 define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI1_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI1_0]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.h, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <4 x half> %op1, <4 x half> %op2
   ret <4 x half> %sel
 }
 
 define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v8f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI2_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI2_0]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    strh w8, [sp, #6]
-; CHECK-NEXT:    strh w8, [sp, #4]
-; CHECK-NEXT:    strh w8, [sp, #2]
-; CHECK-NEXT:    strh w8, [sp]
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.h, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <8 x half> %op1, <8 x half> %op2
   ret <8 x half> %sel
 }
 
 define void @select_v16f16(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w2, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI3_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
 ; CHECK-NEXT:    ldr q2, [x1]
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    ldr q5, [x9, :lo12:.LCPI3_0]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    strh w8, [sp, #6]
-; CHECK-NEXT:    strh w8, [sp, #4]
-; CHECK-NEXT:    strh w8, [sp, #2]
-; CHECK-NEXT:    strh w8, [sp]
-; CHECK-NEXT:    ldr q4, [sp]
-; CHECK-NEXT:    eor z5.d, z4.d, z5.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    mov z4.h, w8
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
 ; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    and z3.d, z3.d, z5.d
+; CHECK-NEXT:    bic z3.d, z3.d, z4.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <16 x half>, ptr %a
   %op2 = load volatile <16 x half>, ptr %b
   %sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2
   store <16 x half> %sel, ptr %a
   ret void
 }
 
 define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v2f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI4_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI4_0]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mvn w9, w8
+; CHECK-NEXT:    mov z2.s, w8
+; CHECK-NEXT:    mov z3.s, w9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <2 x float> %op1, <2 x float> %op2
   ret <2 x float> %sel
 }
 
 define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI5_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI5_0]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    stp w8, w8, [sp]
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mvn w9, w8
+; CHECK-NEXT:    mov z2.s, w8
+; CHECK-NEXT:    mov z3.s, w9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <4 x float> %op1, <4 x float> %op2
   ret <4 x float> %sel
 }
 
 define void @select_v8f32(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v8f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w2, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI6_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
+; CHECK-NEXT:    mvn w9, w8
 ; CHECK-NEXT:    ldr q2, [x1]
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    stp w8, w8, [sp]
-; CHECK-NEXT:    ldr q5, [x9, :lo12:.LCPI6_0]
-; CHECK-NEXT:    ldr q4, [sp]
-; CHECK-NEXT:    eor z5.d, z4.d, z5.d
+; CHECK-NEXT:    mov z4.s, w8
+; CHECK-NEXT:    mov z5.s, w9
 ; CHECK-NEXT:    and z1.d, z1.d, z4.d
 ; CHECK-NEXT:    and z0.d, z0.d, z4.d
 ; CHECK-NEXT:    and z2.d, z2.d, z5.d
 ; CHECK-NEXT:    and z3.d, z3.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <8 x float>, ptr %a
   %op2 = load volatile <8 x float>, ptr %b
   %sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2
   store <8 x float> %sel, ptr %a
   ret void
 }
 
 define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov x9, #-1
-; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    fmov d3, x9
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm x8, ne
+; CHECK-NEXT:    mvn x9, x8
+; CHECK-NEXT:    mov z2.d, x8
+; CHECK-NEXT:    mov z3.d, x9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2
   ret <1 x double> %sel
 }
 
 define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    adrp x9, .LCPI8_0
 ; CHECK-NEXT:    csetm x8, ne
-; CHECK-NEXT:    stp x8, x8, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI8_0]
+; CHECK-NEXT:    mvn x9, x8
+; CHECK-NEXT:    mov z2.d, x8
+; CHECK-NEXT:    mov z3.d, x9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <2 x double> %op1, <2 x double> %op2
   ret <2 x double> %sel
 }
 
 define void @select_v4f64(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w2, #0x1
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
+; CHECK-NEXT:    mvn x9, x8
 ; CHECK-NEXT:    ldr q2, [x1]
-; CHECK-NEXT:    adrp x9, .LCPI9_0
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    stp x8, x8, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI9_0]
-; CHECK-NEXT:    ldr q5, [sp]
-; CHECK-NEXT:    eor z4.d, z5.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    and z0.d, z0.d, z5.d
-; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z4.d
+; CHECK-NEXT:    mov z4.d, x8
+; CHECK-NEXT:    mov z5.d, x9
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    and z2.d, z2.d, z5.d
+; CHECK-NEXT:    and z3.d, z3.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <4 x double>, ptr %a
   %op2 = load volatile <4 x double>, ptr %b
   %sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2
   store <4 x double> %sel, ptr %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll

 ; FCVTZU D -> H
 ;
 
 define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzu_v1f64_v1i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    mov z0.h, w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = fptoui <1 x double> %op1 to <1 x i16>
   ret <1 x i16> %res
 }
 
 define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzu_v2f64_v2i16:
 ; CHECK:       // %bb.0:

 ; FCVTZU D -> D
 ;
 
 define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzu_v1f64_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    fcvtzu x8, d0
-; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    mov z0.d, x8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = fptoui <1 x double> %op1 to <1 x i64>
   ret <1 x i64> %res
 }
 
 define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzu_v2f64_v2i64:
 ; CHECK:       // %bb.0:

 ;
 
 ; v1f64 is perfered to be widened to v4f64, so use SVE
 define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzs_v1f64_v1i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    mov z0.h, w8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = fptosi <1 x double> %op1 to <1 x i16>
   ret <1 x i16> %res
 }
 
 define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzs_v2f64_v2i16:
 ; CHECK:       // %bb.0:

 ; FCVTZS D -> D
 ;
 
 define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzs_v1f64_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    mov z0.d, x8
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = fptosi <1 x double> %op1 to <1 x i64>
   ret <1 x i64> %res
 }
 
 define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) #0 {
 ; CHECK-LABEL: fcvtzs_v2f64_v2i64:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    mov z3.s, z2.s[1]
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    fmov w9, s2
-; CHECK-NEXT:    fmov w10, s3
+; CHECK-NEXT:    fmov w8, s2
+; CHECK-NEXT:    fmov w9, s3
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    adrp x8, .LCPI0_1
-; CHECK-NEXT:    strh w9, [sp, #8]
-; CHECK-NEXT:    strh w10, [sp, #10]
-; CHECK-NEXT:    ldr d3, [sp, #8]
-; CHECK-NEXT:    ldr d4, [x8, :lo12:.LCPI0_1]
-; CHECK-NEXT:    lsl z3.h, p0/m, z3.h, z2.h
-; CHECK-NEXT:    asrr z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    strh w8, [sp, #8]
+; CHECK-NEXT:    strh w9, [sp, #10]
+; CHECK-NEXT:    ldr d2, [sp, #8]
+; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    asr z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x half> %op1, <2 x half> %op2
   ret <2 x half> %sel
 }
 
 define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v4f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
-; CHECK-NEXT:    adrp x9, .LCPI1_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI1_1]
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    asr z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    asr z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <4 x i1> %mask, <4 x half> %op1, <4 x half> %op2
   ret <4 x half> %sel
 }
 
 define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v8f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
-; CHECK-NEXT:    adrp x9, .LCPI2_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    uunpklo z2.h, z2.b
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI2_1]
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    asr z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    asr z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <8 x i1> %mask, <8 x half> %op1, <8 x half> %op2
   ret <8 x half> %sel
 }
 
 define void @select_v16f16(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI3_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    fcmeq p1.h, p0/z, z2.h, z1.h
-; CHECK-NEXT:    fcmeq p0.h, p0/z, z3.h, z0.h
-; CHECK-NEXT:    mov z5.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    fcmeq p1.h, p0/z, z1.h, z2.h
+; CHECK-NEXT:    fcmeq p0.h, p0/z, z0.h, z3.h
+; CHECK-NEXT:    mov z4.h, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    orr z0.d, z0.d, z3.d
+; CHECK-NEXT:    orr z1.d, z1.d, z2.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %mask = fcmp oeq <16 x half> %op1, %op2
   %sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op2
   store <16 x half> %sel, ptr %a
   ret void
 }
 
 define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
-; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI4_1]
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    asr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    asr z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x float> %op1, <2 x float> %op2
   ret <2 x float> %sel
 }
 
 define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v4f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI5_0
-; CHECK-NEXT:    adrp x9, .LCPI5_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    uunpklo z2.s, z2.h
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI5_1]
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    asr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    asr z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <4 x i1> %mask, <4 x float> %op1, <4 x float> %op2
   ret <4 x float> %sel
 }
 
 define void @select_v8f32(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v8f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI6_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI6_0]
-; CHECK-NEXT:    fcmeq p1.s, p0/z, z2.s, z1.s
-; CHECK-NEXT:    fcmeq p0.s, p0/z, z3.s, z0.s
-; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    fcmeq p1.s, p0/z, z1.s, z2.s
+; CHECK-NEXT:    fcmeq p0.s, p0/z, z0.s, z3.s
+; CHECK-NEXT:    mov z4.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    orr z0.d, z0.d, z3.d
+; CHECK-NEXT:    orr z1.d, z1.d, z2.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x float>, ptr %a
   %op2 = load <8 x float>, ptr %b
   %mask = fcmp oeq <8 x float> %op1, %op2
   %sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2
   store <8 x float> %sel, ptr %a
   ret void
 }
 
 define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov x9, #-1
-; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    fmov d3, x9
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm x8, ne
+; CHECK-NEXT:    mvn x9, x8
+; CHECK-NEXT:    mov z2.d, x8
+; CHECK-NEXT:    mov z3.d, x9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2
   ret <1 x double> %sel
 }
 
 define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
-; CHECK-NEXT:    adrp x9, .LCPI8_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    uunpklo z2.d, z2.s
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI8_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI8_1]
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z3.d
-; CHECK-NEXT:    asr z2.d, p0/m, z2.d, z3.d
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, #63
+; CHECK-NEXT:    asr z2.d, p0/m, z2.d, #63
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x double> %op1, <2 x double> %op2
   ret <2 x double> %sel
 }
 
 define void @select_v4f64(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v4f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI9_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI9_0]
-; CHECK-NEXT:    fcmeq p1.d, p0/z, z2.d, z1.d
-; CHECK-NEXT:    fcmeq p0.d, p0/z, z3.d, z0.d
-; CHECK-NEXT:    mov z5.d, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.d, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    fcmeq p1.d, p0/z, z1.d, z2.d
+; CHECK-NEXT:    fcmeq p0.d, p0/z, z0.d, z3.d
+; CHECK-NEXT:    mov z4.d, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    orr z0.d, z0.d, z3.d
+; CHECK-NEXT:    orr z1.d, z1.d, z2.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x double>, ptr %a
   %op2 = load <4 x double>, ptr %b
   %mask = fcmp oeq <4 x double> %op1, %op2
   %sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2
   store <4 x double> %sel, ptr %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll

; CHECK-NEXT:    ret
     %r = insertelement <8 x i32> %op1, i32 5, i64 7
     ret <8 x i32> %r
 }
 
 ;i64
 define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) #0 {
 ; CHECK-LABEL: insertelement_v1i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5
-; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    mov z0.d, #5 // =0x5
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
     %r = insertelement <1 x i64> %op1, i64 5, i64 0
     ret <1 x i64> %r
 }
 
 define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) #0 {
 ; CHECK-LABEL: insertelement_v2i64:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll

 
 ;
 ; ABS
 ;
 
 define <4 x i8> @abs_v4i8(<4 x i8> %op1) #0 {
 ; CHECK-LABEL: abs_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI42_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI42_0]
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    abs z0.h, p0/m, z0.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %op1, i1 false)
   ret <4 x i8> %res
 }
 
 define <8 x i8> @abs_v8i8(<8 x i8> %op1) #0 {
; CHECK-NEXT:    ret
   %res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %op1, i1 false)
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @abs_v2i16(<2 x i16> %op1) #0 {
 ; CHECK-LABEL: abs_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI46_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI46_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    abs z0.s, p0/m, z0.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %op1, i1 false)
   ret <2 x i16> %res
 }
 
 define <4 x i16> @abs_v4i16(<4 x i16> %op1) #0 {

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; SDIV
 ;
 
 define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: sdiv_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    asr z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z2.h
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    sunpklo z1.s, z1.h
 ; CHECK-NEXT:    sunpklo z0.s, z0.h
 ; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = sdiv <4 x i8> %op1, %op2
; CHECK-NEXT:    ret
   %res = sdiv <32 x i8> %op1, %op2
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
 ; CHECK-LABEL: sdiv_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    asr z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #16
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    asr z1.s, p0/m, z1.s, #16
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = sdiv <2 x i16> %op1, %op2
   ret <2 x i16> %res
 }
 
 define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {

 
 ;
 ; UDIV
 ;
 
 define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: udiv_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI14_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
+; CHECK-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEXT:    uunpklo z1.s, z1.h
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
 ; CHECK-NEXT:    udiv z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = udiv <4 x i8> %op1, %op2
   ret <4 x i8> %res
; CHECK-NEXT:    ret
   %res = udiv <32 x i8> %op1, %op2
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
 ; CHECK-LABEL: udiv_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI18_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI18_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
+; CHECK-NEXT:    and z1.s, z1.s, #0xffff
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
 ; CHECK-NEXT:    udiv z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = udiv <2 x i16> %op1, %op2
   ret <2 x i16> %res
 }
 
 define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
; CHECK-NEXT:    ret
   %res = udiv <4 x i64> %op1, %op2
   store <4 x i64> %res, <4 x i64>* %a
   ret void
 }
 
 define void @udiv_constantsplat_v8i32(<8 x i32>* %a)  #0 {
 ; CHECK-LABEL: udiv_constantsplat_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI28_0
-; CHECK-NEXT:    adrp x9, .LCPI28_1
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI28_0]
-; CHECK-NEXT:    adrp x8, .LCPI28_2
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI28_1]
-; CHECK-NEXT:    movprfx z5, z1
-; CHECK-NEXT:    umulh z5.s, p0/m, z5.s, z0.s
-; CHECK-NEXT:    sub z1.s, z1.s, z5.s
-; CHECK-NEXT:    umulh z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI28_2]
-; CHECK-NEXT:    sub z2.s, z2.s, z0.s
-; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, z3.s
-; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    add z1.s, z1.s, z5.s
-; CHECK-NEXT:    add z0.s, z2.s, z0.s
-; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, z4.s
-; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z4.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov w8, #8969
+; CHECK-NEXT:    ptrue p0.s, vl4
+; CHECK-NEXT:    movk w8, #22765, lsl #16
+; CHECK-NEXT:    mov z2.s, w8
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    umulh z3.s, p0/m, z3.s, z2.s
+; CHECK-NEXT:    umulh z2.s, p0/m, z2.s, z1.s
+; CHECK-NEXT:    sub z0.s, z0.s, z3.s
+; CHECK-NEXT:    sub z1.s, z1.s, z2.s
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #1
+; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, #1
+; CHECK-NEXT:    add z0.s, z0.s, z3.s
+; CHECK-NEXT:    add z1.s, z1.s, z2.s
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #6
+; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, #6
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, <8 x i32>* %a
   %res = udiv <8 x i32> %op1, <i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95>
   store <8 x i32> %res, <8 x i32>* %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; sext i1 -> i32
 ;
 
 ; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg
 ; type's element type is not byte based and thus cannot be lowered directly to
 ; an SVE instruction.
 define void @sext_v8i1_v8i32(<8 x i1> %a, <8 x i32>* %out) #0 {
 ; CHECK-LABEL: sext_v8i1_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    uunpklo z0.h, z0.b
-; CHECK-NEXT:    uunpklo z2.s, z0.h
+; CHECK-NEXT:    uunpklo z1.s, z0.h
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z1.s
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z2.s, p0/m, z2.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    stp q2, q0, [x0]
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %b = sext <8 x i1> %a to <8 x i32>
   store <8 x i32> %b, <8 x i32>* %out
   ret void
 }
 
 ;
 ; sext i3 -> i64
 ;
 
 ; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg
 ; type's element type is not power-of-2 based and thus cannot be lowered
 ; directly to an SVE instruction.
 define void @sext_v4i3_v4i64(<4 x i3> %a, <4 x i64>* %out) #0 {
 ; CHECK-LABEL: sext_v4i3_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    uunpklo z2.d, z0.s
+; CHECK-NEXT:    uunpklo z1.d, z0.s
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    asr z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    stp q2, q0, [x0]
+; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, #61
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #61
+; CHECK-NEXT:    asr z1.d, p0/m, z1.d, #61
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #61
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %b = sext <4 x i3> %a to <4 x i64>
   store <4 x i64> %b, <4 x i64>* %out
   ret void
 }
 
 ;
 ; sext i8 -> i16

 ;
 
 ; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The sign
 ; extend is a two step process where the container is any_extend'd with the
 ; result feeding an inreg sign extend.
 define void @sext_v4i8_v4i64(<4 x i8> %a, <4 x i64>* %out) #0 {
 ; CHECK-LABEL: sext_v4i8_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI7_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    uunpklo z2.d, z0.s
+; CHECK-NEXT:    uunpklo z1.d, z0.s
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    asr z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    stp q2, q0, [x0]
+; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, #56
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #56
+; CHECK-NEXT:    asr z1.d, p0/m, z1.d, #56
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #56
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %b = sext <4 x i8> %a to <4 x i64>
   store <4 x i64>%b, <4 x i64>* %out
   ret void
 }
 
 define void @sext_v8i8_v8i64(<8 x i8> %a, <8 x i64>* %out) #0 {
 ; CHECK-LABEL: sext_v8i8_v8i64:

 ;
 
 ; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The zero
 ; extend is a two step process where the container is zero_extend_inreg'd with
 ; the result feeding a normal zero extend from halfs to doublewords.
 define void @zext_v4i8_v4i64(<4 x i8> %a, <4 x i64>* %out) #0 {
 ; CHECK-LABEL: zext_v4i8_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI23_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI23_0]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
 ; CHECK-NEXT:    uunpklo z1.d, z0.s
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
 ; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %b = zext <4 x i8> %a to <4 x i64>
   store <4 x i64>%b, <4 x i64>* %out

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll

 
 ;
 ; ADD
 ;
 
 define void @add_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: add_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    add z1.b, z1.b, z0.b
-; CHECK-NEXT:    add z0.b, z2.b, z0.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    add z0.b, z0.b, #7 // =0x7
+; CHECK-NEXT:    add z1.b, z1.b, #7 // =0x7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i32 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = add <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @add_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: add_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    add z1.h, z1.h, z0.h
-; CHECK-NEXT:    add z0.h, z2.h, z0.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    add z0.h, z0.h, #15 // =0xf
+; CHECK-NEXT:    add z1.h, z1.h, #15 // =0xf
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = add <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @add_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: add_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    add z1.s, z1.s, z0.s
-; CHECK-NEXT:    add z0.s, z2.s, z0.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    add z0.s, z0.s, #31 // =0x1f
+; CHECK-NEXT:    add z1.s, z1.s, #31 // =0x1f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = add <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @add_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: add_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI3_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    add z1.d, z1.d, z0.d
-; CHECK-NEXT:    add z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    add z0.d, z0.d, #63 // =0x3f
+; CHECK-NEXT:    add z1.d, z1.d, #63 // =0x3f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = add <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; AND
 ;
 
 define void @and_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: and_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    and z1.d, z1.d, z0.d
-; CHECK-NEXT:    and z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    and z0.b, z0.b, #0x7
+; CHECK-NEXT:    and z1.b, z1.b, #0x7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i32 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = and <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @and_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: and_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI5_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    and z1.d, z1.d, z0.d
-; CHECK-NEXT:    and z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    and z0.h, z0.h, #0xf
+; CHECK-NEXT:    and z1.h, z1.h, #0xf
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = and <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @and_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: and_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI6_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI6_0]
-; CHECK-NEXT:    and z1.d, z1.d, z0.d
-; CHECK-NEXT:    and z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    and z0.s, z0.s, #0x1f
+; CHECK-NEXT:    and z1.s, z1.s, #0x1f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = and <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @and_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: and_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI7_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI7_0]
-; CHECK-NEXT:    and z1.d, z1.d, z0.d
-; CHECK-NEXT:    and z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    and z0.d, z0.d, #0x3f
+; CHECK-NEXT:    and z1.d, z1.d, #0x3f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = and <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; ASHR
 ;
 
 define void @ashr_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: ashr_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI8_0]
-; CHECK-NEXT:    asr z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    asrr z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z1.b, p0/m, z1.b, #7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i32 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = ashr <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @ashr_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: ashr_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI9_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI9_0]
-; CHECK-NEXT:    asr z1.h, p0/m, z1.h, z0.h
-; CHECK-NEXT:    asrr z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #15
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = ashr <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @ashr_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: ashr_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI10_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI10_0]
-; CHECK-NEXT:    asr z1.s, p0/m, z1.s, z0.s
-; CHECK-NEXT:    asrr z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = ashr <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @ashr_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: ashr_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI11_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI11_0]
-; CHECK-NEXT:    asr z1.d, p0/m, z1.d, z0.d
-; CHECK-NEXT:    asrr z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    asr z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = ashr <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; ICMP
 ;
 
 define void @icmp_eq_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: icmp_eq_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI12_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI12_0]
-; CHECK-NEXT:    cmpeq p1.b, p0/z, z1.b, z0.b
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z2.b, z0.b
+; CHECK-NEXT:    cmpeq p1.b, p0/z, z0.b, #7
 ; CHECK-NEXT:    mov z0.b, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    cmpeq p0.b, p0/z, z1.b, #7
 ; CHECK-NEXT:    mov z1.b, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %cmp = icmp eq <32 x i8> %op1, %op2
   %res = sext <32 x i1> %cmp to <32 x i8>
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @icmp_sge_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: icmp_sge_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI13_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI13_0]
-; CHECK-NEXT:    cmpge p1.h, p0/z, z1.h, z0.h
-; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, z0.h
+; CHECK-NEXT:    cmpge p1.h, p0/z, z0.h, #15
 ; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #15
 ; CHECK-NEXT:    mov z1.h, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %cmp = icmp sge <16 x i16> %op1, %op2
   %res = sext <16 x i1> %cmp to <16 x i16>
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @icmp_sgt_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: icmp_sgt_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI14_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    cmpgt p1.s, p0/z, z1.s, z0.s
-; CHECK-NEXT:    cmpgt p0.s, p0/z, z2.s, z0.s
+; CHECK-NEXT:    cmpgt p1.s, p0/z, z0.s, #-8
 ; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    cmpgt p0.s, p0/z, z1.s, #-8
 ; CHECK-NEXT:    mov z1.s, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 -8, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %cmp = icmp sgt <8 x i32> %op1, %op2
   %res = sext <8 x i1> %cmp to <8 x i32>
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @icmp_ult_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: icmp_ult_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI15_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI15_0]
-; CHECK-NEXT:    cmphi p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    cmphi p0.d, p0/z, z0.d, z2.d
+; CHECK-NEXT:    cmplo p1.d, p0/z, z0.d, #63
 ; CHECK-NEXT:    mov z0.d, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    cmplo p0.d, p0/z, z1.d, #63
 ; CHECK-NEXT:    mov z1.d, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %cmp = icmp ult <4 x i64> %op1, %op2
   %res = sext <4 x i1> %cmp to <4 x i64>
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; LSHR
 ;
 
 define void @lshr_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: lshr_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI16_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI16_0]
-; CHECK-NEXT:    lsr z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    lsrr z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsr z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    lsr z1.b, p0/m, z1.b, #7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = lshr <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @lshr_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: lshr_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI17_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI17_0]
-; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, z0.h
-; CHECK-NEXT:    lsrr z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, #15
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = lshr <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @lshr_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: lshr_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI18_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI18_0]
-; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, z0.s
-; CHECK-NEXT:    lsrr z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = lshr <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @lshr_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: lshr_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI19_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI19_0]
-; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, z0.d
-; CHECK-NEXT:    lsrr z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsr z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = lshr <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; MUL
 ;
 
 define void @mul_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: mul_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI20_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.b, #7 // =0x7
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI20_0]
-; CHECK-NEXT:    mul z1.b, p0/m, z1.b, z0.b
 ; CHECK-NEXT:    mul z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    mul z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = mul <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @mul_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: mul_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI21_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.h, #15 // =0xf
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI21_0]
-; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z0.h
 ; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = mul <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @mul_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: mul_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI22_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.s, #31 // =0x1f
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI22_0]
-; CHECK-NEXT:    mul z1.s, p0/m, z1.s, z0.s
 ; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    mul z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = mul <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @mul_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: mul_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI23_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.d, #63 // =0x3f
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI23_0]
-; CHECK-NEXT:    mul z1.d, p0/m, z1.d, z0.d
 ; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    mul z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = mul <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; OR
 ;
 
 define void @or_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: or_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI24_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI24_0]
-; CHECK-NEXT:    orr z1.d, z1.d, z0.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    orr z0.b, z0.b, #0x7
+; CHECK-NEXT:    orr z1.b, z1.b, #0x7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = or <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @or_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: or_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI25_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI25_0]
-; CHECK-NEXT:    orr z1.d, z1.d, z0.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    orr z0.h, z0.h, #0xf
+; CHECK-NEXT:    orr z1.h, z1.h, #0xf
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = or <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @or_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: or_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI26_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI26_0]
-; CHECK-NEXT:    orr z1.d, z1.d, z0.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    orr z0.s, z0.s, #0x1f
+; CHECK-NEXT:    orr z1.s, z1.s, #0x1f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = or <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @or_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: or_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI27_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI27_0]
-; CHECK-NEXT:    orr z1.d, z1.d, z0.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    orr z0.d, z0.d, #0x3f
+; CHECK-NEXT:    orr z1.d, z1.d, #0x3f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = or <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; SHL
 ;
 
 define void @shl_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: shl_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI28_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI28_0]
-; CHECK-NEXT:    lsl z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    lslr z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    lsl z1.b, p0/m, z1.b, #7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = shl <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @shl_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: shl_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI29_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI29_0]
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z0.h
-; CHECK-NEXT:    lslr z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #15
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = shl <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @shl_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: shl_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI30_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI30_0]
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z0.s
-; CHECK-NEXT:    lslr z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = shl <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @shl_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: shl_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI31_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI31_0]
-; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, z0.d
-; CHECK-NEXT:    lslr z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = shl <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; SMAX
 ;
 
 define void @smax_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: smax_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI32_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.b, #7 // =0x7
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI32_0]
-; CHECK-NEXT:    smax z1.b, p0/m, z1.b, z0.b
 ; CHECK-NEXT:    smax z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smax z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @smax_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: smax_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI33_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.h, #15 // =0xf
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI33_0]
-; CHECK-NEXT:    smax z1.h, p0/m, z1.h, z0.h
 ; CHECK-NEXT:    smax z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smax z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2)
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @smax_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: smax_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI34_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.s, #31 // =0x1f
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI34_0]
-; CHECK-NEXT:    smax z1.s, p0/m, z1.s, z0.s
 ; CHECK-NEXT:    smax z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smax z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2)
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @smax_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: smax_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI35_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.d, #63 // =0x3f
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI35_0]
-; CHECK-NEXT:    smax z1.d, p0/m, z1.d, z0.d
 ; CHECK-NEXT:    smax z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smax z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2)
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; SMIN
 ;
 
 define void @smin_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: smin_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI36_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.b, #7 // =0x7
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI36_0]
-; CHECK-NEXT:    smin z1.b, p0/m, z1.b, z0.b
 ; CHECK-NEXT:    smin z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smin z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @smin_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: smin_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI37_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.h, #15 // =0xf
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI37_0]
-; CHECK-NEXT:    smin z1.h, p0/m, z1.h, z0.h
 ; CHECK-NEXT:    smin z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smin z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @smin_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: smin_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI38_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.s, #31 // =0x1f
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI38_0]
-; CHECK-NEXT:    smin z1.s, p0/m, z1.s, z0.s
 ; CHECK-NEXT:    smin z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @smin_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: smin_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI39_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.d, #63 // =0x3f
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI39_0]
-; CHECK-NEXT:    smin z1.d, p0/m, z1.d, z0.d
 ; CHECK-NEXT:    smin z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; SUB
 ;
 
 define void @sub_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: sub_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI40_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI40_0]
-; CHECK-NEXT:    sub z1.b, z1.b, z0.b
-; CHECK-NEXT:    sub z0.b, z2.b, z0.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    sub z0.b, z0.b, #7 // =0x7
+; CHECK-NEXT:    sub z1.b, z1.b, #7 // =0x7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = sub <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @sub_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: sub_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI41_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI41_0]
-; CHECK-NEXT:    sub z1.h, z1.h, z0.h
-; CHECK-NEXT:    sub z0.h, z2.h, z0.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    sub z0.h, z0.h, #15 // =0xf
+; CHECK-NEXT:    sub z1.h, z1.h, #15 // =0xf
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = sub <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @sub_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: sub_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI42_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI42_0]
-; CHECK-NEXT:    sub z1.s, z1.s, z0.s
-; CHECK-NEXT:    sub z0.s, z2.s, z0.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    sub z0.s, z0.s, #31 // =0x1f
+; CHECK-NEXT:    sub z1.s, z1.s, #31 // =0x1f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = sub <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @sub_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: sub_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI43_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI43_0]
-; CHECK-NEXT:    sub z1.d, z1.d, z0.d
-; CHECK-NEXT:    sub z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    sub z0.d, z0.d, #63 // =0x3f
+; CHECK-NEXT:    sub z1.d, z1.d, #63 // =0x3f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = sub <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; UMAX
 ;
 
 define void @umax_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: umax_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI44_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.b, #7 // =0x7
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI44_0]
-; CHECK-NEXT:    umax z1.b, p0/m, z1.b, z0.b
 ; CHECK-NEXT:    umax z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umax z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @umax_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: umax_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI45_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.h, #15 // =0xf
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI45_0]
-; CHECK-NEXT:    umax z1.h, p0/m, z1.h, z0.h
 ; CHECK-NEXT:    umax z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umax z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2)
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @umax_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: umax_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI46_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.s, #31 // =0x1f
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI46_0]
-; CHECK-NEXT:    umax z1.s, p0/m, z1.s, z0.s
 ; CHECK-NEXT:    umax z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umax z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2)
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @umax_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: umax_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI47_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.d, #63 // =0x3f
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI47_0]
-; CHECK-NEXT:    umax z1.d, p0/m, z1.d, z0.d
 ; CHECK-NEXT:    umax z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umax z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2)
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; UMIN
 ;
 
 define void @umin_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: umin_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI48_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.b, #7 // =0x7
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI48_0]
-; CHECK-NEXT:    umin z1.b, p0/m, z1.b, z0.b
 ; CHECK-NEXT:    umin z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umin z1.b, p0/m, z1.b, z2.b
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @umin_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: umin_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI49_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.h, #15 // =0xf
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI49_0]
-; CHECK-NEXT:    umin z1.h, p0/m, z1.h, z0.h
 ; CHECK-NEXT:    umin z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umin z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @umin_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: umin_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI50_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.s, #31 // =0x1f
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI50_0]
-; CHECK-NEXT:    umin z1.s, p0/m, z1.s, z0.s
 ; CHECK-NEXT:    umin z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @umin_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: umin_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI51_0
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    mov z2.d, #63 // =0x3f
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI51_0]
-; CHECK-NEXT:    umin z1.d, p0/m, z1.d, z0.d
 ; CHECK-NEXT:    umin z0.d, p0/m, z0.d, z2.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    umin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
   store <4 x i64> %res, ptr %a
   ret void
 }
 
 ;
 ; XOR
 ;
 
 define void @xor_v32i8(ptr %a) #0 {
 ; CHECK-LABEL: xor_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI52_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI52_0]
-; CHECK-NEXT:    eor z1.d, z1.d, z0.d
-; CHECK-NEXT:    eor z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    eor z0.b, z0.b, #0x7
+; CHECK-NEXT:    eor z1.b, z1.b, #0x7
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %ins = insertelement <32 x i8> undef, i8 7, i64 0
   %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer
   %res = xor <32 x i8> %op1, %op2
   store <32 x i8> %res, ptr %a
   ret void
 }
 
 define void @xor_v16i16(ptr %a) #0 {
 ; CHECK-LABEL: xor_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI53_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI53_0]
-; CHECK-NEXT:    eor z1.d, z1.d, z0.d
-; CHECK-NEXT:    eor z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    eor z0.h, z0.h, #0xf
+; CHECK-NEXT:    eor z1.h, z1.h, #0xf
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %ins = insertelement <16 x i16> undef, i16 15, i64 0
   %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer
   %res = xor <16 x i16> %op1, %op2
   store <16 x i16> %res, ptr %a
   ret void
 }
 
 define void @xor_v8i32(ptr %a) #0 {
 ; CHECK-LABEL: xor_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI54_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI54_0]
-; CHECK-NEXT:    eor z1.d, z1.d, z0.d
-; CHECK-NEXT:    eor z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    eor z0.s, z0.s, #0x1f
+; CHECK-NEXT:    eor z1.s, z1.s, #0x1f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %ins = insertelement <8 x i32> undef, i32 31, i64 0
   %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer
   %res = xor <8 x i32> %op1, %op2
   store <8 x i32> %res, ptr %a
   ret void
 }
 
 define void @xor_v4i64(ptr %a) #0 {
 ; CHECK-LABEL: xor_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI55_0
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI55_0]
-; CHECK-NEXT:    eor z1.d, z1.d, z0.d
-; CHECK-NEXT:    eor z0.d, z2.d, z0.d
-; CHECK-NEXT:    stp q1, q0, [x0]
+; CHECK-NEXT:    ldp q0, q1, [x0]
+; CHECK-NEXT:    eor z0.d, z0.d, #0x3f
+; CHECK-NEXT:    eor z1.d, z1.d, #0x3f
+; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %ins = insertelement <4 x i64> undef, i64 63, i64 0
   %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
   %res = xor <4 x i64> %op1, %op2
   store <4 x i64> %res, ptr %a
   ret void
 }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 ; This test only tests the legal types for a given vector width, as mulh nodes
 ; do not get generated for non-legal types.
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; SMULH
 ;
 
 define <4 x i8> @smulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: smulh_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    adrp x8, .LCPI0_1
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI0_1]
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    asr z1.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #8
 ; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z3.h
+; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, #4
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i16> undef, i16 4, i64 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> undef, <4 x i32> zeroinitializer
   %1 = sext <4 x i8> %op1 to <4 x i16>
   %2 = sext <4 x i8> %op2 to <4 x i16>
   %mul = mul <4 x i16> %1, %2
   %shr = lshr <4 x i16> %mul, <i16 4, i16 4, i16 4, i16 4>
; CHECK-NEXT:    ret
   %res = trunc <16 x i16> %shr to <16 x i8>
   ret <16 x i8> %res
 }
 
 define void @smulh_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
 ; CHECK-LABEL: smulh_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
-; CHECK-NEXT:    adrp x8, .LCPI3_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    sunpklo z4.h, z1.b
 ; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
 ; CHECK-NEXT:    sunpklo z1.h, z1.b
 ; CHECK-NEXT:    ldp q3, q2, [x1]
 ; CHECK-NEXT:    sunpklo z5.h, z0.b
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
 ; CHECK-NEXT:    sunpklo z0.h, z0.b
 ; CHECK-NEXT:    sunpklo z6.h, z3.b
 ; CHECK-NEXT:    ext z3.b, z3.b, z3.b, #8
 ; CHECK-NEXT:    sunpklo z3.h, z3.b
 ; CHECK-NEXT:    sunpklo z7.h, z2.b
 ; CHECK-NEXT:    ext z2.b, z2.b, z2.b, #8
 ; CHECK-NEXT:    sunpklo z2.h, z2.b
 ; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z3.h
 ; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_0]
+; CHECK-NEXT:    movprfx z2, z5
+; CHECK-NEXT:    mul z2.h, p0/m, z2.h, z7.h
 ; CHECK-NEXT:    movprfx z3, z4
 ; CHECK-NEXT:    mul z3.h, p0/m, z3.h, z6.h
-; CHECK-NEXT:    mul z5.h, p0/m, z5.h, z7.h
-; CHECK-NEXT:    movprfx z4, z5
-; CHECK-NEXT:    lsr z4.h, p0/m, z4.h, z2.h
-; CHECK-NEXT:    lsr z3.h, p0/m, z3.h, z2.h
-; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z2.h
+; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    lsr z3.h, p0/m, z3.h, #8
+; CHECK-NEXT:    lsr z2.h, p0/m, z2.h, #8
+; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    ptrue p0.b, vl8
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
 ; CHECK-NEXT:    uzp1 z1.b, z1.b, z1.b
-; CHECK-NEXT:    uzp1 z2.b, z3.b, z3.b
-; CHECK-NEXT:    uzp1 z3.b, z4.b, z4.b
-; CHECK-NEXT:    splice z2.b, p0, z2.b, z1.b
-; CHECK-NEXT:    splice z3.b, p0, z3.b, z0.b
-; CHECK-NEXT:    stp q2, q3, [x0]
+; CHECK-NEXT:    uzp1 z3.b, z3.b, z3.b
+; CHECK-NEXT:    uzp1 z2.b, z2.b, z2.b
+; CHECK-NEXT:    splice z3.b, p0, z3.b, z1.b
+; CHECK-NEXT:    splice z2.b, p0, z2.b, z0.b
+; CHECK-NEXT:    stp q3, q2, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, <32 x i8>* %a
   %op2 = load <32 x i8>, <32 x i8>* %b
   %1 = sext <32 x i8> %op1 to <32 x i16>
   %2 = sext <32 x i8> %op2 to <32 x i16>
   %mul = mul <32 x i16> %1, %2
   %shr = lshr <32 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   %res = trunc <32 x i16> %shr to <32 x i8>
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @smulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
 ; CHECK-LABEL: smulh_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    asr z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #16
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    asr z1.s, p0/m, z1.s, #16
 ; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %1 = sext <2 x i16> %op1 to <2 x i32>
   %2 = sext <2 x i16> %op2 to <2 x i32>
   %mul = mul <2 x i32> %1, %2
   %shr = lshr <2 x i32> %mul, <i32 16, i32 16>
   %res = trunc <2 x i32> %shr to <2 x i16>
   ret <2 x i16> %res

 
 ;
 ; UMULH
 ;
 
 define <4 x i8> @umulh_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: umulh_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI14_0
-; CHECK-NEXT:    adrp x9, .LCPI14_1
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI14_1]
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
+; CHECK-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z3.h
+; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, #4
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %1 = zext <4 x i8> %op1 to <4 x i16>
   %2 = zext <4 x i8> %op2 to <4 x i16>
   %mul = mul <4 x i16> %1, %2
   %shr = lshr <4 x i16> %mul, <i16 4, i16 4, i16 4, i16 4>
   %res = trunc <4 x i16> %shr to <4 x i8>
   ret <4 x i8> %res
; CHECK-NEXT:    ret
   %res = trunc <16 x i16> %shr to <16 x i8>
   ret <16 x i8> %res
 }
 
 define void @umulh_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
 ; CHECK-LABEL: umulh_v32i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q1, q0, [x0]
-; CHECK-NEXT:    adrp x8, .LCPI17_0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    uunpklo z4.h, z1.b
 ; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
 ; CHECK-NEXT:    uunpklo z1.h, z1.b
 ; CHECK-NEXT:    ldp q3, q2, [x1]
 ; CHECK-NEXT:    uunpklo z5.h, z0.b
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
 ; CHECK-NEXT:    uunpklo z0.h, z0.b
 ; CHECK-NEXT:    uunpklo z6.h, z3.b
 ; CHECK-NEXT:    ext z3.b, z3.b, z3.b, #8
 ; CHECK-NEXT:    uunpklo z3.h, z3.b
 ; CHECK-NEXT:    uunpklo z7.h, z2.b
 ; CHECK-NEXT:    ext z2.b, z2.b, z2.b, #8
 ; CHECK-NEXT:    uunpklo z2.h, z2.b
 ; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z3.h
 ; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI17_0]
+; CHECK-NEXT:    movprfx z2, z5
+; CHECK-NEXT:    mul z2.h, p0/m, z2.h, z7.h
 ; CHECK-NEXT:    movprfx z3, z4
 ; CHECK-NEXT:    mul z3.h, p0/m, z3.h, z6.h
-; CHECK-NEXT:    mul z5.h, p0/m, z5.h, z7.h
-; CHECK-NEXT:    movprfx z4, z5
-; CHECK-NEXT:    lsr z4.h, p0/m, z4.h, z2.h
-; CHECK-NEXT:    lsr z3.h, p0/m, z3.h, z2.h
-; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z2.h
+; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    lsr z3.h, p0/m, z3.h, #8
+; CHECK-NEXT:    lsr z2.h, p0/m, z2.h, #8
+; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    ptrue p0.b, vl8
 ; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
 ; CHECK-NEXT:    uzp1 z1.b, z1.b, z1.b
-; CHECK-NEXT:    uzp1 z2.b, z3.b, z3.b
-; CHECK-NEXT:    uzp1 z3.b, z4.b, z4.b
-; CHECK-NEXT:    splice z2.b, p0, z2.b, z1.b
-; CHECK-NEXT:    splice z3.b, p0, z3.b, z0.b
-; CHECK-NEXT:    stp q2, q3, [x0]
+; CHECK-NEXT:    uzp1 z3.b, z3.b, z3.b
+; CHECK-NEXT:    uzp1 z2.b, z2.b, z2.b
+; CHECK-NEXT:    splice z3.b, p0, z3.b, z1.b
+; CHECK-NEXT:    splice z2.b, p0, z2.b, z0.b
+; CHECK-NEXT:    stp q3, q2, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, <32 x i8>* %a
   %op2 = load <32 x i8>, <32 x i8>* %b
   %1 = zext <32 x i8> %op1 to <32 x i16>
   %2 = zext <32 x i8> %op2 to <32 x i16>
   %mul = mul <32 x i16> %1, %2
   %shr = lshr <32 x i16> %mul, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   %res = trunc <32 x i16> %shr to <32 x i8>
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @umulh_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
 ; CHECK-LABEL: umulh_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI18_0
-; CHECK-NEXT:    adrp x9, .LCPI18_1
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI18_0]
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI18_1]
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
+; CHECK-NEXT:    and z1.s, z1.s, #0xffff
 ; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z3.s
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %1 = zext <2 x i16> %op1 to <2 x i32>
   %2 = zext <2 x i16> %op2 to <2 x i32>
   %mul = mul <2 x i32> %1, %2
   %shr = lshr <2 x i32> %mul, <i32 16, i32 16>
   %res = trunc <2 x i32> %shr to <2 x i16>
   ret <2 x i16> %res

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; SREM
 ;
 
 define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: srem_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    ptrue p1.s, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    asr z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z2.h
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    sunpklo z2.s, z1.h
 ; CHECK-NEXT:    sunpklo z3.s, z0.h
 ; CHECK-NEXT:    sdivr z2.s, p1/m, z2.s, z3.s
 ; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
 ; CHECK-NEXT:    mls z0.h, p0/m, z2.h, z1.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = srem <4 x i8> %op1, %op2

 
 ;
 ; UREM
 ;
 
 define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: urem_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI13_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI13_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
+; CHECK-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEXT:    uunpklo z2.s, z1.h
 ; CHECK-NEXT:    uunpklo z3.s, z0.h
 ; CHECK-NEXT:    udivr z2.s, p0/m, z2.s, z3.s
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
 ; CHECK-NEXT:    mls z0.h, p0/m, z2.h, z1.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI0_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI0_0]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.h, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <4 x i8> %op1, <4 x i8> %op2
   ret <4 x i8> %sel
 }
 
 define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v8i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI1_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI1_0]
-; CHECK-NEXT:    strb w8, [sp, #15]
-; CHECK-NEXT:    strb w8, [sp, #14]
-; CHECK-NEXT:    strb w8, [sp, #13]
-; CHECK-NEXT:    strb w8, [sp, #12]
-; CHECK-NEXT:    strb w8, [sp, #11]
-; CHECK-NEXT:    strb w8, [sp, #10]
-; CHECK-NEXT:    strb w8, [sp, #9]
-; CHECK-NEXT:    strb w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.b, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <8 x i8> %op1, <8 x i8> %op2
   ret <8 x i8> %sel
 }
 
 define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI2_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI2_0]
-; CHECK-NEXT:    strb w8, [sp, #15]
-; CHECK-NEXT:    strb w8, [sp, #14]
-; CHECK-NEXT:    strb w8, [sp, #13]
-; CHECK-NEXT:    strb w8, [sp, #12]
-; CHECK-NEXT:    strb w8, [sp, #11]
-; CHECK-NEXT:    strb w8, [sp, #10]
-; CHECK-NEXT:    strb w8, [sp, #9]
-; CHECK-NEXT:    strb w8, [sp, #8]
-; CHECK-NEXT:    strb w8, [sp, #7]
-; CHECK-NEXT:    strb w8, [sp, #6]
-; CHECK-NEXT:    strb w8, [sp, #5]
-; CHECK-NEXT:    strb w8, [sp, #4]
-; CHECK-NEXT:    strb w8, [sp, #3]
-; CHECK-NEXT:    strb w8, [sp, #2]
-; CHECK-NEXT:    strb w8, [sp, #1]
-; CHECK-NEXT:    strb w8, [sp]
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.b, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <16 x i8> %op1, <16 x i8> %op2
   ret <16 x i8> %sel
 }
 
 define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w2, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI3_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
 ; CHECK-NEXT:    ldr q2, [x1]
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    strb w8, [sp, #15]
-; CHECK-NEXT:    strb w8, [sp, #14]
-; CHECK-NEXT:    ldr q5, [x9, :lo12:.LCPI3_0]
-; CHECK-NEXT:    strb w8, [sp, #13]
-; CHECK-NEXT:    strb w8, [sp, #12]
-; CHECK-NEXT:    strb w8, [sp, #11]
-; CHECK-NEXT:    strb w8, [sp, #10]
-; CHECK-NEXT:    strb w8, [sp, #9]
-; CHECK-NEXT:    strb w8, [sp, #8]
-; CHECK-NEXT:    strb w8, [sp, #7]
-; CHECK-NEXT:    strb w8, [sp, #6]
-; CHECK-NEXT:    strb w8, [sp, #5]
-; CHECK-NEXT:    strb w8, [sp, #4]
-; CHECK-NEXT:    strb w8, [sp, #3]
-; CHECK-NEXT:    strb w8, [sp, #2]
-; CHECK-NEXT:    strb w8, [sp, #1]
-; CHECK-NEXT:    strb w8, [sp]
-; CHECK-NEXT:    ldr q4, [sp]
-; CHECK-NEXT:    eor z5.d, z4.d, z5.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    mov z4.b, w8
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
 ; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    and z3.d, z3.d, z5.d
+; CHECK-NEXT:    bic z3.d, z3.d, z4.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <32 x i8>, ptr %a
   %op2 = load volatile <32 x i8>, ptr %b
   %sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op2
   store <32 x i8> %sel, ptr %a
   ret void
 }
 
 define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI4_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI4_0]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mvn w9, w8
+; CHECK-NEXT:    mov z2.s, w8
+; CHECK-NEXT:    mov z3.s, w9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <2 x i16> %op1, <2 x i16> %op2
   ret <2 x i16> %sel
 }
 
 define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI5_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI5_0]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.h, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <4 x i16> %op1, <4 x i16> %op2
   ret <4 x i16> %sel
 }
 
 define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI6_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI6_0]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    strh w8, [sp, #6]
-; CHECK-NEXT:    strh w8, [sp, #4]
-; CHECK-NEXT:    strh w8, [sp, #2]
-; CHECK-NEXT:    strh w8, [sp]
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mov z2.h, w8
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <8 x i16> %op1, <8 x i16> %op2
   ret <8 x i16> %sel
 }
 
 define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w2, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI7_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
 ; CHECK-NEXT:    ldr q2, [x1]
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    strh w8, [sp, #14]
-; CHECK-NEXT:    strh w8, [sp, #12]
-; CHECK-NEXT:    ldr q5, [x9, :lo12:.LCPI7_0]
-; CHECK-NEXT:    strh w8, [sp, #10]
-; CHECK-NEXT:    strh w8, [sp, #8]
-; CHECK-NEXT:    strh w8, [sp, #6]
-; CHECK-NEXT:    strh w8, [sp, #4]
-; CHECK-NEXT:    strh w8, [sp, #2]
-; CHECK-NEXT:    strh w8, [sp]
-; CHECK-NEXT:    ldr q4, [sp]
-; CHECK-NEXT:    eor z5.d, z4.d, z5.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    mov z4.h, w8
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
 ; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    and z3.d, z3.d, z5.d
+; CHECK-NEXT:    bic z3.d, z3.d, z4.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <16 x i16>, ptr %a
   %op2 = load volatile <16 x i16>, ptr %b
   %sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2
   store <16 x i16> %sel, ptr %a
   ret void
 }
 
 define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI8_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI8_0]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    ldr d2, [sp, #8]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mvn w9, w8
+; CHECK-NEXT:    mov z2.s, w8
+; CHECK-NEXT:    mov z3.s, w9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <2 x i32> %op1, <2 x i32> %op2
   ret <2 x i32> %sel
 }
 
 define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI9_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI9_0]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    stp w8, w8, [sp]
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm w8, ne
+; CHECK-NEXT:    mvn w9, w8
+; CHECK-NEXT:    mov z2.s, w8
+; CHECK-NEXT:    mov z3.s, w9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <4 x i32> %op1, <4 x i32> %op2
   ret <4 x i32> %sel
 }
 
 define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    tst w2, #0x1
-; CHECK-NEXT:    adrp x9, .LCPI10_0
-; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    csetm w8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
+; CHECK-NEXT:    mvn w9, w8
 ; CHECK-NEXT:    ldr q2, [x1]
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    stp w8, w8, [sp, #8]
-; CHECK-NEXT:    stp w8, w8, [sp]
-; CHECK-NEXT:    ldr q5, [x9, :lo12:.LCPI10_0]
-; CHECK-NEXT:    ldr q4, [sp]
-; CHECK-NEXT:    eor z5.d, z4.d, z5.d
+; CHECK-NEXT:    mov z4.s, w8
+; CHECK-NEXT:    mov z5.s, w9
 ; CHECK-NEXT:    and z1.d, z1.d, z4.d
 ; CHECK-NEXT:    and z0.d, z0.d, z4.d
 ; CHECK-NEXT:    and z2.d, z2.d, z5.d
 ; CHECK-NEXT:    and z3.d, z3.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <8 x i32>, ptr %a
   %op2 = load volatile <8 x i32>, ptr %b
   %sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2
   store <8 x i32> %sel, ptr %a
   ret void
 }
 
 define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov x9, #-1
-; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    fmov d3, x9
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm x8, ne
+; CHECK-NEXT:    mvn x9, x8
+; CHECK-NEXT:    mov z2.d, x8
+; CHECK-NEXT:    mov z3.d, x9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2
   ret <1 x i64> %sel
 }
 
 define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 {
 ; CHECK-LABEL: select_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    adrp x9, .LCPI12_0
 ; CHECK-NEXT:    csetm x8, ne
-; CHECK-NEXT:    stp x8, x8, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q2, [sp]
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI12_0]
+; CHECK-NEXT:    mvn x9, x8
+; CHECK-NEXT:    mov z2.d, x8
+; CHECK-NEXT:    mov z3.d, x9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %sel = select i1 %mask, <2 x i64> %op1, <2 x i64> %op2
   ret <2 x i64> %sel
 }
 
 define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 {
 ; CHECK-LABEL: select_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w2, #0x1
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    ldr q1, [x0, #16]
+; CHECK-NEXT:    mvn x9, x8
 ; CHECK-NEXT:    ldr q2, [x1]
-; CHECK-NEXT:    adrp x9, .LCPI13_0
 ; CHECK-NEXT:    ldr q3, [x1, #16]
-; CHECK-NEXT:    stp x8, x8, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI13_0]
-; CHECK-NEXT:    ldr q5, [sp]
-; CHECK-NEXT:    eor z4.d, z5.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    and z0.d, z0.d, z5.d
-; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z4.d
+; CHECK-NEXT:    mov z4.d, x8
+; CHECK-NEXT:    mov z5.d, x9
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    and z2.d, z2.d, z5.d
+; CHECK-NEXT:    and z3.d, z3.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z1.d, z1.d, z3.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %op1 = load volatile <4 x i64>, ptr %a
   %op2 = load volatile <4 x i64>, ptr %b
   %sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2
   store <4 x i64> %sel, ptr %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; ASHR
 ;
 
 define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: ashr_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    adrp x9, .LCPI0_1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI0_1]
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    and z1.h, z1.h, #0xff
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = ashr <4 x i8> %op1, %op2
   ret <4 x i8> %res
 }
 
 define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; CHECK-NEXT:    ret
   %res = ashr <32 x i8> %op1, %op2
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
 ; CHECK-LABEL: ashr_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
-; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr d3, [x9, :lo12:.LCPI4_1]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    and z1.s, z1.s, #0xffff
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = ashr <2 x i16> %op1, %op2
   ret <2 x i16> %res
 }
 
 define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {

 
 ;
 ; LSHR
 ;
 
 define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: lshr_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI14_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
+; CHECK-NEXT:    and z1.h, z1.h, #0xff
+; CHECK-NEXT:    and z0.h, z0.h, #0xff
 ; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = lshr <4 x i8> %op1, %op2
   ret <4 x i8> %res
 }
 
 define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; CHECK-NEXT:    ret
   %res = lshr <32 x i8> %op1, %op2
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
 ; CHECK-LABEL: lshr_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI18_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI18_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
+; CHECK-NEXT:    and z1.s, z1.s, #0xffff
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
 ; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = lshr <2 x i16> %op1, %op2
   ret <2 x i16> %res
 }
 
 define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {

 
 ;
 ; SHL
 ;
 
 define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) #0 {
 ; CHECK-LABEL: shl_v2i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI28_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI28_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
+; CHECK-NEXT:    and z1.s, z1.s, #0xff
 ; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = shl <2 x i8> %op1, %op2
   ret <2 x i8> %res
 }
 
 define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
 ; CHECK-LABEL: shl_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI29_0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI29_0]
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
+; CHECK-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = shl <4 x i8> %op1, %op2
   ret <4 x i8> %res
 }
 
 define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll

 
 ;
 ; UCVTF H -> S
 ;
 
 define <2 x float> @ucvtf_v2i16_v2f32(<2 x i16> %op1) #0 {
 ; CHECK-LABEL: ucvtf_v2i16_v2f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI3_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
 ; CHECK-NEXT:    ucvtf z0.s, p0/m, z0.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = uitofp <2 x i16> %op1 to <2 x float>
   ret <2 x float> %res
 }
 
 define <4 x float> @ucvtf_v4i16_v4f32(<4 x i16> %op1) #0 {

 ; CHECK-NEXT:    ret
   %res = uitofp <1 x i16> %op1 to <1 x double>
   ret <1 x double> %res
 }
 
 define <2 x double> @ucvtf_v2i16_v2f64(<2 x i16> %op1) #0 {
 ; CHECK-LABEL: ucvtf_v2i16_v2f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI8_0]
-; CHECK-NEXT:    and z0.d, z0.d, z1.d
+; CHECK-NEXT:    and z0.s, z0.s, #0xffff
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
 ; CHECK-NEXT:    ucvtf z0.d, p0/m, z0.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %res = uitofp <2 x i16> %op1 to <2 x double>
   ret <2 x double> %res
 }
 

 }
 
 ; SCVTF H -> S
 ;
 
 define <2 x float> @scvtf_v2i16_v2f32(<2 x i16> %op1) #0 {
 ; CHECK-LABEL: scvtf_v2i16_v2f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI33_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI33_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = sitofp <2 x i16> %op1 to <2 x float>
   ret <2 x float> %res
 }
 
 define <4 x float> @scvtf_v4i16_v4f32(<4 x i16> %op1) #0 {

 
 ;
 ; SCVTF H -> D
 ;
 
 define <2 x double> @scvtf_v2i16_v2f64(<2 x i16> %op1) #0 {
 ; CHECK-LABEL: scvtf_v2i16_v2f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI37_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI37_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    sunpklo z0.d, z0.s
 ; CHECK-NEXT:    scvtf z0.d, p0/m, z0.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %res = sitofp <2 x i16> %op1 to <2 x double>
   ret <2 x double> %res
 }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    adrp x9, .LCPI0_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI0_1]
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    asr z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    asr z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <4 x i1> %mask, <4 x i8> %op1, <4 x i8> %op2
   ret <4 x i8> %sel
 }
 
 define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v8i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
-; CHECK-NEXT:    adrp x9, .LCPI1_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.b, vl8
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI1_1]
-; CHECK-NEXT:    lsl z2.b, p0/m, z2.b, z3.b
-; CHECK-NEXT:    asr z2.b, p0/m, z2.b, z3.b
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.b, p0/m, z2.b, #7
+; CHECK-NEXT:    asr z2.b, p0/m, z2.b, #7
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op2
   ret <8 x i8> %sel
 }
 
 define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
-; CHECK-NEXT:    adrp x9, .LCPI2_1
 ; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
 ; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI2_1]
-; CHECK-NEXT:    lsl z2.b, p0/m, z2.b, z3.b
-; CHECK-NEXT:    asr z2.b, p0/m, z2.b, z3.b
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.b, p0/m, z2.b, #7
+; CHECK-NEXT:    asr z2.b, p0/m, z2.b, #7
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2
   ret <16 x i8> %sel
 }
 
 define void @select_v32i8(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI3_0
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    cmpeq p1.b, p0/z, z2.b, z0.b
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z3.b, z1.b
-; CHECK-NEXT:    mov z5.b, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.b, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z5.d
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    cmpeq p1.b, p0/z, z0.b, z2.b
+; CHECK-NEXT:    cmpeq p0.b, p0/z, z1.b, z3.b
+; CHECK-NEXT:    mov z4.b, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.b, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    orr z1.d, z1.d, z3.d
+; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %op2 = load <32 x i8>, ptr %b
   %mask = icmp eq <32 x i8> %op1, %op2
   %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2
   store <32 x i8> %sel, ptr %a
   ret void
 }
 
 define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
-; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI4_1]
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    asr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    asr z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x i16> %op1, <2 x i16> %op2
   ret <2 x i16> %sel
 }
 
 define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI5_0
-; CHECK-NEXT:    adrp x9, .LCPI5_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI5_1]
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    asr z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    asr z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2
   ret <4 x i16> %sel
 }
 
 define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI6_0
-; CHECK-NEXT:    adrp x9, .LCPI6_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    uunpklo z2.h, z2.b
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI6_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI6_1]
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    asr z2.h, p0/m, z2.h, z3.h
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    asr z2.h, p0/m, z2.h, #15
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2
   ret <8 x i16> %sel
 }
 
 define void @select_v16i16(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI7_0
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI7_0]
-; CHECK-NEXT:    cmpeq p1.h, p0/z, z2.h, z0.h
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z3.h, z1.h
-; CHECK-NEXT:    mov z5.h, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.h, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z5.d
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    cmpeq p1.h, p0/z, z0.h, z2.h
+; CHECK-NEXT:    cmpeq p0.h, p0/z, z1.h, z3.h
+; CHECK-NEXT:    mov z4.h, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    orr z1.d, z1.d, z3.d
+; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %op2 = load <16 x i16>, ptr %b
   %mask = icmp eq <16 x i16> %op1, %op2
   %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2
   store <16 x i16> %sel, ptr %a
   ret void
 }
 
 define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
-; CHECK-NEXT:    adrp x9, .LCPI8_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    ldr d3, [x8, :lo12:.LCPI8_0]
-; CHECK-NEXT:    ldr d4, [x9, :lo12:.LCPI8_1]
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    asr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    asr z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2
   ret <2 x i32> %sel
 }
 
 define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI9_0
-; CHECK-NEXT:    adrp x9, .LCPI9_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    uunpklo z2.s, z2.h
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI9_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI9_1]
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    asr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    asr z2.s, p0/m, z2.s, #31
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2
   ret <4 x i32> %sel
 }
 
 define void @select_v8i32(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI10_0
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI10_0]
-; CHECK-NEXT:    cmpeq p1.s, p0/z, z2.s, z0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z3.s, z1.s
-; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z5.d
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    cmpeq p1.s, p0/z, z0.s, z2.s
+; CHECK-NEXT:    cmpeq p0.s, p0/z, z1.s, z3.s
+; CHECK-NEXT:    mov z4.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    orr z1.d, z1.d, z3.d
+; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %op2 = load <8 x i32>, ptr %b
   %mask = icmp eq <8 x i32> %op1, %op2
   %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2
   store <8 x i32> %sel, ptr %a
   ret void
 }
 
 define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov x9, #-1
-; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    fmov d3, x9
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    eor z3.d, z2.d, z3.d
+; CHECK-NEXT:    csetm x8, ne
+; CHECK-NEXT:    mvn x9, x8
+; CHECK-NEXT:    mov z2.d, x8
+; CHECK-NEXT:    mov z3.d, x9
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
 ; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2
   ret <1 x i64> %sel
 }
 
 define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI12_0
-; CHECK-NEXT:    adrp x9, .LCPI12_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    uunpklo z2.d, z2.s
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI12_0]
-; CHECK-NEXT:    ldr q4, [x9, :lo12:.LCPI12_1]
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z3.d
-; CHECK-NEXT:    asr z2.d, p0/m, z2.d, z3.d
-; CHECK-NEXT:    eor z3.d, z2.d, z4.d
+; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, #63
+; CHECK-NEXT:    asr z2.d, p0/m, z2.d, #63
+; CHECK-NEXT:    bic z1.d, z1.d, z2.d
 ; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2
   ret <2 x i64> %sel
 }
 
 define void @select_v4i64(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q1, q0, [x1]
-; CHECK-NEXT:    adrp x8, .LCPI13_0
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI13_0]
-; CHECK-NEXT:    cmpeq p1.d, p0/z, z2.d, z0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z3.d, z1.d
-; CHECK-NEXT:    mov z5.d, p1/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z6.d, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z2.d, z2.d, z5.d
-; CHECK-NEXT:    eor z5.d, z5.d, z4.d
-; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z5.d
-; CHECK-NEXT:    orr z1.d, z3.d, z1.d
-; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    ldp q3, q2, [x1]
+; CHECK-NEXT:    cmpeq p1.d, p0/z, z0.d, z2.d
+; CHECK-NEXT:    cmpeq p0.d, p0/z, z1.d, z3.d
+; CHECK-NEXT:    mov z4.d, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z5.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    bic z2.d, z2.d, z4.d
+; CHECK-NEXT:    bic z3.d, z3.d, z5.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    orr z1.d, z1.d, z3.d
+; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %op2 = load <4 x i64>, ptr %b
   %mask = icmp eq <4 x i64> %op1, %op2
   %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2
   store <4 x i64> %sel, ptr %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" uwtable }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; Masked Load
 ;
 
 define <4 x i8> @masked_load_v4i8(<4 x i8>* %src, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT:    ld1b { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <4 x i8> @llvm.masked.load.v4i8(<4 x i8>* %src, i32 8, <4 x i1> %mask, <4 x i8> zeroinitializer)
   ret <4 x i8> %load
 }
 
 define <8 x i8> @masked_load_v8i8(<8 x i8>* %src, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v8i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.b, vl8
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <8 x i8> @llvm.masked.load.v8i8(<8 x i8>* %src, i32 8, <8 x i1> %mask, <8 x i8> zeroinitializer)
   ret <8 x i8> %load
 }
 
 define <16 x i8> @masked_load_v16i8(<16 x i8>* %src, <16 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %src, i32 8, <16 x i1> %mask, <16 x i8> zeroinitializer)
   ret <16 x i8> %load
 }
 

 ; CHECK-NEXT:    strb w10, [sp, #11]
 ; CHECK-NEXT:    ldr w10, [sp, #40]
 ; CHECK-NEXT:    strb w8, [sp, #10]
 ; CHECK-NEXT:    ldr w8, [sp, #32]
 ; CHECK-NEXT:    strb w9, [sp, #9]
 ; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    strb w10, [sp, #8]
 ; CHECK-NEXT:    strb w8, [sp, #7]
-; CHECK-NEXT:    adrp x8, .LCPI3_0
+; CHECK-NEXT:    mov w8, #16
 ; CHECK-NEXT:    strb w4, [sp, #3]
 ; CHECK-NEXT:    strb w3, [sp, #2]
 ; CHECK-NEXT:    strb w2, [sp, #1]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI3_0]
 ; CHECK-NEXT:    strb w1, [sp]
-; CHECK-NEXT:    mov w8, #16
-; CHECK-NEXT:    ldp q2, q1, [sp]
-; CHECK-NEXT:    lsl z2.b, p0/m, z2.b, z0.b
-; CHECK-NEXT:    lsl z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    asr z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    asrr z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    cmpne p1.b, p0/z, z1.b, #0
-; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
+; CHECK-NEXT:    ldp q1, q0, [sp]
+; CHECK-NEXT:    lsl z1.b, p0/m, z1.b, #7
+; CHECK-NEXT:    asr z1.b, p0/m, z1.b, #7
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
+; CHECK-NEXT:    cmpne p0.b, p0/z, z1.b, #0
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0]
 ; CHECK-NEXT:    ld1b { z1.b }, p1/z, [x0, x8]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
 ; CHECK-NEXT:    add sp, sp, #32
 ; CHECK-NEXT:    ret
   %load = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %src, i32 8, <32 x i1> %mask, <32 x i8> zeroinitializer)
   ret <32 x i8> %load
 }
 
 define <2 x half> @masked_load_v2f16(<2 x half>* %src, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    mov z1.s, z0.s[1]
-; CHECK-NEXT:    fmov w9, s0
-; CHECK-NEXT:    fmov w10, s1
-; CHECK-NEXT:    adrp x8, .LCPI4_0
+; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    str wzr, [sp, #12]
+; CHECK-NEXT:    mov z0.s, z0.s[1]
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    strh w9, [sp, #8]
-; CHECK-NEXT:    strh w10, [sp, #10]
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr d1, [sp, #8]
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z0.h
-; CHECK-NEXT:    asrr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    strh w8, [sp, #8]
+; CHECK-NEXT:    strh w9, [sp, #10]
+; CHECK-NEXT:    ldr d0, [sp, #8]
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %load = call <2 x half> @llvm.masked.load.v2f16(<2 x half>* %src, i32 8, <2 x i1> %mask, <2 x half> zeroinitializer)
   ret <2 x half> %load
 }
 
 define <4 x half> @masked_load_v4f16(<4 x half>* %src, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v4f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI5_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <4 x half> @llvm.masked.load.v4f16(<4 x half>* %src, i32 8, <4 x i1> %mask, <4 x half> zeroinitializer)
   ret <4 x half> %load
 }
 
 define <8 x half> @masked_load_v8f16(<8 x half>* %src, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v8f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI6_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    uunpklo z0.h, z0.b
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <8 x half> @llvm.masked.load.v8f16(<8 x half>* %src, i32 8, <8 x i1> %mask, <8 x half> zeroinitializer)
   ret <8 x half> %load
 }
 
 define <16 x half> @masked_load_v16f16(<16 x half>* %src, <16 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI7_0
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT:    uunpklo z2.h, z0.b
-; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
+; CHECK-NEXT:    uunpklo z1.h, z0.b
 ; CHECK-NEXT:    ptrue p0.h, vl8
+; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #15
 ; CHECK-NEXT:    uunpklo z0.h, z0.b
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
 ; CHECK-NEXT:    mov x8, #8
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z1.h
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    asr z2.h, p0/m, z2.h, z1.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    cmpne p1.h, p0/z, z2.h, #0
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    cmpne p1.h, p0/z, z1.h, #0
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT:    ld1h { z0.h }, p1/z, [x0]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
 ; CHECK-NEXT:    ret
   %load = call <16 x half> @llvm.masked.load.v16f16(<16 x half>* %src, i32 8, <16 x i1> %mask, <16 x half> zeroinitializer)
   ret <16 x half> %load
 }
 
 define <2 x float> @masked_load_v2f32(<2 x float>* %src, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v2f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI8_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
 ; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, #0
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <2 x float> @llvm.masked.load.v2f32(<2 x float>* %src, i32 8, <2 x i1> %mask, <2 x float> zeroinitializer)
   ret <2 x float> %load
 }
 
 define <4 x float> @masked_load_v4f32(<4 x float>* %src, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v4f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI9_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
 ; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, #0
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %src, i32 8, <4 x i1> %mask, <4 x float> zeroinitializer)
   ret <4 x float> %load
 }
 
 define <8 x float> @masked_load_v8f32(<8 x float>* %src, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    mov z1.b, z0.b[3]
 ; CHECK-NEXT:    mov z2.b, z0.b[2]
-; CHECK-NEXT:    adrp x8, .LCPI10_0
+; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    mov z3.b, z0.b[1]
 ; CHECK-NEXT:    mov z4.b, z0.b[7]
 ; CHECK-NEXT:    mov z5.b, z0.b[6]
 ; CHECK-NEXT:    mov z6.b, z0.b[5]
-; CHECK-NEXT:    fmov w10, s1
+; CHECK-NEXT:    fmov w9, s1
 ; CHECK-NEXT:    mov z0.b, z0.b[4]
-; CHECK-NEXT:    fmov w11, s2
-; CHECK-NEXT:    strh w9, [sp, #-16]!
+; CHECK-NEXT:    fmov w10, s2
+; CHECK-NEXT:    strh w8, [sp, #-16]!
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    fmov w9, s3
-; CHECK-NEXT:    strh w10, [sp, #6]
-; CHECK-NEXT:    fmov w10, s4
-; CHECK-NEXT:    strh w11, [sp, #4]
-; CHECK-NEXT:    fmov w11, s5
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI10_0]
-; CHECK-NEXT:    strh w9, [sp, #2]
-; CHECK-NEXT:    fmov w9, s6
-; CHECK-NEXT:    strh w10, [sp, #14]
-; CHECK-NEXT:    fmov w10, s0
-; CHECK-NEXT:    strh w11, [sp, #12]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    strh w9, [sp, #10]
+; CHECK-NEXT:    fmov w8, s3
+; CHECK-NEXT:    strh w9, [sp, #6]
+; CHECK-NEXT:    fmov w9, s4
+; CHECK-NEXT:    strh w10, [sp, #4]
+; CHECK-NEXT:    fmov w10, s5
+; CHECK-NEXT:    strh w8, [sp, #2]
+; CHECK-NEXT:    fmov w8, s6
+; CHECK-NEXT:    strh w9, [sp, #14]
+; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    strh w10, [sp, #12]
+; CHECK-NEXT:    strh w8, [sp, #10]
 ; CHECK-NEXT:    mov x8, #4
-; CHECK-NEXT:    strh w10, [sp, #8]
-; CHECK-NEXT:    ldp d0, d2, [sp]
+; CHECK-NEXT:    strh w9, [sp, #8]
+; CHECK-NEXT:    ldp d0, d1, [sp]
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    uunpklo z2.s, z2.h
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    lsl z2.s, p0/m, z2.s, z1.s
+; CHECK-NEXT:    uunpklo z1.s, z1.h
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z1.s, p0/m, z1.s, #31
 ; CHECK-NEXT:    cmpne p1.s, p0/z, z0.s, #0
-; CHECK-NEXT:    ld1w { z0.s }, p1/z, [x0]
-; CHECK-NEXT:    asrr z1.s, p0/m, z1.s, z2.s
 ; CHECK-NEXT:    cmpne p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT:    ld1w { z0.s }, p1/z, [x0]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
 ; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %load = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %src, i32 8, <8 x i1> %mask, <8 x float> zeroinitializer)
   ret <8 x float> %load
 }
 
 define <2 x double> @masked_load_v2f64(<2 x double>* %src, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v2f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI11_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #63
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %load = call <2 x double> @llvm.masked.load.v2f64(<2 x double>* %src, i32 8, <2 x i1> %mask, <2 x double> zeroinitializer)
   ret <2 x double> %load
 }
 
 define <4 x double> @masked_load_v4f64(<4 x double>* %src, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_load_v4f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI12_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
+; CHECK-NEXT:    mov x8, #2
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    uunpklo z2.d, z0.s
+; CHECK-NEXT:    uunpklo z1.d, z0.s
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_0]
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    mov x8, #2
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    asr z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    cmpne p1.d, p0/z, z2.d, #0
+; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    asr z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    cmpne p1.d, p0/z, z1.d, #0
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
 ; CHECK-NEXT:    ld1d { z0.d }, p1/z, [x0]
 ; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0, x8, lsl #3]
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
 ; CHECK-NEXT:    ret
   %load = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %src, i32 8, <4 x i1> %mask, <4 x double> zeroinitializer)
   ret <4 x double> %load

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; Masked Store
 ;
 
 define void @masked_store_v4i8(<4 x i8>* %dst, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    adrp x8, .LCPI0_1
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_1]
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
-; CHECK-NEXT:    st1b { z2.h }, p0, [x0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
+; CHECK-NEXT:    st1b { z0.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v4i8(<4 x i8> zeroinitializer, <4 x i8>* %dst, i32 8, <4 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v8i8(<8 x i8>* %dst, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v8i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.b, vl8
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    adrp x8, .LCPI1_1
-; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI1_1]
-; CHECK-NEXT:    asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
-; CHECK-NEXT:    st1b { z2.b }, p0, [x0]
+; CHECK-NEXT:    mov z0.b, #0 // =0x0
+; CHECK-NEXT:    st1b { z0.b }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v8i8(<8 x i8> zeroinitializer, <8 x i8>* %dst, i32 8, <8 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v16i8(<16 x i8>* %dst, <16 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    adrp x8, .LCPI2_1
-; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, z1.b
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI2_1]
-; CHECK-NEXT:    asr z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
-; CHECK-NEXT:    st1b { z2.b }, p0, [x0]
+; CHECK-NEXT:    mov z0.b, #0 // =0x0
+; CHECK-NEXT:    st1b { z0.b }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v16i8(<16 x i8> zeroinitializer, <16 x i8>* %dst, i32 8, <16 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v32i8(<32 x i8>* %dst, <32 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v32i8:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ldr w9, [sp, #144]
 ; CHECK-NEXT:    strb w10, [sp, #23]
 ; CHECK-NEXT:    ldr w10, [sp, #136]
 ; CHECK-NEXT:    strb w8, [sp, #22]
 ; CHECK-NEXT:    ldr w8, [sp, #128]
 ; CHECK-NEXT:    strb w9, [sp, #21]
 ; CHECK-NEXT:    ldr w9, [sp, #120]
 ; CHECK-NEXT:    strb w10, [sp, #20]
-; CHECK-NEXT:    ldr w10, [sp, #104]
+; CHECK-NEXT:    ldr w10, [sp, #112]
 ; CHECK-NEXT:    strb w8, [sp, #19]
-; CHECK-NEXT:    ldr w8, [sp, #112]
+; CHECK-NEXT:    ldr w8, [sp, #104]
 ; CHECK-NEXT:    strb w4, [sp, #3]
-; CHECK-NEXT:    adrp x11, .LCPI3_0
-; CHECK-NEXT:    strb w3, [sp, #2]
 ; CHECK-NEXT:    ptrue p0.b, vl16
+; CHECK-NEXT:    strb w3, [sp, #2]
 ; CHECK-NEXT:    strb w2, [sp, #1]
 ; CHECK-NEXT:    strb w1, [sp]
-; CHECK-NEXT:    ldr q0, [x11, :lo12:.LCPI3_0]
 ; CHECK-NEXT:    strb w9, [sp, #18]
-; CHECK-NEXT:    strb w8, [sp, #17]
-; CHECK-NEXT:    adrp x8, .LCPI3_1
-; CHECK-NEXT:    strb w10, [sp, #16]
-; CHECK-NEXT:    ldp q1, q2, [sp]
-; CHECK-NEXT:    lsl z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    asr z1.b, p0/m, z1.b, z0.b
-; CHECK-NEXT:    lsl z2.b, p0/m, z2.b, z0.b
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI3_1]
+; CHECK-NEXT:    strb w10, [sp, #17]
+; CHECK-NEXT:    strb w8, [sp, #16]
 ; CHECK-NEXT:    mov w8, #16
-; CHECK-NEXT:    asrr z0.b, p0/m, z0.b, z2.b
-; CHECK-NEXT:    cmpne p1.b, p0/z, z1.b, #0
+; CHECK-NEXT:    ldp q0, q1, [sp]
+; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
+; CHECK-NEXT:    lsl z1.b, p0/m, z1.b, #7
+; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
+; CHECK-NEXT:    movprfx z0, z1
+; CHECK-NEXT:    asr z0.b, p0/m, z0.b, #7
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
-; CHECK-NEXT:    st1b { z3.b }, p0, [x0, x8]
-; CHECK-NEXT:    st1b { z3.b }, p1, [x0]
+; CHECK-NEXT:    mov z0.b, #0 // =0x0
+; CHECK-NEXT:    st1b { z0.b }, p0, [x0, x8]
+; CHECK-NEXT:    st1b { z0.b }, p1, [x0]
 ; CHECK-NEXT:    add sp, sp, #32
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v32i8(<32 x i8> zeroinitializer, <32 x i8>* %dst, i32 8, <32 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v2f16(<2 x half>* %dst, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT:    mov z1.s, z0.s[1]
-; CHECK-NEXT:    fmov w9, s0
-; CHECK-NEXT:    fmov w10, s1
-; CHECK-NEXT:    adrp x8, .LCPI4_0
+; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    str wzr, [sp, #12]
+; CHECK-NEXT:    mov z0.s, z0.s[1]
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    strh w9, [sp, #8]
-; CHECK-NEXT:    strh w10, [sp, #10]
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr d1, [sp, #8]
-; CHECK-NEXT:    adrp x8, .LCPI4_1
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z0.h
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI4_1]
-; CHECK-NEXT:    asrr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    strh w8, [sp, #8]
+; CHECK-NEXT:    strh w9, [sp, #10]
+; CHECK-NEXT:    ldr d0, [sp, #8]
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
-; CHECK-NEXT:    st1h { z2.h }, p0, [x0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
 ; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v2f16(<2 x half> zeroinitializer, <2 x half>* %dst, i32 8, <2 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v4f16(<4 x half>* %dst, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v4f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI5_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    adrp x8, .LCPI5_1
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI5_1]
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
-; CHECK-NEXT:    st1h { z2.h }, p0, [x0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v4f16(<4 x half> zeroinitializer, <4 x half>* %dst, i32 8, <4 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v8f16(<8 x half>* %dst, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v8f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI6_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    uunpklo z0.h, z0.b
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
-; CHECK-NEXT:    adrp x8, .LCPI6_1
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI6_1]
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
-; CHECK-NEXT:    st1h { z2.h }, p0, [x0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v8f16(<8 x half> zeroinitializer, <8 x half>* %dst, i32 8, <8 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v16f16(<16 x half>* %dst, <16 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI7_0
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    mov z1.d, z0.d
-; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
-; CHECK-NEXT:    uunpklo z0.h, z0.b
 ; CHECK-NEXT:    ptrue p0.h, vl8
+; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #8
+; CHECK-NEXT:    uunpklo z0.h, z0.b
 ; CHECK-NEXT:    uunpklo z1.h, z1.b
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI7_0]
-; CHECK-NEXT:    adrp x8, .LCPI7_1
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI7_1]
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, z2.h
 ; CHECK-NEXT:    mov x8, #8
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z2.h
-; CHECK-NEXT:    asr z1.h, p0/m, z1.h, z2.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z2.h
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #15
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #15
+; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #15
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #15
 ; CHECK-NEXT:    cmpne p1.h, p0/z, z1.h, #0
+; CHECK-NEXT:    mov z1.h, #0 // =0x0
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
-; CHECK-NEXT:    st1h { z3.h }, p1, [x0, x8, lsl #1]
-; CHECK-NEXT:    st1h { z3.h }, p0, [x0]
+; CHECK-NEXT:    st1h { z1.h }, p1, [x0, x8, lsl #1]
+; CHECK-NEXT:    st1h { z1.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v16f16(<16 x half> zeroinitializer, <16 x half>* %dst, i32 8, <16 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v4f32(<4 x float>* %dst, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v4f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
-; CHECK-NEXT:    adrp x8, .LCPI8_1
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI8_1]
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
 ; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, #0
-; CHECK-NEXT:    st1w { z2.s }, p0, [x0]
+; CHECK-NEXT:    mov z0.s, #0 // =0x0
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v4f32(<4 x float> zeroinitializer, <4 x float>* %dst, i32 8, <4 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v8f32(<8 x float>* %dst, <8 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub sp, sp, #16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    mov z1.b, z0.b[7]
 ; CHECK-NEXT:    mov z2.b, z0.b[6]
-; CHECK-NEXT:    fmov w9, s1
+; CHECK-NEXT:    fmov w8, s1
 ; CHECK-NEXT:    mov z1.b, z0.b[5]
-; CHECK-NEXT:    fmov w10, s2
-; CHECK-NEXT:    mov z2.b, z0.b[4]
-; CHECK-NEXT:    fmov w11, s1
-; CHECK-NEXT:    adrp x8, .LCPI9_0
-; CHECK-NEXT:    strh w9, [sp, #14]
 ; CHECK-NEXT:    fmov w9, s2
-; CHECK-NEXT:    strh w10, [sp, #12]
-; CHECK-NEXT:    adrp x10, .LCPI9_1
-; CHECK-NEXT:    strh w11, [sp, #10]
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI9_0]
-; CHECK-NEXT:    strh w9, [sp, #8]
-; CHECK-NEXT:    mov x9, #4
+; CHECK-NEXT:    mov z2.b, z0.b[4]
+; CHECK-NEXT:    fmov w10, s1
+; CHECK-NEXT:    ptrue p0.s, vl4
+; CHECK-NEXT:    strh w8, [sp, #14]
+; CHECK-NEXT:    fmov w8, s2
+; CHECK-NEXT:    strh w9, [sp, #12]
+; CHECK-NEXT:    mov z2.b, z0.b[3]
+; CHECK-NEXT:    strh w10, [sp, #10]
+; CHECK-NEXT:    mov z3.b, z0.b[2]
+; CHECK-NEXT:    strh w8, [sp, #8]
+; CHECK-NEXT:    mov z4.b, z0.b[1]
 ; CHECK-NEXT:    ldr d1, [sp, #8]
 ; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    ldr q3, [x10, :lo12:.LCPI9_1]
-; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    mov z4.b, z0.b[3]
-; CHECK-NEXT:    mov z5.b, z0.b[2]
-; CHECK-NEXT:    uunpklo z1.s, z1.h
-; CHECK-NEXT:    mov z6.b, z0.b[1]
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    movprfx z0, z1
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT:    mov x9, #4
+; CHECK-NEXT:    fmov w10, s2
+; CHECK-NEXT:    uunpklo z0.s, z1.h
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #31
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #31
 ; CHECK-NEXT:    cmpne p1.s, p0/z, z0.s, #0
-; CHECK-NEXT:    fmov w10, s4
-; CHECK-NEXT:    st1w { z3.s }, p1, [x0, x9, lsl #2]
-; CHECK-NEXT:    fmov w9, s5
+; CHECK-NEXT:    mov z0.s, #0 // =0x0
+; CHECK-NEXT:    st1w { z0.s }, p1, [x0, x9, lsl #2]
+; CHECK-NEXT:    fmov w9, s3
 ; CHECK-NEXT:    strh w8, [sp]
-; CHECK-NEXT:    fmov w8, s6
+; CHECK-NEXT:    fmov w8, s4
 ; CHECK-NEXT:    strh w10, [sp, #6]
 ; CHECK-NEXT:    strh w9, [sp, #4]
 ; CHECK-NEXT:    strh w8, [sp, #2]
-; CHECK-NEXT:    ldr d0, [sp]
-; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, #0
-; CHECK-NEXT:    st1w { z3.s }, p0, [x0]
+; CHECK-NEXT:    ldr d1, [sp]
+; CHECK-NEXT:    uunpklo z1.s, z1.h
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    asr z1.s, p0/m, z1.s, #31
+; CHECK-NEXT:    cmpne p0.s, p0/z, z1.s, #0
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
 ; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v8f32(<8 x float> zeroinitializer, <8 x float>* %dst, i32 8, <8 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v2f64(<2 x double>* %dst, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v2f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI10_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI10_0]
-; CHECK-NEXT:    adrp x8, .LCPI10_1
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI10_1]
-; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #63
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
-; CHECK-NEXT:    st1d { z2.d }, p0, [x0]
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v2f64(<2 x double> zeroinitializer, <2 x double>* %dst, i32 8, <2 x i1> %mask)
   ret void
 }
 
 define void @masked_store_v4f64(<4 x double>* %dst, <4 x i1> %mask) #0 {
 ; CHECK-LABEL: masked_store_v4f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI11_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
+; CHECK-NEXT:    mov x8, #2
 ; CHECK-NEXT:    uunpklo z0.s, z0.h
-; CHECK-NEXT:    uunpklo z2.d, z0.s
+; CHECK-NEXT:    uunpklo z1.d, z0.s
 ; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
-; CHECK-NEXT:    adrp x8, .LCPI11_1
 ; CHECK-NEXT:    uunpklo z0.d, z0.s
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI11_1]
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    mov x8, #2
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z1.d
-; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    asrr z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #63
+; CHECK-NEXT:    asr z1.d, p0/m, z1.d, #63
+; CHECK-NEXT:    asr z0.d, p0/m, z0.d, #63
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z0.d, #0
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z1.d, #0
-; CHECK-NEXT:    st1d { z3.d }, p1, [x0, x8, lsl #3]
-; CHECK-NEXT:    st1d { z3.d }, p0, [x0]
+; CHECK-NEXT:    st1d { z0.d }, p1, [x0, x8, lsl #3]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.store.v4f64(<4 x double> zeroinitializer, <4 x double>* %dst, i32 8, <4 x i1> %mask)
   ret void
 }
 
 declare void @llvm.masked.store.v4i8(<4 x i8>, <4 x i8>*, i32, <4 x i1>)
 declare void @llvm.masked.store.v8i8(<8 x i8>, <8 x i8>*, i32, <8 x i1>)
 declare void @llvm.masked.store.v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>)

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define i1 @ptest_v16i1(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: ptest_v16i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
+; CHECK-NEXT:    ldp q0, q1, [x0, #32]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q1, q2, [x0, #32]
 ; CHECK-NEXT:    ptrue p1.h, vl4
-; CHECK-NEXT:    ldp q3, q4, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    fcmne p2.s, p0/z, z2.s, z0.s
-; CHECK-NEXT:    mov z2.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    fcmne p2.s, p0/z, z1.s, z0.s
+; CHECK-NEXT:    ldp q2, q3, [x0]
+; CHECK-NEXT:    fcmne p2.s, p0/z, z1.s, #0.0
 ; CHECK-NEXT:    mov z1.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    fcmne p2.s, p0/z, z4.s, z0.s
-; CHECK-NEXT:    fcmne p0.s, p0/z, z3.s, z0.s
+; CHECK-NEXT:    fcmne p2.s, p0/z, z0.s, #0.0
 ; CHECK-NEXT:    mov z0.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
 ; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
-; CHECK-NEXT:    mov z3.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    splice z1.h, p1, z1.h, z2.h
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    uzp1 z2.h, z3.h, z3.h
-; CHECK-NEXT:    splice z2.h, p1, z2.h, z0.h
-; CHECK-NEXT:    uzp1 z1.b, z1.b, z1.b
-; CHECK-NEXT:    uzp1 z0.b, z2.b, z2.b
+; CHECK-NEXT:    splice z0.h, p1, z0.h, z1.h
+; CHECK-NEXT:    fcmne p2.s, p0/z, z3.s, #0.0
+; CHECK-NEXT:    fcmne p0.s, p0/z, z2.s, #0.0
+; CHECK-NEXT:    mov z2.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z3.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
+; CHECK-NEXT:    uzp1 z3.h, z3.h, z3.h
+; CHECK-NEXT:    splice z3.h, p1, z3.h, z2.h
+; CHECK-NEXT:    uzp1 z0.b, z0.b, z0.b
+; CHECK-NEXT:    uzp1 z1.b, z3.b, z3.b
 ; CHECK-NEXT:    ptrue p0.b, vl8
-; CHECK-NEXT:    splice z0.b, p0, z0.b, z1.b
+; CHECK-NEXT:    splice z1.b, p0, z1.b, z0.b
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    orv b0, p0, z0.b
+; CHECK-NEXT:    orv b0, p0, z1.b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
   %v0 = bitcast ptr %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
   ret i1 %v3
 }
 
 define i1 @ptest_or_v16i1(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: ptest_or_v16i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
+; CHECK-NEXT:    ldp q0, q1, [x0, #32]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q0, q2, [x0, #32]
 ; CHECK-NEXT:    ptrue p1.h, vl4
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
-; CHECK-NEXT:    ldp q3, q4, [x0]
-; CHECK-NEXT:    fcmne p2.s, p0/z, z2.s, z1.s
-; CHECK-NEXT:    fcmne p3.s, p0/z, z0.s, z1.s
+; CHECK-NEXT:    fcmne p3.s, p0/z, z0.s, #0.0
+; CHECK-NEXT:    ldp q2, q3, [x0]
+; CHECK-NEXT:    fcmne p2.s, p0/z, z1.s, #0.0
+; CHECK-NEXT:    mov z1.s, p3/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    mov z0.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z2.s, p3/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
-; CHECK-NEXT:    splice z2.h, p1, z2.h, z0.h
-; CHECK-NEXT:    ldp q0, q5, [x1, #32]
-; CHECK-NEXT:    fcmne p2.s, p0/z, z4.s, z1.s
-; CHECK-NEXT:    uzp1 z2.b, z2.b, z2.b
-; CHECK-NEXT:    mov z4.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    fcmne p2.s, p0/z, z3.s, z1.s
-; CHECK-NEXT:    mov z3.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    splice z1.h, p1, z1.h, z0.h
+; CHECK-NEXT:    fcmne p3.s, p0/z, z2.s, #0.0
+; CHECK-NEXT:    mov z4.s, p3/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    fcmne p2.s, p0/z, z3.s, #0.0
 ; CHECK-NEXT:    uzp1 z4.h, z4.h, z4.h
+; CHECK-NEXT:    ldp q3, q0, [x1, #32]
+; CHECK-NEXT:    mov z2.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
+; CHECK-NEXT:    splice z4.h, p1, z4.h, z2.h
+; CHECK-NEXT:    fcmne p3.s, p0/z, z3.s, #0.0
+; CHECK-NEXT:    mov z3.s, p3/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    ldp q5, q6, [x1]
+; CHECK-NEXT:    fcmne p2.s, p0/z, z0.s, #0.0
 ; CHECK-NEXT:    uzp1 z3.h, z3.h, z3.h
-; CHECK-NEXT:    fcmne p3.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    splice z3.h, p1, z3.h, z4.h
-; CHECK-NEXT:    fcmne p2.s, p0/z, z5.s, z1.s
-; CHECK-NEXT:    uzp1 z3.b, z3.b, z3.b
-; CHECK-NEXT:    ldp q4, q5, [x1]
 ; CHECK-NEXT:    mov z0.s, p2/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    fcmne p2.s, p0/z, z5.s, z1.s
-; CHECK-NEXT:    fcmne p0.s, p0/z, z4.s, z1.s
-; CHECK-NEXT:    mov z5.s, p3/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    splice z3.h, p1, z3.h, z0.h
+; CHECK-NEXT:    uzp1 z0.b, z1.b, z1.b
+; CHECK-NEXT:    uzp1 z1.b, z4.b, z4.b
+; CHECK-NEXT:    fcmne p2.s, p0/z, z6.s, #0.0
+; CHECK-NEXT:    fcmne p0.s, p0/z, z5.s, #0.0
+; CHECK-NEXT:    mov z2.s, p2/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    mov z4.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    uzp1 z5.h, z5.h, z5.h
-; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
+; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
 ; CHECK-NEXT:    uzp1 z4.h, z4.h, z4.h
-; CHECK-NEXT:    splice z5.h, p1, z5.h, z0.h
-; CHECK-NEXT:    splice z4.h, p1, z4.h, z1.h
-; CHECK-NEXT:    ptrue p3.b, vl8
-; CHECK-NEXT:    uzp1 z0.b, z5.b, z5.b
-; CHECK-NEXT:    uzp1 z1.b, z4.b, z4.b
-; CHECK-NEXT:    splice z3.b, p3, z3.b, z2.b
-; CHECK-NEXT:    splice z1.b, p3, z1.b, z0.b
+; CHECK-NEXT:    splice z4.h, p1, z4.h, z2.h
+; CHECK-NEXT:    ptrue p0.b, vl8
+; CHECK-NEXT:    uzp1 z2.b, z3.b, z3.b
+; CHECK-NEXT:    uzp1 z3.b, z4.b, z4.b
+; CHECK-NEXT:    splice z1.b, p0, z1.b, z0.b
+; CHECK-NEXT:    splice z3.b, p0, z3.b, z2.b
+; CHECK-NEXT:    orr z0.d, z1.d, z3.d
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    orr z0.d, z3.d, z1.d
 ; CHECK-NEXT:    orv b0, p0, z0.b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
   %v0 = bitcast ptr %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = bitcast float* %b to <16 x float>*
   %v4 = load <16 x float>, <16 x float>* %v3, align 4
   %v5 = fcmp une <16 x float> %v4, zeroinitializer
   %v6 = or <16 x i1> %v2, %v5
   %v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6)
   ret i1 %v7
 }
 
 declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>)
 
 ;
 ; AND reduction.
 ;
 
 define i1 @ptest_and_v16i1(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: ptest_and_v16i1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
+; CHECK-NEXT:    ldp q0, q1, [x0, #32]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldp q0, q2, [x0, #32]
 ; CHECK-NEXT:    ptrue p1.h, vl4
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    ldp q3, q4, [x0]
-; CHECK-NEXT:    fcmne p2.s, p0/z, z2.s, z1.s
-; CHECK-NEXT:    fcmne p3.s, p0/z, z0.s, z1.s
+; CHECK-NEXT:    fcmne p3.s, p0/z, z0.s, #0.0
+; CHECK-NEXT:    ldp q2, q3, [x0]
+; CHECK-NEXT:    fcmne p2.s, p0/z, z1.s, #0.0
+; CHECK-NEXT:    mov z1.s, p3/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    mov z0.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z2.s, p3/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
-; CHECK-NEXT:    splice z2.h, p1, z2.h, z0.h
-; CHECK-NEXT:    ldp q0, q5, [x1, #32]
-; CHECK-NEXT:    fcmne p2.s, p0/z, z4.s, z1.s
-; CHECK-NEXT:    uzp1 z2.b, z2.b, z2.b
-; CHECK-NEXT:    mov z4.s, p2/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    fcmne p2.s, p0/z, z3.s, z1.s
-; CHECK-NEXT:    mov z3.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    splice z1.h, p1, z1.h, z0.h
+; CHECK-NEXT:    fcmne p3.s, p0/z, z2.s, #0.0
+; CHECK-NEXT:    mov z4.s, p3/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    fcmne p2.s, p0/z, z3.s, #0.0
 ; CHECK-NEXT:    uzp1 z4.h, z4.h, z4.h
+; CHECK-NEXT:    ldp q3, q0, [x1, #32]
+; CHECK-NEXT:    mov z2.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
+; CHECK-NEXT:    splice z4.h, p1, z4.h, z2.h
+; CHECK-NEXT:    fcmne p3.s, p0/z, z3.s, #0.0
+; CHECK-NEXT:    mov z3.s, p3/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    ldp q5, q6, [x1]
+; CHECK-NEXT:    fcmne p2.s, p0/z, z0.s, #0.0
 ; CHECK-NEXT:    uzp1 z3.h, z3.h, z3.h
-; CHECK-NEXT:    fcmne p3.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    splice z3.h, p1, z3.h, z4.h
-; CHECK-NEXT:    fcmne p2.s, p0/z, z5.s, z1.s
-; CHECK-NEXT:    uzp1 z3.b, z3.b, z3.b
-; CHECK-NEXT:    ldp q4, q5, [x1]
 ; CHECK-NEXT:    mov z0.s, p2/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT:    fcmne p2.s, p0/z, z5.s, z1.s
-; CHECK-NEXT:    fcmne p0.s, p0/z, z4.s, z1.s
-; CHECK-NEXT:    mov z5.s, p3/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    mov z1.s, p2/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    splice z3.h, p1, z3.h, z0.h
+; CHECK-NEXT:    uzp1 z0.b, z1.b, z1.b
+; CHECK-NEXT:    uzp1 z1.b, z4.b, z4.b
+; CHECK-NEXT:    fcmne p2.s, p0/z, z6.s, #0.0
+; CHECK-NEXT:    fcmne p0.s, p0/z, z5.s, #0.0
+; CHECK-NEXT:    mov z2.s, p2/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    mov z4.s, p0/z, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    uzp1 z5.h, z5.h, z5.h
-; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
+; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
 ; CHECK-NEXT:    uzp1 z4.h, z4.h, z4.h
-; CHECK-NEXT:    splice z5.h, p1, z5.h, z0.h
-; CHECK-NEXT:    splice z4.h, p1, z4.h, z1.h
-; CHECK-NEXT:    ptrue p3.b, vl8
-; CHECK-NEXT:    uzp1 z0.b, z5.b, z5.b
-; CHECK-NEXT:    uzp1 z1.b, z4.b, z4.b
-; CHECK-NEXT:    splice z3.b, p3, z3.b, z2.b
-; CHECK-NEXT:    splice z1.b, p3, z1.b, z0.b
+; CHECK-NEXT:    splice z4.h, p1, z4.h, z2.h
+; CHECK-NEXT:    ptrue p0.b, vl8
+; CHECK-NEXT:    uzp1 z2.b, z3.b, z3.b
+; CHECK-NEXT:    uzp1 z3.b, z4.b, z4.b
+; CHECK-NEXT:    splice z1.b, p0, z1.b, z0.b
+; CHECK-NEXT:    splice z3.b, p0, z3.b, z2.b
+; CHECK-NEXT:    and z0.d, z1.d, z3.d
 ; CHECK-NEXT:    ptrue p0.b, vl16
-; CHECK-NEXT:    and z0.d, z3.d, z1.d
 ; CHECK-NEXT:    andv b0, p0, z0.b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    and w0, w8, #0x1
 ; CHECK-NEXT:    ret
   %v0 = bitcast ptr %a to <16 x float>*
   %v1 = load <16 x float>, <16 x float>* %v0, align 4
   %v2 = fcmp une <16 x float> %v1, zeroinitializer
   %v3 = bitcast float* %b to <16 x float>*

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; RBIT
 ;
 
 define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) #0 {
 ; CHECK-LABEL: bitreverse_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
 ; CHECK-NEXT:    rbit z0.h, p0/m, z0.h
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %op)
   ret <4 x i8> %res
 }
 
 define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) #0 {
 ; CHECK-LABEL: bitreverse_v8i8:
; CHECK-NEXT:    ret
   %res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op)
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) #0 {
 ; CHECK-LABEL: bitreverse_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    rbit z0.s, p0/m, z0.s
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %op)
   ret <2 x i16> %res
 }
 
 define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) #0 {
 ; CHECK-LABEL: bitreverse_v4i16:

 
 ;
 ; REVB
 ;
 
 define <2 x i16> @bswap_v2i16(<2 x i16> %op) #0 {
 ; CHECK-LABEL: bswap_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI14_0
-; CHECK-NEXT:    adrp x10, .LCPI14_2
-; CHECK-NEXT:    adrp x9, .LCPI14_1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    adrp x8, .LCPI14_3
-; CHECK-NEXT:    ldr d3, [x10, :lo12:.LCPI14_2]
-; CHECK-NEXT:    movprfx z4, z0
-; CHECK-NEXT:    lsr z4.s, p0/m, z4.s, z1.s
-; CHECK-NEXT:    ldr d2, [x9, :lo12:.LCPI14_1]
-; CHECK-NEXT:    movprfx z5, z0
-; CHECK-NEXT:    lsr z5.s, p0/m, z5.s, z2.s
-; CHECK-NEXT:    lslr z1.s, p0/m, z1.s, z0.s
-; CHECK-NEXT:    and z0.d, z0.d, z3.d
-; CHECK-NEXT:    and z3.d, z5.d, z3.d
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z2.s
-; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI14_3]
-; CHECK-NEXT:    orr z3.d, z3.d, z4.d
-; CHECK-NEXT:    orr z0.d, z1.d, z0.d
-; CHECK-NEXT:    orr z0.d, z0.d, z3.d
-; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, #24
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, #8
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsl z3.s, p0/m, z3.s, #24
+; CHECK-NEXT:    and z0.s, z0.s, #0xff00
+; CHECK-NEXT:    and z2.s, z2.s, #0xff00
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #8
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    orr z0.d, z3.d, z0.d
+; CHECK-NEXT:    orr z0.d, z0.d, z1.d
+; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %op)
   ret <2 x i16> %res
 }
 
 define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 {
 ; CHECK-LABEL: bswap_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI15_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI15_0]
-; CHECK-NEXT:    movprfx z2, z0
-; CHECK-NEXT:    lsr z2.h, p0/m, z2.h, z1.h
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    orr z0.d, z0.d, z2.d
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %op)
   ret <4 x i16> %res
 }
 
 define <8 x i16> @bswap_v8i16(<8 x i16> %op) #0 {
 ; CHECK-LABEL: bswap_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI16_0
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
-; CHECK-NEXT:    movprfx z2, z0
-; CHECK-NEXT:    lsr z2.h, p0/m, z2.h, z1.h
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    orr z0.d, z0.d, z2.d
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %op)
   ret <8 x i16> %res
 }
 
 define void @bswap_v16i16(<16 x i16>* %a) #0 {
 ; CHECK-LABEL: bswap_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI17_0
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.h, vl8
-; CHECK-NEXT:    ldp q2, q0, [x0]
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
-; CHECK-NEXT:    movprfx z3, z0
-; CHECK-NEXT:    lsr z3.h, p0/m, z3.h, z1.h
-; CHECK-NEXT:    movprfx z4, z2
-; CHECK-NEXT:    lsr z4.h, p0/m, z4.h, z1.h
-; CHECK-NEXT:    lsl z2.h, p0/m, z2.h, z1.h
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    orr z1.d, z2.d, z4.d
-; CHECK-NEXT:    orr z0.d, z0.d, z3.d
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.h, p0/m, z2.h, #8
+; CHECK-NEXT:    movprfx z3, z1
+; CHECK-NEXT:    lsr z3.h, p0/m, z3.h, #8
+; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    orr z1.d, z1.d, z3.d
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op = load <16 x i16>, <16 x i16>* %a
   %res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op)
   store <16 x i16> %res, <16 x i16>* %a
   ret void
 }
 
 define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 {
 ; CHECK-LABEL: bswap_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI18_0
-; CHECK-NEXT:    adrp x10, .LCPI18_2
-; CHECK-NEXT:    adrp x9, .LCPI18_1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI18_0]
-; CHECK-NEXT:    movprfx z4, z0
-; CHECK-NEXT:    lsr z4.s, p0/m, z4.s, z1.s
-; CHECK-NEXT:    ldr d3, [x10, :lo12:.LCPI18_2]
-; CHECK-NEXT:    ldr d2, [x9, :lo12:.LCPI18_1]
-; CHECK-NEXT:    movprfx z5, z0
-; CHECK-NEXT:    lsr z5.s, p0/m, z5.s, z2.s
-; CHECK-NEXT:    and z5.d, z5.d, z3.d
-; CHECK-NEXT:    and z3.d, z0.d, z3.d
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    movprfx z1, z3
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    orr z2.d, z5.d, z4.d
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, #24
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, #8
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsl z3.s, p0/m, z3.s, #24
+; CHECK-NEXT:    and z0.s, z0.s, #0xff00
+; CHECK-NEXT:    and z2.s, z2.s, #0xff00
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #8
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    orr z0.d, z3.d, z0.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op)
   ret <2 x i32> %res
 }
 
 define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 {
 ; CHECK-LABEL: bswap_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI19_0
-; CHECK-NEXT:    adrp x10, .LCPI19_2
-; CHECK-NEXT:    adrp x9, .LCPI19_1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI19_0]
-; CHECK-NEXT:    movprfx z4, z0
-; CHECK-NEXT:    lsr z4.s, p0/m, z4.s, z1.s
-; CHECK-NEXT:    ldr q3, [x10, :lo12:.LCPI19_2]
-; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI19_1]
-; CHECK-NEXT:    movprfx z5, z0
-; CHECK-NEXT:    lsr z5.s, p0/m, z5.s, z2.s
-; CHECK-NEXT:    and z5.d, z5.d, z3.d
-; CHECK-NEXT:    and z3.d, z0.d, z3.d
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    movprfx z1, z3
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    orr z2.d, z5.d, z4.d
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.s, p0/m, z1.s, #24
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, #8
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsl z3.s, p0/m, z3.s, #24
+; CHECK-NEXT:    and z0.s, z0.s, #0xff00
+; CHECK-NEXT:    and z2.s, z2.s, #0xff00
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #8
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    orr z0.d, z3.d, z0.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op)
   ret <4 x i32> %res
 }
 
 define void @bswap_v8i32(<8 x i32>* %a) #0 {
 ; CHECK-LABEL: bswap_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI20_0
-; CHECK-NEXT:    adrp x9, .LCPI20_1
-; CHECK-NEXT:    ldp q4, q1, [x0]
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.s, vl4
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI20_0]
-; CHECK-NEXT:    adrp x8, .LCPI20_2
-; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI20_1]
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.s, p0/m, z2.s, #24
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsr z3.s, p0/m, z3.s, #8
+; CHECK-NEXT:    movprfx z4, z1
+; CHECK-NEXT:    lsr z4.s, p0/m, z4.s, #24
 ; CHECK-NEXT:    movprfx z5, z1
-; CHECK-NEXT:    lsr z5.s, p0/m, z5.s, z0.s
-; CHECK-NEXT:    movprfx z6, z1
-; CHECK-NEXT:    lsr z6.s, p0/m, z6.s, z2.s
-; CHECK-NEXT:    movprfx z7, z1
-; CHECK-NEXT:    lsl z7.s, p0/m, z7.s, z0.s
-; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI20_2]
-; CHECK-NEXT:    movprfx z16, z4
-; CHECK-NEXT:    lsr z16.s, p0/m, z16.s, z2.s
-; CHECK-NEXT:    and z1.d, z1.d, z3.d
-; CHECK-NEXT:    and z6.d, z6.d, z3.d
-; CHECK-NEXT:    and z16.d, z16.d, z3.d
-; CHECK-NEXT:    and z3.d, z4.d, z3.d
-; CHECK-NEXT:    orr z5.d, z6.d, z5.d
-; CHECK-NEXT:    movprfx z6, z4
-; CHECK-NEXT:    lsr z6.s, p0/m, z6.s, z0.s
-; CHECK-NEXT:    lslr z0.s, p0/m, z0.s, z4.s
-; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT:    lslr z2.s, p0/m, z2.s, z3.s
-; CHECK-NEXT:    orr z3.d, z16.d, z6.d
+; CHECK-NEXT:    lsr z5.s, p0/m, z5.s, #8
+; CHECK-NEXT:    and z3.s, z3.s, #0xff00
+; CHECK-NEXT:    and z5.s, z5.s, #0xff00
+; CHECK-NEXT:    orr z2.d, z3.d, z2.d
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsl z3.s, p0/m, z3.s, #24
+; CHECK-NEXT:    orr z4.d, z5.d, z4.d
+; CHECK-NEXT:    movprfx z5, z1
+; CHECK-NEXT:    lsl z5.s, p0/m, z5.s, #24
+; CHECK-NEXT:    and z1.s, z1.s, #0xff00
+; CHECK-NEXT:    and z0.s, z0.s, #0xff00
+; CHECK-NEXT:    lsl z1.s, p0/m, z1.s, #8
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #8
+; CHECK-NEXT:    orr z1.d, z5.d, z1.d
+; CHECK-NEXT:    orr z0.d, z3.d, z0.d
+; CHECK-NEXT:    orr z1.d, z1.d, z4.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
-; CHECK-NEXT:    orr z1.d, z7.d, z1.d
-; CHECK-NEXT:    orr z0.d, z0.d, z3.d
-; CHECK-NEXT:    orr z1.d, z1.d, z5.d
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op = load <8 x i32>, <8 x i32>* %a
   %res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op)
   store <8 x i32> %res, <8 x i32>* %a
   ret void
 }
 
 define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
 ; CHECK-LABEL: bswap_v1i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #56
-; CHECK-NEXT:    mov w9, #40
-; CHECK-NEXT:    mov w10, #65280
-; CHECK-NEXT:    mov w11, #24
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    mov w8, #16711680
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    mov w9, #8
-; CHECK-NEXT:    fmov d3, x10
-; CHECK-NEXT:    movprfx z7, z0
-; CHECK-NEXT:    lsr z7.d, p0/m, z7.d, z1.d
-; CHECK-NEXT:    fmov d5, x8
-; CHECK-NEXT:    mov w8, #-16777216
-; CHECK-NEXT:    movprfx z16, z0
-; CHECK-NEXT:    lsr z16.d, p0/m, z16.d, z2.d
-; CHECK-NEXT:    fmov d4, x11
-; CHECK-NEXT:    fmov d6, x9
-; CHECK-NEXT:    and z16.d, z16.d, z3.d
-; CHECK-NEXT:    fmov d17, x8
-; CHECK-NEXT:    orr z7.d, z16.d, z7.d
-; CHECK-NEXT:    movprfx z16, z0
-; CHECK-NEXT:    lsr z16.d, p0/m, z16.d, z4.d
-; CHECK-NEXT:    movprfx z18, z0
-; CHECK-NEXT:    lsr z18.d, p0/m, z18.d, z6.d
-; CHECK-NEXT:    and z16.d, z16.d, z5.d
-; CHECK-NEXT:    and z5.d, z0.d, z5.d
-; CHECK-NEXT:    and z18.d, z18.d, z17.d
-; CHECK-NEXT:    and z17.d, z0.d, z17.d
-; CHECK-NEXT:    lslr z6.d, p0/m, z6.d, z17.d
-; CHECK-NEXT:    lslr z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT:    and z3.d, z0.d, z3.d
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    orr z16.d, z18.d, z16.d
-; CHECK-NEXT:    movprfx z1, z3
-; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, z2.d
-; CHECK-NEXT:    orr z2.d, z4.d, z6.d
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    orr z1.d, z16.d, z7.d
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #56
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #40
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsr z3.d, p0/m, z3.d, #24
+; CHECK-NEXT:    movprfx z4, z0
+; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #8
+; CHECK-NEXT:    mov z5.d, z0.d
+; CHECK-NEXT:    and z2.d, z2.d, #0xff00
+; CHECK-NEXT:    and z3.d, z3.d, #0xff0000
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    mov z2.d, z0.d
+; CHECK-NEXT:    and z4.d, z4.d, #0xff000000
+; CHECK-NEXT:    and z5.d, z5.d, #0xff000000
+; CHECK-NEXT:    orr z3.d, z4.d, z3.d
+; CHECK-NEXT:    and z2.d, z2.d, #0xff0000
+; CHECK-NEXT:    movprfx z4, z5
+; CHECK-NEXT:    lsl z4.d, p0/m, z4.d, #8
+; CHECK-NEXT:    movprfx z5, z0
+; CHECK-NEXT:    lsl z5.d, p0/m, z5.d, #56
+; CHECK-NEXT:    and z0.d, z0.d, #0xff00
+; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, #24
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #40
+; CHECK-NEXT:    orr z2.d, z2.d, z4.d
+; CHECK-NEXT:    orr z0.d, z5.d, z0.d
+; CHECK-NEXT:    orr z1.d, z3.d, z1.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op)
   ret <1 x i64> %res
 }
 
 define <2 x i64> @bswap_v2i64(<2 x i64> %op) #0 {
 ; CHECK-LABEL: bswap_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI22_0
-; CHECK-NEXT:    adrp x9, .LCPI22_1
-; CHECK-NEXT:    adrp x10, .LCPI22_2
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_0]
-; CHECK-NEXT:    adrp x8, .LCPI22_3
-; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI22_1]
-; CHECK-NEXT:    adrp x9, .LCPI22_4
-; CHECK-NEXT:    ldr q3, [x10, :lo12:.LCPI22_2]
-; CHECK-NEXT:    adrp x10, .LCPI22_5
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI22_3]
-; CHECK-NEXT:    adrp x8, .LCPI22_6
-; CHECK-NEXT:    ldr q5, [x9, :lo12:.LCPI22_4]
-; CHECK-NEXT:    movprfx z7, z0
-; CHECK-NEXT:    lsr z7.d, p0/m, z7.d, z1.d
-; CHECK-NEXT:    movprfx z16, z0
-; CHECK-NEXT:    lsr z16.d, p0/m, z16.d, z2.d
-; CHECK-NEXT:    ldr q6, [x10, :lo12:.LCPI22_5]
-; CHECK-NEXT:    ldr q17, [x8, :lo12:.LCPI22_6]
-; CHECK-NEXT:    and z16.d, z16.d, z3.d
-; CHECK-NEXT:    orr z7.d, z16.d, z7.d
-; CHECK-NEXT:    movprfx z16, z0
-; CHECK-NEXT:    lsr z16.d, p0/m, z16.d, z4.d
-; CHECK-NEXT:    movprfx z18, z0
-; CHECK-NEXT:    lsr z18.d, p0/m, z18.d, z6.d
-; CHECK-NEXT:    and z16.d, z16.d, z5.d
-; CHECK-NEXT:    and z18.d, z18.d, z17.d
-; CHECK-NEXT:    and z17.d, z0.d, z17.d
-; CHECK-NEXT:    and z5.d, z0.d, z5.d
-; CHECK-NEXT:    lslr z6.d, p0/m, z6.d, z17.d
-; CHECK-NEXT:    lslr z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT:    and z3.d, z0.d, z3.d
-; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    orr z16.d, z18.d, z16.d
-; CHECK-NEXT:    movprfx z1, z3
-; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, z2.d
-; CHECK-NEXT:    orr z2.d, z4.d, z6.d
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    orr z1.d, z16.d, z7.d
+; CHECK-NEXT:    movprfx z1, z0
+; CHECK-NEXT:    lsr z1.d, p0/m, z1.d, #56
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #40
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsr z3.d, p0/m, z3.d, #24
+; CHECK-NEXT:    movprfx z4, z0
+; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #8
+; CHECK-NEXT:    mov z5.d, z0.d
+; CHECK-NEXT:    and z2.d, z2.d, #0xff00
+; CHECK-NEXT:    and z3.d, z3.d, #0xff0000
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    mov z2.d, z0.d
+; CHECK-NEXT:    and z4.d, z4.d, #0xff000000
+; CHECK-NEXT:    and z5.d, z5.d, #0xff000000
+; CHECK-NEXT:    orr z3.d, z4.d, z3.d
+; CHECK-NEXT:    and z2.d, z2.d, #0xff0000
+; CHECK-NEXT:    movprfx z4, z5
+; CHECK-NEXT:    lsl z4.d, p0/m, z4.d, #8
+; CHECK-NEXT:    movprfx z5, z0
+; CHECK-NEXT:    lsl z5.d, p0/m, z5.d, #56
+; CHECK-NEXT:    and z0.d, z0.d, #0xff00
+; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, #24
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #40
+; CHECK-NEXT:    orr z2.d, z2.d, z4.d
+; CHECK-NEXT:    orr z0.d, z5.d, z0.d
+; CHECK-NEXT:    orr z1.d, z3.d, z1.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z2.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z1.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op)
   ret <2 x i64> %res
 }
 
 define void @bswap_v4i64(<4 x i64>* %a) #0 {
 ; CHECK-LABEL: bswap_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI23_0
-; CHECK-NEXT:    adrp x9, .LCPI23_1
-; CHECK-NEXT:    adrp x10, .LCPI23_3
+; CHECK-NEXT:    ldp q1, q0, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ldp q1, q2, [x0]
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI23_0]
-; CHECK-NEXT:    adrp x8, .LCPI23_2
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI23_1]
-; CHECK-NEXT:    adrp x9, .LCPI23_4
-; CHECK-NEXT:    ldr q5, [x10, :lo12:.LCPI23_3]
-; CHECK-NEXT:    adrp x10, .LCPI23_6
-; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI23_2]
-; CHECK-NEXT:    adrp x8, .LCPI23_5
-; CHECK-NEXT:    ldr q6, [x9, :lo12:.LCPI23_4]
-; CHECK-NEXT:    movprfx z16, z2
-; CHECK-NEXT:    lsr z16.d, p0/m, z16.d, z3.d
-; CHECK-NEXT:    ldr q17, [x10, :lo12:.LCPI23_6]
-; CHECK-NEXT:    movprfx z18, z2
-; CHECK-NEXT:    lsr z18.d, p0/m, z18.d, z0.d
-; CHECK-NEXT:    ldr q7, [x8, :lo12:.LCPI23_5]
-; CHECK-NEXT:    movprfx z19, z2
-; CHECK-NEXT:    lsr z19.d, p0/m, z19.d, z5.d
-; CHECK-NEXT:    movprfx z20, z2
-; CHECK-NEXT:    lsr z20.d, p0/m, z20.d, z7.d
-; CHECK-NEXT:    and z16.d, z16.d, z4.d
-; CHECK-NEXT:    and z19.d, z19.d, z6.d
-; CHECK-NEXT:    and z20.d, z20.d, z17.d
-; CHECK-NEXT:    orr z16.d, z16.d, z18.d
-; CHECK-NEXT:    orr z18.d, z20.d, z19.d
-; CHECK-NEXT:    and z19.d, z2.d, z17.d
-; CHECK-NEXT:    and z20.d, z2.d, z6.d
-; CHECK-NEXT:    lsl z19.d, p0/m, z19.d, z7.d
-; CHECK-NEXT:    lsl z20.d, p0/m, z20.d, z5.d
-; CHECK-NEXT:    orr z16.d, z18.d, z16.d
-; CHECK-NEXT:    orr z18.d, z20.d, z19.d
-; CHECK-NEXT:    movprfx z19, z2
-; CHECK-NEXT:    lsl z19.d, p0/m, z19.d, z0.d
-; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    movprfx z20, z1
-; CHECK-NEXT:    lsr z20.d, p0/m, z20.d, z3.d
-; CHECK-NEXT:    lsl z2.d, p0/m, z2.d, z3.d
-; CHECK-NEXT:    movprfx z21, z1
-; CHECK-NEXT:    lsr z21.d, p0/m, z21.d, z0.d
-; CHECK-NEXT:    and z20.d, z20.d, z4.d
-; CHECK-NEXT:    orr z2.d, z19.d, z2.d
-; CHECK-NEXT:    orr z19.d, z20.d, z21.d
-; CHECK-NEXT:    movprfx z20, z1
-; CHECK-NEXT:    lsr z20.d, p0/m, z20.d, z5.d
-; CHECK-NEXT:    movprfx z21, z1
-; CHECK-NEXT:    lsr z21.d, p0/m, z21.d, z7.d
-; CHECK-NEXT:    and z20.d, z20.d, z6.d
-; CHECK-NEXT:    and z21.d, z21.d, z17.d
-; CHECK-NEXT:    and z17.d, z1.d, z17.d
-; CHECK-NEXT:    and z6.d, z1.d, z6.d
-; CHECK-NEXT:    lslr z7.d, p0/m, z7.d, z17.d
-; CHECK-NEXT:    lslr z5.d, p0/m, z5.d, z6.d
-; CHECK-NEXT:    lslr z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    orr z20.d, z21.d, z20.d
-; CHECK-NEXT:    and z4.d, z1.d, z4.d
-; CHECK-NEXT:    movprfx z1, z4
-; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, z3.d
-; CHECK-NEXT:    orr z3.d, z5.d, z7.d
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    orr z1.d, z20.d, z19.d
+; CHECK-NEXT:    movprfx z2, z0
+; CHECK-NEXT:    lsr z2.d, p0/m, z2.d, #56
+; CHECK-NEXT:    movprfx z3, z0
+; CHECK-NEXT:    lsr z3.d, p0/m, z3.d, #40
+; CHECK-NEXT:    movprfx z4, z0
+; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #24
+; CHECK-NEXT:    movprfx z5, z0
+; CHECK-NEXT:    lsr z5.d, p0/m, z5.d, #8
+; CHECK-NEXT:    and z3.d, z3.d, #0xff00
+; CHECK-NEXT:    and z4.d, z4.d, #0xff0000
+; CHECK-NEXT:    and z5.d, z5.d, #0xff000000
+; CHECK-NEXT:    orr z2.d, z3.d, z2.d
+; CHECK-NEXT:    orr z3.d, z5.d, z4.d
+; CHECK-NEXT:    mov z6.d, z0.d
+; CHECK-NEXT:    mov z7.d, z0.d
+; CHECK-NEXT:    movprfx z16, z0
+; CHECK-NEXT:    lsl z16.d, p0/m, z16.d, #56
+; CHECK-NEXT:    orr z2.d, z3.d, z2.d
+; CHECK-NEXT:    and z6.d, z6.d, #0xff000000
+; CHECK-NEXT:    and z7.d, z7.d, #0xff0000
+; CHECK-NEXT:    movprfx z3, z6
+; CHECK-NEXT:    lsl z3.d, p0/m, z3.d, #8
+; CHECK-NEXT:    movprfx z4, z7
+; CHECK-NEXT:    lsl z4.d, p0/m, z4.d, #24
+; CHECK-NEXT:    orr z3.d, z4.d, z3.d
+; CHECK-NEXT:    movprfx z4, z1
+; CHECK-NEXT:    lsr z4.d, p0/m, z4.d, #40
+; CHECK-NEXT:    and z0.d, z0.d, #0xff00
+; CHECK-NEXT:    movprfx z5, z1
+; CHECK-NEXT:    lsr z5.d, p0/m, z5.d, #56
+; CHECK-NEXT:    and z4.d, z4.d, #0xff00
+; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, #40
+; CHECK-NEXT:    orr z4.d, z4.d, z5.d
+; CHECK-NEXT:    movprfx z5, z1
+; CHECK-NEXT:    lsr z5.d, p0/m, z5.d, #24
+; CHECK-NEXT:    movprfx z7, z1
+; CHECK-NEXT:    lsr z7.d, p0/m, z7.d, #8
+; CHECK-NEXT:    orr z0.d, z16.d, z0.d
+; CHECK-NEXT:    mov z6.d, z1.d
+; CHECK-NEXT:    mov z16.d, z1.d
+; CHECK-NEXT:    and z5.d, z5.d, #0xff0000
+; CHECK-NEXT:    and z7.d, z7.d, #0xff000000
+; CHECK-NEXT:    orr z5.d, z7.d, z5.d
+; CHECK-NEXT:    and z6.d, z6.d, #0xff000000
+; CHECK-NEXT:    and z16.d, z16.d, #0xff0000
+; CHECK-NEXT:    movprfx z7, z1
+; CHECK-NEXT:    lsl z7.d, p0/m, z7.d, #56
+; CHECK-NEXT:    and z1.d, z1.d, #0xff00
+; CHECK-NEXT:    lsl z6.d, p0/m, z6.d, #8
+; CHECK-NEXT:    lsl z16.d, p0/m, z16.d, #24
+; CHECK-NEXT:    lsl z1.d, p0/m, z1.d, #40
+; CHECK-NEXT:    orr z6.d, z16.d, z6.d
+; CHECK-NEXT:    orr z1.d, z7.d, z1.d
+; CHECK-NEXT:    orr z4.d, z5.d, z4.d
+; CHECK-NEXT:    orr z1.d, z1.d, z6.d
 ; CHECK-NEXT:    orr z0.d, z0.d, z3.d
-; CHECK-NEXT:    orr z2.d, z2.d, z18.d
-; CHECK-NEXT:    orr z0.d, z0.d, z1.d
-; CHECK-NEXT:    orr z1.d, z2.d, z16.d
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    orr z1.d, z1.d, z4.d
+; CHECK-NEXT:    orr z0.d, z0.d, z2.d
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op = load <4 x i64>, <4 x i64>* %a
   %res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op)
   store <4 x i64> %res, <4 x i64>* %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) #0 {
 ; CHECK-LABEL: sdiv_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
+; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
 ; CHECK-NEXT:    asrd z0.h, p0/m, z0.h, #5
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = sdiv <4 x i8> %op1, shufflevector (<4 x i8> insertelement (<4 x i8> poison, i8 32, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)
   ret <4 x i8> %res
 }
 
 define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) #0 {
; CHECK-NEXT:    ret
   %res = sdiv <32 x i8> %op1, shufflevector (<32 x i8> insertelement (<32 x i8> poison, i8 32, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)
   store <32 x i8> %res, <32 x i8>* %a
   ret void
 }
 
 define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) #0 {
 ; CHECK-LABEL: sdiv_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
-; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, #16
+; CHECK-NEXT:    asr z0.s, p0/m, z0.s, #16
 ; CHECK-NEXT:    asrd z0.s, p0/m, z0.s, #5
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = sdiv <2 x i16> %op1, shufflevector (<2 x i16> insertelement (<2 x i16> poison, i16 32, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)
   ret <2 x i16> %res
 }
 
 define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) #0 {

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 
 target triple = "aarch64-unknown-linux-gnu"
 
 ;
 ; DUP (integer)
 ;
 
 define <4 x i8> @splat_v4i8(i8 %a) #0 {
 ; CHECK-LABEL: splat_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strh w0, [sp, #14]
-; CHECK-NEXT:    strh w0, [sp, #12]
-; CHECK-NEXT:    strh w0, [sp, #10]
-; CHECK-NEXT:    strh w0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    mov z0.h, w0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i8> undef, i8 %a, i64 0
   %splat = shufflevector <4 x i8> %insert, <4 x i8> undef, <4 x i32> zeroinitializer
   ret <4 x i8> %splat
 }
 
 define <8 x i8> @splat_v8i8(i8 %a) #0 {
 ; CHECK-LABEL: splat_v8i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strb w0, [sp, #15]
-; CHECK-NEXT:    strb w0, [sp, #14]
-; CHECK-NEXT:    strb w0, [sp, #13]
-; CHECK-NEXT:    strb w0, [sp, #12]
-; CHECK-NEXT:    strb w0, [sp, #11]
-; CHECK-NEXT:    strb w0, [sp, #10]
-; CHECK-NEXT:    strb w0, [sp, #9]
-; CHECK-NEXT:    strb w0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    mov z0.b, w0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i8> undef, i8 %a, i64 0
   %splat = shufflevector <8 x i8> %insert, <8 x i8> undef, <8 x i32> zeroinitializer
   ret <8 x i8> %splat
 }
 
 define <16 x i8> @splat_v16i8(i8 %a) #0 {
 ; CHECK-LABEL: splat_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strb w0, [sp, #15]
-; CHECK-NEXT:    strb w0, [sp, #14]
-; CHECK-NEXT:    strb w0, [sp, #13]
-; CHECK-NEXT:    strb w0, [sp, #12]
-; CHECK-NEXT:    strb w0, [sp, #11]
-; CHECK-NEXT:    strb w0, [sp, #10]
-; CHECK-NEXT:    strb w0, [sp, #9]
-; CHECK-NEXT:    strb w0, [sp, #8]
-; CHECK-NEXT:    strb w0, [sp, #7]
-; CHECK-NEXT:    strb w0, [sp, #6]
-; CHECK-NEXT:    strb w0, [sp, #5]
-; CHECK-NEXT:    strb w0, [sp, #4]
-; CHECK-NEXT:    strb w0, [sp, #3]
-; CHECK-NEXT:    strb w0, [sp, #2]
-; CHECK-NEXT:    strb w0, [sp, #1]
-; CHECK-NEXT:    strb w0, [sp]
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    mov z0.b, w0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <16 x i8> undef, i8 %a, i64 0
   %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
   ret <16 x i8> %splat
 }
 
 define void @splat_v32i8(i8 %a, <32 x i8>* %b) #0 {
 ; CHECK-LABEL: splat_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strb w0, [sp, #15]
-; CHECK-NEXT:    strb w0, [sp, #14]
-; CHECK-NEXT:    strb w0, [sp, #13]
-; CHECK-NEXT:    strb w0, [sp, #12]
-; CHECK-NEXT:    strb w0, [sp, #11]
-; CHECK-NEXT:    strb w0, [sp, #10]
-; CHECK-NEXT:    strb w0, [sp, #9]
-; CHECK-NEXT:    strb w0, [sp, #8]
-; CHECK-NEXT:    strb w0, [sp, #7]
-; CHECK-NEXT:    strb w0, [sp, #6]
-; CHECK-NEXT:    strb w0, [sp, #5]
-; CHECK-NEXT:    strb w0, [sp, #4]
-; CHECK-NEXT:    strb w0, [sp, #3]
-; CHECK-NEXT:    strb w0, [sp, #2]
-; CHECK-NEXT:    strb w0, [sp, #1]
-; CHECK-NEXT:    strb w0, [sp]
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    mov z0.b, w0
 ; CHECK-NEXT:    stp q0, q0, [x1]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <32 x i8> undef, i8 %a, i64 0
   %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
   store <32 x i8> %splat, <32 x i8>* %b
   ret void
 }
 
 define <2 x i16> @splat_v2i16(i16 %a) #0 {
 ; CHECK-LABEL: splat_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp w0, w0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    mov z0.s, w0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i16> undef, i16 %a, i64 0
   %splat = shufflevector <2 x i16> %insert, <2 x i16> undef, <2 x i32> zeroinitializer
   ret <2 x i16> %splat
 }
 
 define <4 x i16> @splat_v4i16(i16 %a) #0 {
 ; CHECK-LABEL: splat_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strh w0, [sp, #14]
-; CHECK-NEXT:    strh w0, [sp, #12]
-; CHECK-NEXT:    strh w0, [sp, #10]
-; CHECK-NEXT:    strh w0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    mov z0.h, w0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i16> undef, i16 %a, i64 0
   %splat = shufflevector <4 x i16> %insert, <4 x i16> undef, <4 x i32> zeroinitializer
   ret <4 x i16> %splat
 }
 
 define <8 x i16> @splat_v8i16(i16 %a) #0 {
 ; CHECK-LABEL: splat_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strh w0, [sp, #14]
-; CHECK-NEXT:    strh w0, [sp, #12]
-; CHECK-NEXT:    strh w0, [sp, #10]
-; CHECK-NEXT:    strh w0, [sp, #8]
-; CHECK-NEXT:    strh w0, [sp, #6]
-; CHECK-NEXT:    strh w0, [sp, #4]
-; CHECK-NEXT:    strh w0, [sp, #2]
-; CHECK-NEXT:    strh w0, [sp]
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    mov z0.h, w0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i16> undef, i16 %a, i64 0
   %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
   ret <8 x i16> %splat
 }
 
 define void @splat_v16i16(i16 %a, <16 x i16>* %b) #0 {
 ; CHECK-LABEL: splat_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    strh w0, [sp, #14]
-; CHECK-NEXT:    strh w0, [sp, #12]
-; CHECK-NEXT:    strh w0, [sp, #10]
-; CHECK-NEXT:    strh w0, [sp, #8]
-; CHECK-NEXT:    strh w0, [sp, #6]
-; CHECK-NEXT:    strh w0, [sp, #4]
-; CHECK-NEXT:    strh w0, [sp, #2]
-; CHECK-NEXT:    strh w0, [sp]
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    mov z0.h, w0
 ; CHECK-NEXT:    stp q0, q0, [x1]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <16 x i16> undef, i16 %a, i64 0
   %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
   store <16 x i16> %splat, <16 x i16>* %b
   ret void
 }
 
 define <2 x i32> @splat_v2i32(i32 %a) #0 {
 ; CHECK-LABEL: splat_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp w0, w0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    mov z0.s, w0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i32> undef, i32 %a, i64 0
   %splat = shufflevector <2 x i32> %insert, <2 x i32> undef, <2 x i32> zeroinitializer
   ret <2 x i32> %splat
 }
 
 define <4 x i32> @splat_v4i32(i32 %a) #0 {
 ; CHECK-LABEL: splat_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp w0, w0, [sp, #8]
-; CHECK-NEXT:    stp w0, w0, [sp]
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    mov z0.s, w0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i32> undef, i32 %a, i64 0
   %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat
 }
 
 define void @splat_v8i32(i32 %a, <8 x i32>* %b) #0 {
 ; CHECK-LABEL: splat_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp w0, w0, [sp, #8]
-; CHECK-NEXT:    stp w0, w0, [sp]
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    mov z0.s, w0
 ; CHECK-NEXT:    stp q0, q0, [x1]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i32> undef, i32 %a, i64 0
   %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %splat, <8 x i32>* %b
   ret void
 }
 
 define <1 x i64> @splat_v1i64(i64 %a) #0 {
 ; CHECK-LABEL: splat_v1i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov d0, x0
+; CHECK-NEXT:    mov z0.d, x0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <1 x i64> undef, i64 %a, i64 0
   %splat = shufflevector <1 x i64> %insert, <1 x i64> undef, <1 x i32> zeroinitializer
   ret <1 x i64> %splat
 }
 
 define <2 x i64> @splat_v2i64(i64 %a) #0 {
 ; CHECK-LABEL: splat_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    stp x0, x0, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    mov z0.d, x0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x i64> undef, i64 %a, i64 0
   %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat
 }
 
 define void @splat_v4i64(i64 %a, <4 x i64>* %b) #0 {
 ; CHECK-LABEL: splat_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    stp x0, x0, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    mov z0.d, x0
 ; CHECK-NEXT:    stp q0, q0, [x1]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i64> undef, i64 %a, i64 0
   %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %splat, <4 x i64>* %b
   ret void
 }
 
 ;
 ; DUP (floating-point)
 ;
 
 define <2 x half> @splat_v2f16(half %a) #0 {
 ; CHECK-LABEL: splat_v2f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    str h0, [sp, #10]
-; CHECK-NEXT:    str h0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x half> undef, half %a, i64 0
   %splat = shufflevector <2 x half> %insert, <2 x half> undef, <2 x i32> zeroinitializer
   ret <2 x half> %splat
 }
 
 define <4 x half> @splat_v4f16(half %a) #0 {
 ; CHECK-LABEL: splat_v4f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    str h0, [sp, #14]
-; CHECK-NEXT:    str h0, [sp, #12]
-; CHECK-NEXT:    str h0, [sp, #10]
-; CHECK-NEXT:    str h0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x half> undef, half %a, i64 0
   %splat = shufflevector <4 x half> %insert, <4 x half> undef, <4 x i32> zeroinitializer
   ret <4 x half> %splat
 }
 
 define <8 x half> @splat_v8f16(half %a) #0 {
 ; CHECK-LABEL: splat_v8f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    str h0, [sp, #14]
-; CHECK-NEXT:    str h0, [sp, #12]
-; CHECK-NEXT:    str h0, [sp, #10]
-; CHECK-NEXT:    str h0, [sp, #8]
-; CHECK-NEXT:    str h0, [sp, #6]
-; CHECK-NEXT:    str h0, [sp, #4]
-; CHECK-NEXT:    str h0, [sp, #2]
-; CHECK-NEXT:    str h0, [sp]
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x half> undef, half %a, i64 0
   %splat = shufflevector <8 x half> %insert, <8 x half> undef, <8 x i32> zeroinitializer
   ret <8 x half> %splat
 }
 
 define void @splat_v16f16(half %a, <16 x half>* %b) #0 {
 ; CHECK-LABEL: splat_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    str h0, [sp, #14]
-; CHECK-NEXT:    str h0, [sp, #12]
-; CHECK-NEXT:    str h0, [sp, #10]
-; CHECK-NEXT:    str h0, [sp, #8]
-; CHECK-NEXT:    str h0, [sp, #6]
-; CHECK-NEXT:    str h0, [sp, #4]
-; CHECK-NEXT:    str h0, [sp, #2]
-; CHECK-NEXT:    str h0, [sp]
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    stp q0, q0, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <16 x half> undef, half %a, i64 0
   %splat = shufflevector <16 x half> %insert, <16 x half> undef, <16 x i32> zeroinitializer
   store <16 x half> %splat, <16 x half>* %b
   ret void
 }
 
 define <2 x float> @splat_v2f32(float %a, <2 x float> %op2) #0 {
 ; CHECK-LABEL: splat_v2f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp s0, s0, [sp, #8]
-; CHECK-NEXT:    ldr d0, [sp, #8]
-; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT:    mov z0.s, s0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x float> undef, float %a, i64 0
   %splat = shufflevector <2 x float> %insert, <2 x float> undef, <2 x i32> zeroinitializer
   ret <2 x float> %splat
 }
 
 define <4 x float> @splat_v4f32(float %a, <4 x float> %op2) #0 {
 ; CHECK-LABEL: splat_v4f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp s0, s0, [sp, #8]
-; CHECK-NEXT:    stp s0, s0, [sp]
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT:    mov z0.s, s0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x float> undef, float %a, i64 0
   %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %splat
 }
 
 define void @splat_v8f32(float %a, <8 x float>* %b) #0 {
 ; CHECK-LABEL: splat_v8f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    stp s0, s0, [sp, #8]
-; CHECK-NEXT:    stp s0, s0, [sp]
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT:    mov z0.s, s0
 ; CHECK-NEXT:    stp q0, q0, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x float> undef, float %a, i64 0
   %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer
   store <8 x float> %splat, <8 x float>* %b
   ret void
 }
 
 define <1 x double> @splat_v1f64(double %a, <1 x double> %op2) #0 {
 ; CHECK-LABEL: splat_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
   %insert = insertelement <1 x double> undef, double %a, i64 0
   %splat = shufflevector <1 x double> %insert, <1 x double> undef, <1 x i32> zeroinitializer
   ret <1 x double> %splat
 }
 
 define <2 x double> @splat_v2f64(double %a, <2 x double> %op2) #0 {
 ; CHECK-LABEL: splat_v2f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    stp d0, d0, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q0, [sp], #16
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT:    mov z0.d, d0
+; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; CHECK-NEXT:    ret
   %insert = insertelement <2 x double> undef, double %a, i64 0
   %splat = shufflevector <2 x double> %insert, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %splat
 }
 
 define void @splat_v4f64(double %a, <4 x double>* %b) #0 {
 ; CHECK-LABEL: splat_v4f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    stp d0, d0, [sp, #-16]!
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    ldr q0, [sp]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT:    mov z0.d, d0
 ; CHECK-NEXT:    stp q0, q0, [x0]
-; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x double> undef, double %a, i64 0
   %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer
   store <4 x double> %splat, <4 x double>* %b
   ret void
 }
 
 ;
 ; DUP (integer immediate)
 ;
 
 define void @splat_imm_v32i8(<32 x i8>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI24_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI24_0]
+; CHECK-NEXT:    mov z0.b, #1 // =0x1
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <32 x i8> undef, i8 1, i64 0
   %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
   store <32 x i8> %splat, <32 x i8>* %a
   ret void
 }
 
 define void @splat_imm_v16i16(<16 x i16>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI25_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI25_0]
+; CHECK-NEXT:    mov z0.h, #2 // =0x2
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <16 x i16> undef, i16 2, i64 0
   %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
   store <16 x i16> %splat, <16 x i16>* %a
   ret void
 }
 
 define void @splat_imm_v8i32(<8 x i32>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI26_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI26_0]
+; CHECK-NEXT:    mov z0.s, #3 // =0x3
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x i32> undef, i32 3, i64 0
   %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %splat, <8 x i32>* %a
   ret void
 }
 
 define void @splat_imm_v4i64(<4 x i64>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI27_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI27_0]
+; CHECK-NEXT:    mov z0.d, #4 // =0x4
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x i64> undef, i64 4, i64 0
   %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %splat, <4 x i64>* %a
   ret void
 }
 
 ;
 ; DUP (floating-point immediate)
 ;
 
 define void @splat_imm_v16f16(<16 x half>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI28_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI28_0]
+; CHECK-NEXT:    fmov z0.h, #5.00000000
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <16 x half> undef, half 5.0, i64 0
   %splat = shufflevector <16 x half> %insert, <16 x half> undef, <16 x i32> zeroinitializer
   store <16 x half> %splat, <16 x half>* %a
   ret void
 }
 
 define void @splat_imm_v8f32(<8 x float>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v8f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI29_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI29_0]
+; CHECK-NEXT:    fmov z0.s, #6.00000000
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <8 x float> undef, float 6.0, i64 0
   %splat = shufflevector <8 x float> %insert, <8 x float> undef, <8 x i32> zeroinitializer
   store <8 x float> %splat, <8 x float>* %a
   ret void
 }
 
 define void @splat_imm_v4f64(<4 x double>* %a) #0 {
 ; CHECK-LABEL: splat_imm_v4f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI30_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI30_0]
+; CHECK-NEXT:    fmov z0.d, #7.00000000
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   %insert = insertelement <4 x double> undef, double 7.0, i64 0
   %splat = shufflevector <4 x double> %insert, <4 x double> undef, <4 x i32> zeroinitializer
   store <4 x double> %splat, <4 x double>* %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
 define void @store_v4i8(<4 x i8>* %a) #0 {
 ; CHECK-LABEL: store_v4i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    st1b { z0.h }, p0, [x0]
 ; CHECK-NEXT:    ret
   store <4 x i8> zeroinitializer, <4 x i8>* %a
   ret void
 }
 
 define void @store_v8i8(<8 x i8>* %a) #0 {
 ; CHECK-LABEL: store_v8i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI1_0
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI1_0]
+; CHECK-NEXT:    mov z0.b, #0 // =0x0
 ; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
   store <8 x i8> zeroinitializer, <8 x i8>* %a
   ret void
 }
 
 define void @store_v16i8(<16 x i8>* %a) #0 {
 ; CHECK-LABEL: store_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI2_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
+; CHECK-NEXT:    mov z0.b, #0 // =0x0
 ; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
   store <16 x i8> zeroinitializer, <16 x i8>* %a
   ret void
 }
 
 define void @store_v32i8(<32 x i8>* %a) #0 {
 ; CHECK-LABEL: store_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI3_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI3_0]
+; CHECK-NEXT:    mov z0.b, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <32 x i8> zeroinitializer, <32 x i8>* %a
   ret void
 }
 
 define void @store_v2i16(<2 x i16>* %a) #0 {
 ; CHECK-LABEL: store_v2i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI4_0]
+; CHECK-NEXT:    mov z0.s, #0 // =0x0
 ; CHECK-NEXT:    st1h { z0.s }, p0, [x0]
 ; CHECK-NEXT:    ret
   store <2 x i16> zeroinitializer, <2 x i16>* %a
   ret void
 }
 
 define void @store_v2f16(<2 x half>* %a) #0 {
 ; CHECK-LABEL: store_v2f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI5_0
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI5_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    str w8, [x0]
 ; CHECK-NEXT:    ret
   store <2 x half> zeroinitializer, <2 x half>* %a
   ret void
 }
 
 define void @store_v4i16(<4 x i16>* %a) #0 {
 ; CHECK-LABEL: store_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI6_0
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI6_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
   store <4 x i16> zeroinitializer, <4 x i16>* %a
   ret void
 }
 
 define void @store_v4f16(<4 x half>* %a) #0 {
 ; CHECK-LABEL: store_v4f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI7_0
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI7_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
   store <4 x half> zeroinitializer, <4 x half>* %a
   ret void
 }
 
 define void @store_v8i16(<8 x i16>* %a) #0 {
 ; CHECK-LABEL: store_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI8_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI8_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
   store <8 x i16> zeroinitializer, <8 x i16>* %a
   ret void
 }
 
 define void @store_v8f16(<8 x half>* %a) #0 {
 ; CHECK-LABEL: store_v8f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI9_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI9_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
   store <8 x half> zeroinitializer, <8 x half>* %a
   ret void
 }
 
 define void @store_v16i16(<16 x i16>* %a) #0 {
 ; CHECK-LABEL: store_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI10_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI10_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <16 x i16> zeroinitializer, <16 x i16>* %a
   ret void
 }
 
 define void @store_v16f16(<16 x half>* %a) #0 {
 ; CHECK-LABEL: store_v16f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI11_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI11_0]
+; CHECK-NEXT:    mov z0.h, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <16 x half> zeroinitializer, <16 x half>* %a
   ret void
 }
 
 define void @store_v2i32(<2 x i32>* %a) #0 {
 ; CHECK-LABEL: store_v2i32:

 ; CHECK-NEXT:    ret
   store <4 x float> zeroinitializer, <4 x float>* %a
   ret void
 }
 
 define void @store_v8i32(<8 x i32>* %a) #0 {
 ; CHECK-LABEL: store_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI16_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI16_0]
+; CHECK-NEXT:    mov z0.s, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <8 x i32> zeroinitializer, <8 x i32>* %a
   ret void
 }
 
 define void @store_v8f32(<8 x float>* %a) #0 {
 ; CHECK-LABEL: store_v8f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI17_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI17_0]
+; CHECK-NEXT:    mov z0.s, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <8 x float> zeroinitializer, <8 x float>* %a
   ret void
 }
 
 define void @store_v1i64(<1 x i64>* %a) #0 {
 ; CHECK-LABEL: store_v1i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov d0, xzr
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
 ; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
   store <1 x i64> zeroinitializer, <1 x i64>* %a
   ret void
 }
 
 define void @store_v1f64(<1 x double>* %a) #0 {
 ; CHECK-LABEL: store_v1f64:

 ; CHECK-NEXT:    ret
   store <2 x double> zeroinitializer, <2 x double>* %a
   ret void
 }
 
 define void @store_v4i64(<4 x i64>* %a) #0 {
 ; CHECK-LABEL: store_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI22_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI22_0]
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <4 x i64> zeroinitializer, <4 x i64>* %a
   ret void
 }
 
 define void @store_v4f64(<4 x double>* %a) #0 {
 ; CHECK-LABEL: store_v4f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI23_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI23_0]
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
 ; CHECK-NEXT:    stp q0, q0, [x0]
 ; CHECK-NEXT:    ret
   store <4 x double> zeroinitializer, <4 x double>* %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }