[AArch64][SME]: Use SVE mov instruction for FPR128 registers in streaming-compatible mode.

[hassnaa-arm]

Summary

1- in streaming mode, use SVE OR instruction instead of NEON OR,

during copying phyReg.(AArch64InstrInfo::copyPhysReg).

2- add test file: register-mov.ll.

[hassnaa-arm]

add test file: register-mov.ll to test code changes in AArch64InstrInfo::copyPhysReg.

[hassnaa-arm]

Remove not related testing files.

[sdesmalen]

Thanks for this change @hassnaa-arm. The patch looks good, just added two nits.

Could you change the title to something like this:

[AArch64][SME]: Use SVE mov instruction for FPR128 registers in streaming-compatible mode.

such that it has:

• Proper capitalisation
• [AArch64] as the target description, [SME] for the sub-topic
• A slightly more descriptive title

llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll

6

nit: Can you add a comment to describe the rationale behind the test (i.e. that a NEON Q-register mov is not valid in streaming mode, but an SVE Z-register mov is)

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if (AArch64::WSeqPairsClassRegClass.contains(DestReg) &&
     static const unsigned Indices[] = {AArch64::sube32, AArch64::subo32};
     copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs,
                     AArch64::WZR, Indices);
     return;
   }
 
   if (AArch64::FPR128RegClass.contains(DestReg) &&
       AArch64::FPR128RegClass.contains(SrcReg)) {
-    if (Subtarget.hasNEON()) {
+    if (Subtarget.forceStreamingCompatibleSVE()) {
+      BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ))
+          .addReg(AArch64::Z0 + (DestReg - AArch64::Q0), RegState::Define)
+          .addReg(AArch64::Z0 + (SrcReg - AArch64::Q0))
+          .addReg(AArch64::Z0 + (SrcReg - AArch64::Q0));
+    } else if (Subtarget.hasNEON()) {
       BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
           .addReg(SrcReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
       BuildMI(MBB, I, DL, get(AArch64::STRQpre))
           .addReg(AArch64::SP, RegState::Define)
           .addReg(SrcReg, getKillRegState(KillSrc))
           .addReg(AArch64::SP)

llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -force-streaming-compatible-sve  < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; A NEON Q-register mov is not valid in streaming mode, but an SVE Z-register mov is.
+define fp128 @test_streaming_compatible_register_mov(fp128 %q0, fp128 %q1) #0 {
+; CHECK-LABEL: test_streaming_compatible_register_mov:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    ret
+  ret fp128 %q1
+}
+
+attributes #0 = { "target-features"="+sve" }