[X86] Allow no X87 on 32-bit

[pengfei]

Summary

This patch is an alternative of D100091. It solved the problems in f80 type lowering.

[LuoYuanke]

llvm/lib/Target/X86/X86InstrFormats.td

479

Remove "Not Predicated" of the comments?

llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll

140

Is it because the last 16 bit value is stored in cx?

195

Add a case to convert from x86_fp80 to int?

[pengfei]

Address review comments.

llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll

140

Yes. We first bitcast f80 to i80, then extend it to i96. We cleared the upper 16 bits during this stage.

[LuoYuanke]

LGTM, but pls wait for a few days so that other reviewers' comments can be addressed.

llvm/include/llvm/CodeGen/TargetLowering.h

public:
   }
 
   /// For types supported by the target, this is an identity function.  For
   /// types that must be promoted to larger types, this returns the larger type
   /// to promote to.  For integer types that are larger than the largest integer
   /// register, this contains one step in the expansion to get to the smaller
   /// register. For illegal floating point types, this returns the integer type
   /// to transform to.
-  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
+  virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
     return getTypeConversion(Context, VT).second;
   }
 
   /// For types supported by the target, this is an identity function.  For
   /// types that must be expanded (i.e. integer types that are larger than the
   /// largest integer register or illegal floating point types), this returns
   /// the largest legal type it will be expanded to.
   EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
   assert((OpIdEntry == 0) && "Node is already promoted!");
   OpIdEntry = getTableId(Result);
   Result->setFlags(Op->getFlags());
 
   DAG.transferDbgValues(Op, Result);
 }
 
 void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
-  assert(Result.getValueType() ==
-         TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
+#ifndef NDEBUG
+  EVT VT = Result.getValueType();
+  LLVMContext &Ctx = *DAG.getContext();
+  assert((VT == EVT::getIntegerVT(Ctx, 80) ||
+          VT == TLI.getTypeToTransformTo(Ctx, Op.getValueType())) &&
          "Invalid type for softened float");
+#endif
   AnalyzeNewValue(Result);
 
   auto &OpIdEntry = SoftenedFloats[getTableId(Op)];
   assert((OpIdEntry == 0) && "Node is already converted to integer!");
   OpIdEntry = getTableId(Result);
 }
 
 void DAGTypeLegalizer::SetPromotedFloat(SDValue Op, SDValue Result) {

llvm/lib/CodeGen/TargetLoweringBase.cpp

void TargetLoweringBase::computeRegisterProperties(
   // expand it to i128 and we will be generating soft float library calls.
   if (!isTypeLegal(MVT::f128)) {
     NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
     RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
     TransformToType[MVT::f128] = MVT::i128;
     ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
   }
 
+  // Decide how to handle f80. If the target does not have native f80 support,
+  // expand it to i96 and we will be generating soft float library calls.
+  if (!isTypeLegal(MVT::f80)) {
+    NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
+    RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
+    TransformToType[MVT::f80] = MVT::i32;
+    ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);
+  }
+
   // Decide how to handle f64. If the target does not have native f64 support,
   // expand it to i64 and we will be generating soft float library calls.
   if (!isTypeLegal(MVT::f64)) {
     NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
     RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
     TransformToType[MVT::f64] = MVT::i64;
     ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
   }

llvm/lib/Target/X86/X86ISelLowering.h

bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
                                unsigned Factor) const override;
 
     SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value,
                                    SDValue Addr, SelectionDAG &DAG)
                                    const override;
 
     Align getPrefLoopAlignment(MachineLoop *ML) const override;
 
+    EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const override {
+      if (VT == MVT::f80)
+        return EVT::getIntegerVT(Context, 96);
+      return TargetLoweringBase::getTypeToTransformTo(Context, VT);
+    }
+
   protected:
     std::pair<const TargetRegisterClass *, uint8_t>
     findRepresentativeClass(const TargetRegisterInfo *TRI,
                             MVT VT) const override;
 
   private:
     /// Keep a reference to the X86Subtarget around so that we can
     /// make the right decision when generating code for different targets.

llvm/lib/Target/X86/X86ISelLowering.cpp

if (SrcVT == MVT::i16 && (UseSSEReg || VT == MVT::f128)) {
     SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, Src);
     if (IsStrict)
       return DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, {VT, MVT::Other},
                          {Chain, Ext});
 
     return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Ext);
   }
 
-  if (VT == MVT::f128)
+  if (VT == MVT::f128 || !Subtarget.hasX87())
     return SDValue();
 
   SDValue ValueToStore = Src;
   if (SrcVT == MVT::i64 && Subtarget.hasSSE2() && !Subtarget.is64Bit())
     // Bitcasting to f64 here allows us to do a single 64-bit store from
     // an SSE register, avoiding the store forwarding penalty that would come
     // with two 32-bit stores.
     ValueToStore = DAG.getBitcast(MVT::f64, ValueToStore);

llvm/lib/Target/X86/X86InstrFormats.td

class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
   let CodeSize = 3;
 }
 
 // FPStack Instruction Templates:
 // FPI - Floating Point Instruction template.
 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
   : I<o, F, outs, ins, asm, []> {
   let Defs = [FPSW];
+  let Predicates = [HasX87];
 }
 
-// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
+// FpI_ - Floating Point Pseudo Instruction template.
 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
   : PseudoI<outs, ins, pattern> {
   let FPForm = fp;
   let Defs = [FPSW];
+  let Predicates = [HasX87];
 }
 
 // Templates for instructions that use a 16- or 32-bit segmented address as
 //  their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
 //
 //   Iseg16 - 16-bit segment selector, 16-bit offset
 //   Iseg32 - 16-bit segment selector, 32-bit offset
 

llvm/lib/Target/X86/X86InstrInfo.td

 def NoVLX_Or_NoVNNI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVNNI()">;
 
 def HasBITALG    : Predicate<"Subtarget->hasBITALG()">;
 def HasPOPCNT    : Predicate<"Subtarget->hasPOPCNT()">;
 def HasAES       : Predicate<"Subtarget->hasAES()">;
 def HasVAES      : Predicate<"Subtarget->hasVAES()">;
 def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">;
 def HasFXSR      : Predicate<"Subtarget->hasFXSR()">;
+def HasX87       : Predicate<"Subtarget->hasX87()">;
 def HasXSAVE     : Predicate<"Subtarget->hasXSAVE()">;
 def HasXSAVEOPT  : Predicate<"Subtarget->hasXSAVEOPT()">;
 def HasXSAVEC    : Predicate<"Subtarget->hasXSAVEC()">;
 def HasXSAVES    : Predicate<"Subtarget->hasXSAVES()">;
 def HasPCLMUL    : Predicate<"Subtarget->hasPCLMUL()">;
 def NoVLX_Or_NoVPCLMULQDQ :
                     Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">;
 def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">;

llvm/test/CodeGen/X86/no-ret-in-x87-reg.ll

 ; SSE-NOX87-NEXT:    movl %ebp, %esp
 ; SSE-NOX87-NEXT:    popl %ebp
 ; SSE-NOX87-NEXT:    retl
 entry:
   %0 = fadd double %a, %b
   ret double %0
 }
 
-; FIXME: We should not generate x87 instructions when x87 is disabled.
 define x86_fp80 @f6(x86_fp80 %a, x86_fp80 %b) nounwind {
 ; X87-LABEL: f6:
 ; X87:       # %bb.0: # %entry
 ; X87-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X87-NEXT:    faddp %st, %st(1)
 ; X87-NEXT:    retl
 ;
 ; NOX87-LABEL: f6:
 ; NOX87:       # %bb.0: # %entry
-; NOX87-NEXT:    pushl %ebp
-; NOX87-NEXT:    movl %esp, %ebp
-; NOX87-NEXT:    andl $-8, %esp
-; NOX87-NEXT:    subl $48, %esp
-; NOX87-NEXT:    movl 20(%ebp), %eax
-; NOX87-NEXT:    movl 24(%ebp), %ecx
-; NOX87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; NOX87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; NOX87-NEXT:    movl 28(%ebp), %eax
-; NOX87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
-; NOX87-NEXT:    movl 8(%ebp), %eax
-; NOX87-NEXT:    movl 12(%ebp), %ecx
-; NOX87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
-; NOX87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; NOX87-NEXT:    movl 16(%ebp), %eax
-; NOX87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
-; NOX87-NEXT:    fldt {{[0-9]+}}(%esp)
-; NOX87-NEXT:    fldt {{[0-9]+}}(%esp)
-; NOX87-NEXT:    faddp %st, %st(1)
-; NOX87-NEXT:    fstpt (%esp)
-; NOX87-NEXT:    movl (%esp), %eax
-; NOX87-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; NOX87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; NOX87-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
-; NOX87-NEXT:    movl %ebp, %esp
-; NOX87-NEXT:    popl %ebp
+; NOX87-NEXT:    pushl %ecx
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    pushl %eax
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    calll __addxf3
+; NOX87-NEXT:    addl $24, %esp
+; NOX87-NEXT:    movzwl %cx, %ecx
 ; NOX87-NEXT:    retl
 entry:
   %0 = fadd x86_fp80 %a, %b
   ret x86_fp80 %0
 }
 
 define {float, float, float} @f7(float %a, float %b) nounwind {
 ; X87-LABEL: f7:

 ; SSE-NOX87-NEXT:    movd %xmm1, %ecx
 ; SSE-NOX87-NEXT:    retl
 entry:
   %0 = insertvalue {float, float, float} undef, float %a, 0
   %1 = insertvalue {float, float, float} %0, float %a, 1
   %2 = insertvalue {float, float, float} %1, float %b, 2
   ret {float, float, float} %2
 }
+
+define x86_fp80 @f8(i64 %a) nounwind {
+; X87-LABEL: f8:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    fildll {{[0-9]+}}(%esp)
+; X87-NEXT:    retl
+;
+; NOX87-LABEL: f8:
+; NOX87:       # %bb.0: # %entry
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    calll __floatdixf
+; NOX87-NEXT:    addl $8, %esp
+; NOX87-NEXT:    movzwl %cx, %ecx
+; NOX87-NEXT:    retl
+entry:
+  %0 = sitofp i64 %a to x86_fp80
+  ret x86_fp80 %0
+}
+
+define i32 @f9(x86_fp80 %a) nounwind {
+; X87-LABEL: f9:
+; X87:       # %bb.0: # %entry
+; X87-NEXT:    subl $8, %esp
+; X87-NEXT:    fldt {{[0-9]+}}(%esp)
+; X87-NEXT:    fnstcw (%esp)
+; X87-NEXT:    movzwl (%esp), %eax
+; X87-NEXT:    orl $3072, %eax # imm = 0xC00
+; X87-NEXT:    movw %ax, {{[0-9]+}}(%esp)
+; X87-NEXT:    fldcw {{[0-9]+}}(%esp)
+; X87-NEXT:    fistpl {{[0-9]+}}(%esp)
+; X87-NEXT:    fldcw (%esp)
+; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X87-NEXT:    addl $8, %esp
+; X87-NEXT:    retl
+;
+; NOX87-LABEL: f9:
+; NOX87:       # %bb.0: # %entry
+; NOX87-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; NOX87-NEXT:    pushl %eax
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    pushl {{[0-9]+}}(%esp)
+; NOX87-NEXT:    calll __fixxfsi
+; NOX87-NEXT:    addl $12, %esp
+; NOX87-NEXT:    retl
+entry:
+  %0 = fptosi x86_fp80 %a to i32
+  ret i32 %0
+}