[AArch64] FNMUL

[SjoerdMeijer]

Summary

This adds match patterns for the reassociated forms of FNMUL.

[madhur13490]

Can we please more verbose title for the patch?

llvm/test/CodeGen/AArch64/fnmul.ll

54

The test cases cover -x * y test cases. Can we have x * -y too? I believe this patch will handle those cases too. However, it is good to have a test case.

[SjoerdMeijer]

Added the tests.

I think this subject + body is an excellent description of the things here:

[AArch64] FNMUL
This adds match patterns for the reassociated forms of FNMUL.

I could merge this all into the subject, have no body, but I don't think this is all very important for this simple patch...

[dmgreen]

NoHonorSignDependentRounding is the old way of doing things - it should be based on fastmath flags nowadays. Or at least I've not heard of NoHonorSignDependentRounding before and it seems to be only used in the Arm backend at the moment.

This alive test seems to suggest that we can just always do the transform: https://alive2.llvm.org/ce/z/5-LdY1. Which I think sounds OK considering that it is a fneg. Do you know why HonorSignDependentRounding is needed? Was it just copied from Arm?

[SjoerdMeijer]

In D137925#3924452, @dmgreen wrote:

NoHonorSignDependentRounding is the old way of doing things - it should be based on fastmath flags nowadays. Or at least I've not heard of NoHonorSignDependentRounding before and it seems to be only used in the Arm backend at the moment.

This alive test seems to suggest that we can just always do the transform: https://alive2.llvm.org/ce/z/5-LdY1. Which I think sounds OK considering that it is a fneg. Do you know why HonorSignDependentRounding is needed? Was it just copied from Arm?

Thanks Dave.
Yeah, I also think we don't need NoHonorSignDependentRounding, but just added it to be consistent with ARM. The default is off, so it will do the transform, which is why I didn't mind adding it... but you're right it's probably better not to add it if it is the old way of doing things. So I will remove it from here. Let's then also remove it for ARM, but we can do that separately.

[SjoerdMeijer]

• removed NoHonorSignDependentRounding from the rules
• changed tests to run with and without fp-contract=fast, and some cases with and without fast IR instruction to show it should always trigger.

[dmgreen]

Thanks. Sounds good. LGTM

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", any_fminnum>;
 defm FMIN   : TwoOperandFPData<0b0101, "fmin", any_fminimum>;
 let SchedRW = [WriteFMul] in {
 defm FMUL   : TwoOperandFPData<0b0000, "fmul", any_fmul>;
 defm FNMUL  : TwoOperandFPDataNeg<0b1000, "fnmul", any_fmul>;
 }
 defm FSUB   : TwoOperandFPData<0b0011, "fsub", any_fsub>;
 
+// Match reassociated forms of FNMUL.
+def : Pat<(fmul (fneg FPR16:$a), (f16 FPR16:$b)),
+          (FNMULHrr FPR16:$a, FPR16:$b)>,
+          Requires<[HasFullFP16]>;
+def : Pat<(fmul (fneg FPR32:$a), (f32 FPR32:$b)),
+          (FNMULSrr FPR32:$a, FPR32:$b)>;
+def : Pat<(fmul (fneg FPR64:$a), (f64 FPR64:$b)),
+          (FNMULDrr FPR64:$a, FPR64:$b)>;
+
 def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
           (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
           (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
           (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
           (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;

llvm/test/CodeGen/AArch64/fnmul.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -fp-contract=fast -verify-machineinstrs -global-isel=0 | FileCheck %s
+;RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -verify-machineinstrs -global-isel=0 | FileCheck %s
+
+
+define half @fnmul16(half noundef %x, half noundef %y)  {
+; CHECK-LABEL: fnmul16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fnmul h0, h0, h1
+; CHECK-NEXT:    ret
+;
+entry:
+  %fneg = fneg fast half %x
+  %mul = fmul fast half %fneg, %y
+  ret half %mul
+}
+
+define float @fnmul32(float noundef %x, float noundef %y)  {
+; CHECK-LABEL: fnmul32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fnmul s0, s0, s1
+; CHECK-NEXT:    ret
+;
+entry:
+  %fneg = fneg float %x
+  %mul = fmul float %fneg, %y
+  ret float %mul
+}
+
+define double @fnmul64(double noundef %x, double noundef %y)  {
+; CHECK-LABEL: fnmul64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fnmul d0, d0, d1
+; CHECK-NEXT:    ret
+;
+entry:
+  %fneg = fneg fast double %x
+  %mul = fmul fast double %fneg, %y
+  ret double %mul
+}
+
+define half @fnmul16_2(half noundef %x, half noundef %y)  {
+; CHECK-LABEL: fnmul16_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fnmul h0, h1, h0
+; CHECK-NEXT:    ret
+;
+entry:
+  %fneg = fneg fast half %y
+  %mul = fmul fast half %x, %fneg
+  ret half %mul
+}
+
+define float @fnmul32_2(float noundef %x, float noundef %y)  {
+; CHECK-LABEL: fnmul32_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fnmul s0, s1, s0
+; CHECK-NEXT:    ret
+;
+entry:
+  %fneg = fneg fast float %y
+  %mul = fmul fast float %x, %fneg
+  ret float %mul
+}
+
+define double @fnmul64_2(double noundef %x, double noundef %y)  {
+; CHECK-LABEL: fnmul64_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fnmul d0, d1, d0
+; CHECK-NEXT:    ret
+;
+entry:
+  %fneg = fneg double %y
+  %mul = fmul double %x, %fneg
+  ret double %mul
+}