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Differential D137619

[AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions
ClosedPublic

Authored by david-arm on Nov 8 2022, 1:21 AM.

Details

Reviewers
sdesmalen
aemerson
paulwalker-arm
CarolineConcatto
kmclaughlin
efriedma
Commits
rG098e20134af5: [AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions
Summary

This patch adds the assembly/disassembly for the following instructions:

zipq1 : Interleave elements from low halves of each pair of quadword vector segments
zipq2 : Interleave elements from high halves of each pair of quadword vector segments
uzpq1 : Concatenate even elements within each pair of quadword vector segments
uzpq2 : Concatenate odd elements within each pair of quadword vector segments
tblq : Programmable table lookup within each quadword vector segment (zeroing)

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Nov 8 2022, 1:21 AM
Herald added a reviewer: efriedma. · View Herald TranscriptNov 8 2022, 1:21 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
david-arm requested review of this revision.Nov 8 2022, 1:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 8 2022, 1:21 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B196660: Diff 473915.Nov 8 2022, 2:18 AM
CarolineConcatto added inline comments.Nov 8 2022, 6:06 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9348

You could re-use class sve2_clamp
and then change:
let Inst{15-11} = 0b11000;
let Inst{10} = U;
to be:
let Inst{15-13} = 0b11;
let Inst{13-10} = op;

david-arm updated this revision to Diff 474195.Nov 9 2022, 1:45 AM
  • Reuse sve2_clamp class from SMEInstrFormats.td
david-arm marked an inline comment as done.Nov 9 2022, 1:46 AM
Harbormaster completed remote builds in B196855: Diff 474195.Nov 9 2022, 2:32 AM
paulwalker-arm added inline comments.Nov 9 2022, 2:57 AM
llvm/lib/Target/AArch64/SMEInstrFormats.td
1086

Not really against it but is there a good reason to move this code rather than adding you new sve2p1_tblq multiclass here instead?

llvm/lib/Target/AArch64/SVEInstrFormats.td
9529

I don't think this comment means anything because those bits are passed in via opc.

9542–9547

Can you reuse sve2_clamp here and pass in null_frag? I suppose this depends on whether these permute instructions are going to need floating point patterns but we can alway separate them later if that turns out to be true.

david-arm updated this revision to Diff 474236.Nov 9 2022, 5:22 AM
  • Reuse the old sve2_clamp multiclass with null_frag operators.
david-arm marked 2 inline comments as done.Nov 9 2022, 5:25 AM
david-arm added inline comments.
llvm/lib/Target/AArch64/SMEInstrFormats.td
1086

As discussed privately, this is actually moving to a different file - SVEInstrFormats.td

llvm/lib/Target/AArch64/SVEInstrFormats.td
9529

My apologies - it was a stray comment I'd left in the code by mistake!

Harbormaster completed remote builds in B196882: Diff 474236.Nov 9 2022, 6:30 AM
david-arm updated this revision to Diff 474287.Nov 9 2022, 8:38 AM
david-arm marked 2 inline comments as done.

Reverting to original patch due to difference in register constraints between SVE2.1 permute instructions and SVE2 sclamp/uclamp.

Harbormaster completed remote builds in B196916: Diff 474287.Nov 9 2022, 10:03 AM
paulwalker-arm accepted this revision.Nov 9 2022, 10:27 AM
This revision is now accepted and ready to land.Nov 9 2022, 10:27 AM
This revision was landed with ongoing or failed builds.Nov 10 2022, 1:19 AM
Closed by commit rG098e20134af5: [AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions (authored by david-arm). · Explain Why
This revision was automatically updated to reflect the committed changes.
david-arm added a commit: rG098e20134af5: [AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
10 lines
32 lines
51 lines
test/
MC/
AArch64/
SVE2p1/
14 lines
114 lines
14 lines
115 lines
14 lines
115 lines
14 lines
115 lines
14 lines
115 lines

Diff 474195

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,608 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SME or SVE2.1 instructions // SME or SVE2.1 instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasSVE2p1_or_HasSME] in { let Predicates = [HasSVE2p1_or_HasSME] in {
defm REVD_ZPmZ : sve2_int_perm_revd<"revd", AArch64revd_mt>; defm REVD_ZPmZ : sve2_int_perm_revd<"revd", AArch64revd_mt>;
defm SCLAMP_ZZZ : sve2_clamp<"sclamp", 0b0, int_aarch64_sve_sclamp>; defm SCLAMP_ZZZ : sve2_clamp<"sclamp", 0b0000, int_aarch64_sve_sclamp>;
defm UCLAMP_ZZZ : sve2_clamp<"uclamp", 0b1, int_aarch64_sve_uclamp>; defm UCLAMP_ZZZ : sve2_clamp<"uclamp", 0b0001, int_aarch64_sve_uclamp>;
defm PSEL_PPPRI : sve2_int_perm_sel_p<"psel", int_aarch64_sve_psel>; defm PSEL_PPPRI : sve2_int_perm_sel_p<"psel", int_aarch64_sve_psel>;
} // End HasSVE2p1_or_HasSME } // End HasSVE2p1_or_HasSME
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SME2 or SVE2.1 instructions // SME2 or SVE2.1 instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">; defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">;
defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">; defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">;
defm DUPQ_ZZI : sve2p1_dupq<"dupq">; defm DUPQ_ZZI : sve2p1_dupq<"dupq">;
def EXTQ_ZZI : sve2p1_extq<"extq">; def EXTQ_ZZI : sve2p1_extq<"extq">;
defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">; defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">;
defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">; defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">;
defm ZIPQ1_ZZZ : sve2p1_permute_vec_elems_q<0b1000, "zipq1">;
defm ZIPQ2_ZZZ : sve2p1_permute_vec_elems_q<0b1001, "zipq2">;
defm UZPQ1_ZZZ : sve2p1_permute_vec_elems_q<0b1010, "uzpq1">;
defm UZPQ2_ZZZ : sve2p1_permute_vec_elems_q<0b1011, "uzpq2">;
defm TBLQ_ZZZ : sve2p1_tblq<"tblq">;
} // End HasSVE2p1_or_HasSME2p1 } // End HasSVE2p1_or_HasSME2p1

llvm/lib/Target/AArch64/SMEInstrFormats.td

Show First 20 Lines • Show All 1,077 Lines • ▼ Show 20 Linesmulticlass sve2_int_perm_revd<string asm, SDPatternOperator op> {
def NAME : sve2_int_perm_revd<asm>; def NAME : sve2_int_perm_revd<asm>;
def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME)>; def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME)>;
def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME)>; def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME)>;
def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME)>; def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME)>;
def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME)>; def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME)>;
} }
class sve2_clamp<string asm, bits<2> sz, bit U, ZPRRegOp zpr_ty>
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Not really against it but is there a good reason to move this code rather than adding you new sve2p1_tblq multiclass here instead?

paulwalker-arm: Not really against it but is there a good reason to move this code rather than adding you new…
david-armAuthorUnsubmitted
Done
ReplyInline Actions

As discussed privately, this is actually moving to a different file - SVEInstrFormats.td

david-arm: As discussed privately, this is actually moving to a different file - SVEInstrFormats.td
: I<(outs zpr_ty:$Zd), (ins zpr_ty:$Zn, zpr_ty:$Zm, zpr_ty:$_Zd),
asm, "\t$Zd, $Zn, $Zm", "", []>,
Sched<[]> {
bits<5> Zm;
bits<5> Zn;
bits<5> Zd;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15-11} = 0b11000;
let Inst{10} = U;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
let DestructiveInstType = DestructiveOther;
let ElementSize = zpr_ty.ElementSize;
}
multiclass sve2_clamp<string asm, bit U, SDPatternOperator op> {
def _B : sve2_clamp<asm, 0b00, U, ZPR8>;
def _H : sve2_clamp<asm, 0b01, U, ZPR16>;
def _S : sve2_clamp<asm, 0b10, U, ZPR32>;
def _D : sve2_clamp<asm, 0b11, U, ZPR64>;
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
}
class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty> class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty>
: I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm, : I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm,
MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>, asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>,
Sched<[]> { Sched<[]> {
bits<2> Rv; bits<2> Rv;
bits<4> Pn; bits<4> Pn;
▲ Show 20 Lines • Show All 2,501 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,339 Lines • ▼ Show 20 Linesmulticlass sve_mem_128b_cld_ss<bits<2> dtype, string mnemonic, RegisterOperand gprsh_ty> {
def NAME : sve_mem_128b_cld_ss<dtype, mnemonic, gprsh_ty>; def NAME : sve_mem_128b_cld_ss<dtype, mnemonic, gprsh_ty>;
def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]", def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Rn, $Rm]",
(!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>; (!cast<Instruction>(NAME) ZPR128:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprsh_ty:$Rm), 0>;
} }
// SVE floating-point recursive reduction (quadwords) // SVE floating-point recursive reduction (quadwords)
class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic, class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic,
CarolineConcattoUnsubmitted
Done
ReplyInline Actions

You could re-use class sve2_clamp
and then change:
let Inst{15-11} = 0b11000;
let Inst{10} = U;
to be:
let Inst{15-13} = 0b11;
let Inst{13-10} = op;

CarolineConcatto: You could re-use class sve2_clamp and then change: let Inst{15-11} = 0b11000; let Inst{10} =…
RegisterOperand zpr_ty, string vec_sfx> RegisterOperand zpr_ty, string vec_sfx>
: I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn), : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn", mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
"", []>, Sched<[]> { "", []>, Sched<[]> {
bits<5> Vd; bits<5> Vd;
bits<5> Zn; bits<5> Zn;
bits<3> Pg; bits<3> Pg;
let Inst{31-24} = 0b01100100; let Inst{31-24} = 0b01100100;
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines def _D : sve2p1_pred_to_vector<{1, ?, ?, ?}, mnemonic, PPR64, VectorIndexH32b> {
bits<3> index; bits<3> index;
let Inst{22} = index{2}; let Inst{22} = index{2};
let Inst{18-17} = index{1-0}; let Inst{18-17} = index{1-0};
} }
def : InstAlias<mnemonic # "\t$Zd, $Pn", def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>; (!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
} }
class sve2_permuteq_or_clamp<string asm, bits<2> sz, bits<4> opc, ZPRRegOp zpr_ty,
RegisterOperand src1_ty>
: I<(outs zpr_ty:$Zd), (ins src1_ty:$Zn, zpr_ty:$Zm, zpr_ty:$_Zd),
asm, "\t$Zd, $Zn, $Zm", "", []>,
Sched<[]> {
bits<5> Zm;
bits<5> Zn;
bits<5> Zd;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-16} = Zm;
let Inst{15-14} = 0b11;
let Inst{13-10} = opc;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
let DestructiveInstType = DestructiveOther;
let ElementSize = zpr_ty.ElementSize;
}
multiclass sve2_clamp<string asm, bits<4> opc, SDPatternOperator op> {
// bits 13-11 = 0
paulwalker-armUnsubmitted
Done
ReplyInline Actions

I don't think this comment means anything because those bits are passed in via opc.

paulwalker-arm: I don't think this comment means anything because those bits are passed in via `opc`.
david-armAuthorUnsubmitted
Done
ReplyInline Actions

My apologies - it was a stray comment I'd left in the code by mistake!

david-arm: My apologies - it was a stray comment I'd left in the code by mistake!
def _B : sve2_permuteq_or_clamp<asm, 0b00, opc, ZPR8, ZPR8>;
def _H : sve2_permuteq_or_clamp<asm, 0b01, opc, ZPR16, ZPR16>;
def _S : sve2_permuteq_or_clamp<asm, 0b10, opc, ZPR32, ZPR32>;
def _D : sve2_permuteq_or_clamp<asm, 0b11, opc, ZPR64, ZPR64>;
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
}
multiclass sve2p1_permute_vec_elems_q<bits<4> opc, string mnemonic> {
def _B : sve2_permuteq_or_clamp<mnemonic, 0b00, opc, ZPR8, ZPR8>;
def _H : sve2_permuteq_or_clamp<mnemonic, 0b01, opc, ZPR16, ZPR16>;
def _S : sve2_permuteq_or_clamp<mnemonic, 0b10, opc, ZPR32, ZPR32>;
def _D : sve2_permuteq_or_clamp<mnemonic, 0b11, opc, ZPR64, ZPR64>;
}
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Can you reuse sve2_clamp here and pass in null_frag? I suppose this depends on whether these permute instructions are going to need floating point patterns but we can alway separate them later if that turns out to be true.

paulwalker-arm: Can you reuse `sve2_clamp` here and pass in `null_frag`? I suppose this depends on whether…
multiclass sve2p1_tblq<string mnemonic> {
def _B : sve2_permuteq_or_clamp<mnemonic, 0b00, 0b1110, ZPR8, Z_b>;
def _H : sve2_permuteq_or_clamp<mnemonic, 0b01, 0b1110, ZPR16, Z_h>;
def _S : sve2_permuteq_or_clamp<mnemonic, 0b10, 0b1110, ZPR32, Z_s>;
def _D : sve2_permuteq_or_clamp<mnemonic, 0b11, 0b1110, ZPR64, Z_d>;
}

llvm/test/MC/AArch64/SVE2p1/tblq-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector suffix
tblq z0.b, {z0.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: tblq z0.b, {z0.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
tblq z23.d, {z23.s}, z13.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: tblq z23.d, {z23.s}, z13.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/tblq.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
tblq z0.h, {z0.h}, z0.h // 01000100-01000000-11111000-00000000
// CHECK-INST: tblq z0.h, { z0.h }, z0.h
// CHECK-ENCODING: [0x00,0xf8,0x40,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4440f800 <unknown>
tblq z21.h, {z10.h}, z21.h // 01000100-01010101-11111001-01010101
// CHECK-INST: tblq z21.h, { z10.h }, z21.h
// CHECK-ENCODING: [0x55,0xf9,0x55,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4455f955 <unknown>
tblq z23.h, {z13.h}, z8.h // 01000100-01001000-11111001-10110111
// CHECK-INST: tblq z23.h, { z13.h }, z8.h
// CHECK-ENCODING: [0xb7,0xf9,0x48,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4448f9b7 <unknown>
tblq z31.h, {z31.h}, z31.h // 01000100-01011111-11111011-11111111
// CHECK-INST: tblq z31.h, { z31.h }, z31.h
// CHECK-ENCODING: [0xff,0xfb,0x5f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 445ffbff <unknown>
tblq z0.s, {z0.s}, z0.s // 01000100-10000000-11111000-00000000
// CHECK-INST: tblq z0.s, { z0.s }, z0.s
// CHECK-ENCODING: [0x00,0xf8,0x80,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4480f800 <unknown>
tblq z21.s, {z10.s}, z21.s // 01000100-10010101-11111001-01010101
// CHECK-INST: tblq z21.s, { z10.s }, z21.s
// CHECK-ENCODING: [0x55,0xf9,0x95,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4495f955 <unknown>
tblq z23.s, {z13.s}, z8.s // 01000100-10001000-11111001-10110111
// CHECK-INST: tblq z23.s, { z13.s }, z8.s
// CHECK-ENCODING: [0xb7,0xf9,0x88,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4488f9b7 <unknown>
tblq z31.s, {z31.s}, z31.s // 01000100-10011111-11111011-11111111
// CHECK-INST: tblq z31.s, { z31.s }, z31.s
// CHECK-ENCODING: [0xff,0xfb,0x9f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 449ffbff <unknown>
tblq z0.d, {z0.d}, z0.d // 01000100-11000000-11111000-00000000
// CHECK-INST: tblq z0.d, { z0.d }, z0.d
// CHECK-ENCODING: [0x00,0xf8,0xc0,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c0f800 <unknown>
tblq z21.d, {z10.d}, z21.d // 01000100-11010101-11111001-01010101
// CHECK-INST: tblq z21.d, { z10.d }, z21.d
// CHECK-ENCODING: [0x55,0xf9,0xd5,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44d5f955 <unknown>
tblq z23.d, {z13.d}, z8.d // 01000100-11001000-11111001-10110111
// CHECK-INST: tblq z23.d, { z13.d }, z8.d
// CHECK-ENCODING: [0xb7,0xf9,0xc8,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c8f9b7 <unknown>
tblq z31.d, {z31.d}, z31.d // 01000100-11011111-11111011-11111111
// CHECK-INST: tblq z31.d, { z31.d }, z31.d
// CHECK-ENCODING: [0xff,0xfb,0xdf,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44dffbff <unknown>
tblq z0.b, {z0.b}, z0.b // 01000100-00000000-11111000-00000000
// CHECK-INST: tblq z0.b, { z0.b }, z0.b
// CHECK-ENCODING: [0x00,0xf8,0x00,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4400f800 <unknown>
tblq z21.b, {z10.b}, z21.b // 01000100-00010101-11111001-01010101
// CHECK-INST: tblq z21.b, { z10.b }, z21.b
// CHECK-ENCODING: [0x55,0xf9,0x15,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4415f955 <unknown>
tblq z23.b, {z13.b}, z8.b // 01000100-00001000-11111001-10110111
// CHECK-INST: tblq z23.b, { z13.b }, z8.b
// CHECK-ENCODING: [0xb7,0xf9,0x08,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4408f9b7 <unknown>
tblq z31.b, {z31.b}, z31.b // 01000100-00011111-11111011-11111111
// CHECK-INST: tblq z31.b, { z31.b }, z31.b
// CHECK-ENCODING: [0xff,0xfb,0x1f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 441ffbff <unknown>

llvm/test/MC/AArch64/SVE2p1/uzpq1-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid register suffixes
uzpq1 z0.h, z0.h, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uzpq1 z0.h, z0.h, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uzpq1 z0.d, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uzpq1 z0.d, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/uzpq1.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uzpq1 z0.h, z0.h, z0.h // 01000100-01000000-11101000-00000000
// CHECK-INST: uzpq1 z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0xe8,0x40,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4440e800 <unknown>
uzpq1 z21.h, z10.h, z21.h // 01000100-01010101-11101001-01010101
// CHECK-INST: uzpq1 z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0xe9,0x55,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4455e955 <unknown>
uzpq1 z23.h, z13.h, z8.h // 01000100-01001000-11101001-10110111
// CHECK-INST: uzpq1 z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xe9,0x48,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4448e9b7 <unknown>
uzpq1 z31.h, z31.h, z31.h // 01000100-01011111-11101011-11111111
// CHECK-INST: uzpq1 z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0xeb,0x5f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 445febff <unknown>
uzpq1 z0.s, z0.s, z0.s // 01000100-10000000-11101000-00000000
// CHECK-INST: uzpq1 z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0xe8,0x80,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4480e800 <unknown>
uzpq1 z21.s, z10.s, z21.s // 01000100-10010101-11101001-01010101
// CHECK-INST: uzpq1 z21.s, z10.s, z21.s
// CHECK-ENCODING: [0x55,0xe9,0x95,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4495e955 <unknown>
uzpq1 z23.s, z13.s, z8.s // 01000100-10001000-11101001-10110111
// CHECK-INST: uzpq1 z23.s, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0xe9,0x88,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4488e9b7 <unknown>
uzpq1 z31.s, z31.s, z31.s // 01000100-10011111-11101011-11111111
// CHECK-INST: uzpq1 z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0xeb,0x9f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 449febff <unknown>
uzpq1 z0.d, z0.d, z0.d // 01000100-11000000-11101000-00000000
// CHECK-INST: uzpq1 z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0xe8,0xc0,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c0e800 <unknown>
uzpq1 z21.d, z10.d, z21.d // 01000100-11010101-11101001-01010101
// CHECK-INST: uzpq1 z21.d, z10.d, z21.d
// CHECK-ENCODING: [0x55,0xe9,0xd5,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44d5e955 <unknown>
uzpq1 z23.d, z13.d, z8.d // 01000100-11001000-11101001-10110111
// CHECK-INST: uzpq1 z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0xe9,0xc8,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c8e9b7 <unknown>
uzpq1 z31.d, z31.d, z31.d // 01000100-11011111-11101011-11111111
// CHECK-INST: uzpq1 z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0xeb,0xdf,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44dfebff <unknown>
uzpq1 z0.b, z0.b, z0.b // 01000100-00000000-11101000-00000000
// CHECK-INST: uzpq1 z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe8,0x00,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4400e800 <unknown>
uzpq1 z21.b, z10.b, z21.b // 01000100-00010101-11101001-01010101
// CHECK-INST: uzpq1 z21.b, z10.b, z21.b
// CHECK-ENCODING: [0x55,0xe9,0x15,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4415e955 <unknown>
uzpq1 z23.b, z13.b, z8.b // 01000100-00001000-11101001-10110111
// CHECK-INST: uzpq1 z23.b, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0xe9,0x08,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4408e9b7 <unknown>
uzpq1 z31.b, z31.b, z31.b // 01000100-00011111-11101011-11111111
// CHECK-INST: uzpq1 z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0xeb,0x1f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 441febff <unknown>

llvm/test/MC/AArch64/SVE2p1/uzpq2-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid register suffixes
uzpq2 z0.h, z0.h, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uzpq2 z0.h, z0.h, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uzpq2 z0.d, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uzpq2 z0.d, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/uzpq2.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uzpq2 z0.h, z0.h, z0.h // 01000100-01000000-11101100-00000000
// CHECK-INST: uzpq2 z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0xec,0x40,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4440ec00 <unknown>
uzpq2 z21.h, z10.h, z21.h // 01000100-01010101-11101101-01010101
// CHECK-INST: uzpq2 z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0xed,0x55,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4455ed55 <unknown>
uzpq2 z23.h, z13.h, z8.h // 01000100-01001000-11101101-10110111
// CHECK-INST: uzpq2 z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xed,0x48,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4448edb7 <unknown>
uzpq2 z31.h, z31.h, z31.h // 01000100-01011111-11101111-11111111
// CHECK-INST: uzpq2 z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0xef,0x5f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 445fefff <unknown>
uzpq2 z0.s, z0.s, z0.s // 01000100-10000000-11101100-00000000
// CHECK-INST: uzpq2 z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0xec,0x80,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4480ec00 <unknown>
uzpq2 z21.s, z10.s, z21.s // 01000100-10010101-11101101-01010101
// CHECK-INST: uzpq2 z21.s, z10.s, z21.s
// CHECK-ENCODING: [0x55,0xed,0x95,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4495ed55 <unknown>
uzpq2 z23.s, z13.s, z8.s // 01000100-10001000-11101101-10110111
// CHECK-INST: uzpq2 z23.s, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0xed,0x88,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4488edb7 <unknown>
uzpq2 z31.s, z31.s, z31.s // 01000100-10011111-11101111-11111111
// CHECK-INST: uzpq2 z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0xef,0x9f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 449fefff <unknown>
uzpq2 z0.d, z0.d, z0.d // 01000100-11000000-11101100-00000000
// CHECK-INST: uzpq2 z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0xec,0xc0,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c0ec00 <unknown>
uzpq2 z21.d, z10.d, z21.d // 01000100-11010101-11101101-01010101
// CHECK-INST: uzpq2 z21.d, z10.d, z21.d
// CHECK-ENCODING: [0x55,0xed,0xd5,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44d5ed55 <unknown>
uzpq2 z23.d, z13.d, z8.d // 01000100-11001000-11101101-10110111
// CHECK-INST: uzpq2 z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0xed,0xc8,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c8edb7 <unknown>
uzpq2 z31.d, z31.d, z31.d // 01000100-11011111-11101111-11111111
// CHECK-INST: uzpq2 z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0xef,0xdf,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44dfefff <unknown>
uzpq2 z0.b, z0.b, z0.b // 01000100-00000000-11101100-00000000
// CHECK-INST: uzpq2 z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0xec,0x00,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4400ec00 <unknown>
uzpq2 z21.b, z10.b, z21.b // 01000100-00010101-11101101-01010101
// CHECK-INST: uzpq2 z21.b, z10.b, z21.b
// CHECK-ENCODING: [0x55,0xed,0x15,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4415ed55 <unknown>
uzpq2 z23.b, z13.b, z8.b // 01000100-00001000-11101101-10110111
// CHECK-INST: uzpq2 z23.b, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0xed,0x08,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4408edb7 <unknown>
uzpq2 z31.b, z31.b, z31.b // 01000100-00011111-11101111-11111111
// CHECK-INST: uzpq2 z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0xef,0x1f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 441fefff <unknown>

llvm/test/MC/AArch64/SVE2p1/zipq1-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid register suffixes
zipq1 z0.h, z0.h, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: zipq1 z0.h, z0.h, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
zipq1 z0.d, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: zipq1 z0.d, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/zipq1.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
zipq1 z0.h, z0.h, z0.h // 01000100-01000000-11100000-00000000
// CHECK-INST: zipq1 z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0xe0,0x40,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4440e000 <unknown>
zipq1 z21.h, z10.h, z21.h // 01000100-01010101-11100001-01010101
// CHECK-INST: zipq1 z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0xe1,0x55,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4455e155 <unknown>
zipq1 z23.h, z13.h, z8.h // 01000100-01001000-11100001-10110111
// CHECK-INST: zipq1 z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xe1,0x48,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4448e1b7 <unknown>
zipq1 z31.h, z31.h, z31.h // 01000100-01011111-11100011-11111111
// CHECK-INST: zipq1 z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0xe3,0x5f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 445fe3ff <unknown>
zipq1 z0.s, z0.s, z0.s // 01000100-10000000-11100000-00000000
// CHECK-INST: zipq1 z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0xe0,0x80,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4480e000 <unknown>
zipq1 z21.s, z10.s, z21.s // 01000100-10010101-11100001-01010101
// CHECK-INST: zipq1 z21.s, z10.s, z21.s
// CHECK-ENCODING: [0x55,0xe1,0x95,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4495e155 <unknown>
zipq1 z23.s, z13.s, z8.s // 01000100-10001000-11100001-10110111
// CHECK-INST: zipq1 z23.s, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0xe1,0x88,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4488e1b7 <unknown>
zipq1 z31.s, z31.s, z31.s // 01000100-10011111-11100011-11111111
// CHECK-INST: zipq1 z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0xe3,0x9f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 449fe3ff <unknown>
zipq1 z0.d, z0.d, z0.d // 01000100-11000000-11100000-00000000
// CHECK-INST: zipq1 z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0xe0,0xc0,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c0e000 <unknown>
zipq1 z21.d, z10.d, z21.d // 01000100-11010101-11100001-01010101
// CHECK-INST: zipq1 z21.d, z10.d, z21.d
// CHECK-ENCODING: [0x55,0xe1,0xd5,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44d5e155 <unknown>
zipq1 z23.d, z13.d, z8.d // 01000100-11001000-11100001-10110111
// CHECK-INST: zipq1 z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0xe1,0xc8,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c8e1b7 <unknown>
zipq1 z31.d, z31.d, z31.d // 01000100-11011111-11100011-11111111
// CHECK-INST: zipq1 z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0xe3,0xdf,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44dfe3ff <unknown>
zipq1 z0.b, z0.b, z0.b // 01000100-00000000-11100000-00000000
// CHECK-INST: zipq1 z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe0,0x00,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4400e000 <unknown>
zipq1 z21.b, z10.b, z21.b // 01000100-00010101-11100001-01010101
// CHECK-INST: zipq1 z21.b, z10.b, z21.b
// CHECK-ENCODING: [0x55,0xe1,0x15,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4415e155 <unknown>
zipq1 z23.b, z13.b, z8.b // 01000100-00001000-11100001-10110111
// CHECK-INST: zipq1 z23.b, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0xe1,0x08,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4408e1b7 <unknown>
zipq1 z31.b, z31.b, z31.b // 01000100-00011111-11100011-11111111
// CHECK-INST: zipq1 z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0xe3,0x1f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 441fe3ff <unknown>

llvm/test/MC/AArch64/SVE2p1/zipq2-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid register suffixes
zipq2 z0.h, z0.h, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: zipq2 z0.h, z0.h, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
zipq2 z0.d, z0.s, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: zipq2 z0.d, z0.s, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/zipq2.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
zipq2 z0.h, z0.h, z0.h // 01000100-01000000-11100100-00000000
// CHECK-INST: zipq2 z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0xe4,0x40,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4440e400 <unknown>
zipq2 z21.h, z10.h, z21.h // 01000100-01010101-11100101-01010101
// CHECK-INST: zipq2 z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0xe5,0x55,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4455e555 <unknown>
zipq2 z23.h, z13.h, z8.h // 01000100-01001000-11100101-10110111
// CHECK-INST: zipq2 z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xe5,0x48,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4448e5b7 <unknown>
zipq2 z31.h, z31.h, z31.h // 01000100-01011111-11100111-11111111
// CHECK-INST: zipq2 z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0xe7,0x5f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 445fe7ff <unknown>
zipq2 z0.s, z0.s, z0.s // 01000100-10000000-11100100-00000000
// CHECK-INST: zipq2 z0.s, z0.s, z0.s
// CHECK-ENCODING: [0x00,0xe4,0x80,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4480e400 <unknown>
zipq2 z21.s, z10.s, z21.s // 01000100-10010101-11100101-01010101
// CHECK-INST: zipq2 z21.s, z10.s, z21.s
// CHECK-ENCODING: [0x55,0xe5,0x95,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4495e555 <unknown>
zipq2 z23.s, z13.s, z8.s // 01000100-10001000-11100101-10110111
// CHECK-INST: zipq2 z23.s, z13.s, z8.s
// CHECK-ENCODING: [0xb7,0xe5,0x88,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4488e5b7 <unknown>
zipq2 z31.s, z31.s, z31.s // 01000100-10011111-11100111-11111111
// CHECK-INST: zipq2 z31.s, z31.s, z31.s
// CHECK-ENCODING: [0xff,0xe7,0x9f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 449fe7ff <unknown>
zipq2 z0.d, z0.d, z0.d // 01000100-11000000-11100100-00000000
// CHECK-INST: zipq2 z0.d, z0.d, z0.d
// CHECK-ENCODING: [0x00,0xe4,0xc0,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c0e400 <unknown>
zipq2 z21.d, z10.d, z21.d // 01000100-11010101-11100101-01010101
// CHECK-INST: zipq2 z21.d, z10.d, z21.d
// CHECK-ENCODING: [0x55,0xe5,0xd5,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44d5e555 <unknown>
zipq2 z23.d, z13.d, z8.d // 01000100-11001000-11100101-10110111
// CHECK-INST: zipq2 z23.d, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0xe5,0xc8,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44c8e5b7 <unknown>
zipq2 z31.d, z31.d, z31.d // 01000100-11011111-11100111-11111111
// CHECK-INST: zipq2 z31.d, z31.d, z31.d
// CHECK-ENCODING: [0xff,0xe7,0xdf,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 44dfe7ff <unknown>
zipq2 z0.b, z0.b, z0.b // 01000100-00000000-11100100-00000000
// CHECK-INST: zipq2 z0.b, z0.b, z0.b
// CHECK-ENCODING: [0x00,0xe4,0x00,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4400e400 <unknown>
zipq2 z21.b, z10.b, z21.b // 01000100-00010101-11100101-01010101
// CHECK-INST: zipq2 z21.b, z10.b, z21.b
// CHECK-ENCODING: [0x55,0xe5,0x15,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4415e555 <unknown>
zipq2 z23.b, z13.b, z8.b // 01000100-00001000-11100101-10110111
// CHECK-INST: zipq2 z23.b, z13.b, z8.b
// CHECK-ENCODING: [0xb7,0xe5,0x08,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 4408e5b7 <unknown>
zipq2 z31.b, z31.b, z31.b // 01000100-00011111-11100111-11111111
// CHECK-INST: zipq2 z31.b, z31.b, z31.b
// CHECK-ENCODING: [0xff,0xe7,0x1f,0x44]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 441fe7ff <unknown>