[AArch64][SVE] Rename PPR3b register class to PPR_p0to7

[david-arm]

Summary

In order to be consistent with the naming scheme introduced
by D136678 for the register class PPR_p8to15, I've also
created this patch to rename PPR3b to PPR_p0to7.

[paulwalker-arm]

I won't go as far as saying I'm against this patch given there is logic behind the change but I will highlight the existing idiom of specifying the bit length to restrict the range of another operand is pretty common. For example, we have ZPR_3b, ZPR_4b and the immediates are defined in this way. My comment on D136678 was more about not needing to duplicate information for something that wasn't purely about restricting the upper bound. However, the change is sensible and more expressive so if you feel strongly enough then fair enough.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case 'y':
       break;
     }
   } else {
     PredicateConstraint PC = parsePredicateConstraint(Constraint);
     if (PC != PredicateConstraint::Invalid) {
       if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
         return std::make_pair(0U, nullptr);
       bool restricted = (PC == PredicateConstraint::Upl);
-      return restricted ? std::make_pair(0U, &AArch64::PPR_3bRegClass)
+      return restricted ? std::make_pair(0U, &AArch64::PPR_p0to7RegClass)
                         : std::make_pair(0U, &AArch64::PPRRegClass);
     }
   }
   if (StringRef("{cc}").equals_insensitive(Constraint))
     return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
 
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 class PPRClass<int lastreg> : RegisterClass<
                                   "AArch64",
                                   [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1 ], 16,
                                   (sequence "P%u", 0, lastreg)> {
   let Size = 16;
 }
 
 def PPR    : PPRClass<15>;
-def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
+def PPR_p0to7 : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
 
 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
   let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"
                             # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
   let DiagnosticType = "InvalidSVE" # name # "Reg";
   let RenderMethod = "addRegOperands";
   let ParserMethod = "tryParseSVEPredicateVector";
 }
 
 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR",  0>;
 def PPRAsmOp8   : PPRAsmOperand<"PredicateB",   "PPR",  8>;
 def PPRAsmOp16  : PPRAsmOperand<"PredicateH",   "PPR", 16>;
 def PPRAsmOp32  : PPRAsmOperand<"PredicateS",   "PPR", 32>;
 def PPRAsmOp64  : PPRAsmOperand<"PredicateD",   "PPR", 64>;
 
 def PPRAny : PPRRegOp<"",  PPRAsmOpAny, ElementSizeNone, PPR>;
 def PPR8   : PPRRegOp<"b", PPRAsmOp8,   ElementSizeB,  PPR>;
 def PPR16  : PPRRegOp<"h", PPRAsmOp16,  ElementSizeH,  PPR>;
 def PPR32  : PPRRegOp<"s", PPRAsmOp32,  ElementSizeS,  PPR>;
 def PPR64  : PPRRegOp<"d", PPRAsmOp64,  ElementSizeD,  PPR>;
 
-def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b",  0>;
+def PPRAsmOpAny_p0to7 : PPRAsmOperand<"PredicateAny_p0to7", "PPR_p0to7",  0>;
 
-def PPR3bAny : PPRRegOp<"",  PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;
+def PPRAny_p0to7 : PPRRegOp<"", PPRAsmOpAny_p0to7, ElementSizeNone, PPR_p0to7>;
 
 //******************************************************************************
 
 // SVE vector register classes
 class ZPRClass<int lastreg> : RegisterClass<"AArch64",
                                             [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
                                              nxv2f16, nxv4f16, nxv8f16,
                                              nxv2bf16, nxv4bf16, nxv8bf16,

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVEorSME] in {
   def PRFB_PRR : sve_mem_prfm_ss<0b001, "prfb", GPR64NoXZRshifted8>;
   def PRFH_PRR : sve_mem_prfm_ss<0b011, "prfh", GPR64NoXZRshifted16>;
   def PRFW_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>;
   def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>;
 
   multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instruction RegImmInst, Instruction RegRegInst, ComplexPattern AddrCP> {
     // reg + imm
     let AddedComplexity = 2 in {
-      def _reg_imm : Pat<(prefetch (PredTy PPR_3b:$gp), (am_sve_indexed_s6 GPR64sp:$base, simm6s1:$offset), (i32 sve_prfop:$prfop)),
-                         (RegImmInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, simm6s1:$offset)>;
+      def _reg_imm : Pat<(prefetch (PredTy PPR_p0to7:$gp), (am_sve_indexed_s6 GPR64sp:$base, simm6s1:$offset), (i32 sve_prfop:$prfop)),
+                         (RegImmInst sve_prfop:$prfop, PPR_p0to7:$gp, GPR64:$base, simm6s1:$offset)>;
     }
 
     // reg + reg
     let AddedComplexity = 1 in {
-      def _reg_reg : Pat<(prefetch (PredTy PPR_3b:$gp), (AddrCP GPR64sp:$base, GPR64:$index), (i32 sve_prfop:$prfop)),
-                         (RegRegInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, GPR64:$index)>;
+      def _reg_reg : Pat<(prefetch (PredTy PPR_p0to7:$gp), (AddrCP GPR64sp:$base, GPR64:$index), (i32 sve_prfop:$prfop)),
+                         (RegRegInst sve_prfop:$prfop, PPR_p0to7:$gp, GPR64:$base, GPR64:$index)>;
     }
 
     // default fallback
-    def _default : Pat<(prefetch  (PredTy PPR_3b:$gp), GPR64:$base, (i32 sve_prfop:$prfop)),
-                       (RegImmInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, (i64 0))>;
+    def _default : Pat<(prefetch  (PredTy PPR_p0to7:$gp), GPR64:$base, (i32 sve_prfop:$prfop)),
+                       (RegImmInst sve_prfop:$prfop, PPR_p0to7:$gp, GPR64:$base, (i64 0))>;
   }
 
   defm : sve_prefetch<int_aarch64_sve_prf, nxv16i1, PRFB_PRI, PRFB_PRR, am_sve_regreg_lsl0>;
   defm : sve_prefetch<int_aarch64_sve_prf, nxv8i1,  PRFH_PRI, PRFH_PRR, am_sve_regreg_lsl1>;
   defm : sve_prefetch<int_aarch64_sve_prf, nxv4i1,  PRFW_PRI, PRFW_PRR, am_sve_regreg_lsl2>;
   defm : sve_prefetch<int_aarch64_sve_prf, nxv2i1,  PRFD_PRI, PRFD_PRR, am_sve_regreg_lsl3>;
 } // End HasSVEorSME
 
let Predicates = [HasSVEorSME] in {
 
   def : InstAlias<"not $Pd, $Pg/z, $Pn",
                   (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
 
   def : InstAlias<"nots $Pd, $Pg/z, $Pn",
                   (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
 
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPGE_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPGE_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPGE_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPGE_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPHI_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPHI_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPHI_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPHI_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPHS_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPHS_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPHS_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPHS_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPGT_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPGT_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPGT_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPGT_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FACGE_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FACGE_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FACGE_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FACGT_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FACGT_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FACGT_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FCMGE_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FCMGE_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FCMGE_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FCMGT_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FCMGT_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FCMGT_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   // Pseudo instructions representing unpredicated LDR and STR for ZPR2,3,4.
   // These get expanded to individual LDR_ZXI/STR_ZXI instructions in
   // AArch64ExpandPseudoInsts.
   let mayLoad = 1, hasSideEffects = 0 in {
     def LDR_ZZXI   : Pseudo<(outs   ZZ_b:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
     def LDR_ZZZXI  : Pseudo<(outs  ZZZ_b:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
     def LDR_ZZZZXI : Pseudo<(outs ZZZZ_b:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

template <unsigned Class> bool isSVEVectorReg() const {
     RegKind RK;
     switch (Class) {
     case AArch64::ZPRRegClassID:
     case AArch64::ZPR_3bRegClassID:
     case AArch64::ZPR_4bRegClassID:
       RK = RegKind::SVEDataVector;
       break;
     case AArch64::PPRRegClassID:
-    case AArch64::PPR_3bRegClassID:
+    case AArch64::PPR_p0to7RegClassID:
       RK = RegKind::SVEPredicateVector;
       break;
     default:
       llvm_unreachable("Unsupport register class");
     }
 
     return (Kind == k_Register && Reg.Kind == RK) &&
            AArch64MCRegisterClasses[Class].contains(getReg());
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidSVEPattern:
     return Error(Loc, "invalid predicate pattern");
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPredicateBReg:
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
     return Error(Loc, "invalid predicate register.");
-  case Match_InvalidSVEPredicate3bAnyReg:
+  case Match_InvalidSVEPredicateAny_p0to7Reg:
     return Error(Loc, "invalid restricted predicate register, expected p0..p7 (without element suffix)");
   case Match_InvalidSVEExactFPImmOperandHalfOne:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 2.0.");
   case Match_InvalidSVEExactFPImmOperandZeroOne:
     return Error(Loc, "Invalid floating point constant, expected 0.0 or 1.0.");
   case Match_InvalidMatrixTileVectorH8:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidZPR_4b32:
   case Match_InvalidZPR_4b64:
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPattern:
   case Match_InvalidSVEPredicateBReg:
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
-  case Match_InvalidSVEPredicate3bAnyReg:
+  case Match_InvalidSVEPredicateAny_p0to7Reg:
   case Match_InvalidSVEExactFPImmOperandHalfOne:
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
   case Match_InvalidSVEExactFPImmOperandZeroOne:
   case Match_InvalidMatrixTile32:
   case Match_InvalidMatrixTile64:
   case Match_InvalidMatrix:
   case Match_InvalidMatrix32:
   case Match_InvalidMatrix64:

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
                                      const MCDisassembler *Decoder);
 static DecodeStatus
 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
                                   uint64_t Address,
                                   const MCDisassembler *Decoder);
 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder);
-static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
+static DecodeStatus DecodePPR_p0to7RegisterClass(MCInst &Inst, unsigned RegNo,
                                                  uint64_t Address,
                                                  const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
                                                const MCDisassembler *Decoder);
 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
if (RegNo > 15)
     return Fail;
 
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
-static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
-                                              uint64_t Addr,
-                                              const MCDisassembler *Decoder) {
+static DecodeStatus
+DecodePPR_p0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
   if (RegNo > 7)
     return Fail;
 
   // Just reuse the PPR decode table
   return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
 }
 
 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,

llvm/lib/Target/AArch64/SMEInstrFormats.td

 
 def am_sme_indexed_b4 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<0,15>", [], [SDNPWantRoot]>;
 
 //===----------------------------------------------------------------------===//
 // SME Outer Products
 //===----------------------------------------------------------------------===//
 
 class sme_outer_product_pseudo<ZPRRegOp zpr_ty>
-    : Pseudo<(outs), (ins i64imm:$tile, PPR3bAny:$pn, PPR3bAny:$pm,
+    : Pseudo<(outs), (ins i64imm:$tile, PPRAny_p0to7:$pn, PPRAny_p0to7:$pm,
                           zpr_ty:$zn, zpr_ty:$zm), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
 }
 
 class sme_fp_outer_product_inst<bit S, bit sz, MatrixTileOperand za_ty,
                                 ZPRRegOp zpr_ty, string mnemonic>
     : I<(outs za_ty:$ZAda),
-      (ins za_ty:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
+      (ins za_ty:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn, $Zm",
         "", []>,
       Sched<[]> {
   bits<5> Zm;
   bits<3> Pm;
   bits<3> Pn;
   bits<5> Zn;
   let Inst{31-23} = 0b100000001;
multiclass sme_outer_product_fp32<bit S, string mnemonic, SDPatternOperator op> {
   def NAME : sme_fp_outer_product_inst<S, 0b0, TileOp32, ZPR32, mnemonic> {
     bits<2> ZAda;
     let Inst{1-0} = ZAda;
     let Inst{2}   = 0b0;
   }
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR32>;
 
-  def : Pat<(op imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv4i1 PPRAny_p0to7:$pn), (nxv4i1 PPRAny_p0to7:$pm),
                 (nxv4f32 ZPR32:$zn), (nxv4f32 ZPR32:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 multiclass sme_outer_product_fp64<bit S, string mnemonic, SDPatternOperator op> {
   def NAME : sme_fp_outer_product_inst<S, 0b1, TileOp64, ZPR64, mnemonic> {
     bits<3> ZAda;
     let Inst{2-0} = ZAda;
   }
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR64>;
 
-  def : Pat<(op imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_7:$tile, (nxv2i1 PPRAny_p0to7:$pn), (nxv2i1 PPRAny_p0to7:$pm),
                 (nxv2f64 ZPR64:$zn), (nxv2f64 ZPR64:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 class sme_int_outer_product_inst<bit u0, bit u1, bit S, bit sz,
                                  MatrixTileOperand za_ty, ZPRRegOp zpr_ty,
                                  string mnemonic>
     : I<(outs za_ty:$ZAda),
-        (ins za_ty:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
+        (ins za_ty:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn, $Zm",
         "", []>,
       Sched<[]> {
   bits<5> Zm;
   bits<3> Pm;
   bits<3> Pn;
   bits<5> Zn;
   let Inst{31-25} = 0b1010000;
def NAME : sme_int_outer_product_inst<opc{2}, opc{1}, opc{0}, 0b0, TileOp32,
                                         ZPR8, mnemonic> {
     bits<2> ZAda;
     let Inst{1-0} = ZAda;
     let Inst{2}   = 0b0;
   }
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR8>;
 
-  def : Pat<(op imm0_3:$tile, (nxv16i1 PPR3bAny:$pn), (nxv16i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv16i1 PPRAny_p0to7:$pn), (nxv16i1 PPRAny_p0to7:$pm),
                 (nxv16i8 ZPR8:$zn), (nxv16i8 ZPR8:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 multiclass sme_int_outer_product_i64<bits<3> opc, string mnemonic,
                                      SDPatternOperator op> {
   def NAME : sme_int_outer_product_inst<opc{2}, opc{1}, opc{0}, 0b1, TileOp64,
                                         ZPR16, mnemonic> {
     bits<3> ZAda;
     let Inst{2-0} = ZAda;
   }
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
 
-  def : Pat<(op imm0_7:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_7:$tile, (nxv8i1 PPRAny_p0to7:$pn), (nxv8i1 PPRAny_p0to7:$pm),
                 (nxv8i16 ZPR16:$zn), (nxv8i16 ZPR16:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 class sme_outer_product_widening_inst<bit op, bit S, string mnemonic>
     : I<(outs TileOp32:$ZAda),
-        (ins  TileOp32:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, ZPR16:$Zn, ZPR16:$Zm),
+        (ins  TileOp32:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, ZPR16:$Zn, ZPR16:$Zm),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn, $Zm",
         "", []>,
       Sched<[]> {
   bits<5> Zm;
   bits<3> Pm;
   bits<3> Pn;
   bits<5> Zn;
   bits<2> ZAda;
class sme_outer_product_widening_inst<bit op, bit S, string mnemonic>
   let Constraints = "$ZAda = $_ZAda";
 }
 
 multiclass sme_bf16_outer_product<bit S, string mnemonic, SDPatternOperator op> {
   def NAME : sme_outer_product_widening_inst<0b0, S, mnemonic>;
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
 
-  def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv8i1 PPRAny_p0to7:$pn), (nxv8i1 PPRAny_p0to7:$pm),
                 (nxv8bf16 ZPR16:$zn), (nxv8bf16 ZPR16:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 multiclass sme_f16_outer_product<bit S, string mnemonic, SDPatternOperator op> {
   def NAME : sme_outer_product_widening_inst<0b1, S, mnemonic>;
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
 
-  def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv8i1 PPRAny_p0to7:$pn), (nxv8i1 PPRAny_p0to7:$pm),
                 (nxv8f16 ZPR16:$zn), (nxv8f16 ZPR16:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SME Add Vector to Tile
 //===----------------------------------------------------------------------===//
 
 class sme_add_vector_to_tile_inst<bit op, bit V, MatrixTileOperand tile_ty,
                                   ZPRRegOp zpr_ty, string mnemonic>
     : I<(outs tile_ty:$ZAda),
-        (ins tile_ty:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn),
+        (ins tile_ty:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn",
         "", []>, Sched<[]> {
   bits<3> Pm;
   bits<3> Pn;
   bits<5> Zn;
   let Inst{31-23} = 0b110000001;
   let Inst{22}    = op;
   let Inst{21-17} = 0b01000;

 class sme_add_vector_to_tile_u64<bit V, string mnemonic>
     : sme_add_vector_to_tile_inst<0b1, V, TileOp64, ZPR64, mnemonic> {
   bits<3> ZAda;
   let Inst{2-0} = ZAda;
 }
 
 class sme_add_vector_to_tile_pseudo<ZPRRegOp zpr_ty>
     : Pseudo<(outs),
-             (ins i64imm:$tile, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn), []>,
+             (ins i64imm:$tile, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
 }
 
 def ADDHA_MPPZ_PSEUDO_S : sme_add_vector_to_tile_pseudo<ZPR32>;
 def ADDVA_MPPZ_PSEUDO_S : sme_add_vector_to_tile_pseudo<ZPR32>;
 
 def : Pat<(int_aarch64_sme_addha
-            imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
+            imm0_3:$tile, (nxv4i1 PPRAny_p0to7:$pn), (nxv4i1 PPRAny_p0to7:$pm),
             (nxv4i32 ZPR32:$zn)),
           (ADDHA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
 def : Pat<(int_aarch64_sme_addva
-            imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
+            imm0_3:$tile, (nxv4i1 PPRAny_p0to7:$pn), (nxv4i1 PPRAny_p0to7:$pm),
             (nxv4i32 ZPR32:$zn)),
           (ADDVA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
 
 let Predicates = [HasSMEI16I64] in {
 def ADDHA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
 def ADDVA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
 
 def : Pat<(int_aarch64_sme_addha
-            imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
+            imm0_7:$tile, (nxv2i1 PPRAny_p0to7:$pn), (nxv2i1 PPRAny_p0to7:$pm),
             (nxv2i64 ZPR64:$zn)),
           (ADDHA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
 def : Pat<(int_aarch64_sme_addva
-            imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
+            imm0_7:$tile, (nxv2i1 PPRAny_p0to7:$pn), (nxv2i1 PPRAny_p0to7:$pm),
             (nxv2i64 ZPR64:$zn)),
           (ADDVA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SME Contiguous Loads
 //===----------------------------------------------------------------------===//
 
class sme_mem_ld_ss_base<bit Q, bit V, bits<2> msz, dag outs, dag ins,
   let mayLoad = 1;
 }
 
 class sme_mem_ld_ss_inst<bit Q, bits<2> msz, string mnemonic,
                          MatrixTileVectorOperand tile_ty, bit is_col,
                          Operand imm_ty, RegisterOperand gpr_ty>
     : sme_mem_ld_ss_base<
         Q, is_col, msz, (outs tile_ty:$ZAt),
-        (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn,
+        (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn,
              gpr_ty:$Rm),
         mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
 
 multiclass sme_mem_ss_aliases_base<string mnemonic, Instruction inst,
                                    MatrixTileVectorOperand tile_ty,
                                    Operand imm_ty, RegisterOperand gpr_ty,
                                    string pg_suffix=""> {
   def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
-                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
   // Default XZR offset aliases
   def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv, $imm]\\}, $Pg" # pg_suffix # ", [$Rn]",
-                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 1>;
   def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn]",
-                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 0>;
 }
 
 multiclass sme_mem_ss_aliases<string mnemonic, string inst, bit is_col,
                               string pg_suffix=""> {
   defm : sme_mem_ss_aliases_base<mnemonic # "b", !cast<Instruction>(inst # _B),
                                  !if(is_col, TileVectorOpV8, TileVectorOpH8),
                                  sme_elm_idx0_15, GPR64shifted8, pg_suffix>;
   defm : sme_mem_ss_aliases_base<mnemonic # "h", !cast<Instruction>(inst # _H),
multiclass sme_mem_ld_ss_aliases<string inst, bit is_col> {
   defm NAME : sme_mem_ss_aliases<"ld1", inst, is_col, "/z">;
 }
 
 multiclass sme_mem_ld_ss_patterns<Instruction Inst, SDPatternOperator Load,
                                   Operand tile_ty, Operand offset_ty,
                                   ComplexPattern addr,
                                   ComplexPattern tileslice> {
   // base, tileslice
-  def : Pat<(Load PPR3bAny:$pg, GPR64sp:$base, tile_ty:$tile,
+  def : Pat<(Load PPRAny_p0to7:$pg, GPR64sp:$base, tile_ty:$tile,
                   (i32 (tileslice MatrixIndexGPR32Op12_15:$idx, offset_ty:$imm))),
             (Inst tile_ty:$tile, $idx, $imm, $pg, $base, XZR)>;
 
   // reg + reg, tileslice
   let AddedComplexity = 1 in {
-    def : Pat<(Load PPR3bAny:$pg, (addr GPR64sp:$base, GPR64:$offset),
+    def : Pat<(Load PPRAny_p0to7:$pg, (addr GPR64sp:$base, GPR64:$offset),
                     tile_ty:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
                                               offset_ty:$imm))),
               (Inst tile_ty:$tile, $idx, $imm, $pg, $base, $offset)>;
   }
 }
 
 class sme_load_pseudo
     : Pseudo<(outs), (ins i64imm:$tile, MatrixIndexGPR32Op12_15:$idx,
-                          i64imm:$imm, PPR3bAny:$pg, GPR64sp:$base, GPR64:$offset), []>,
+                          i64imm:$imm, PPRAny_p0to7:$pg, GPR64sp:$base, GPR64:$offset), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
   let mayLoad = 1;
 }
 
 multiclass sme_mem_ld_v_ss<string mnemonic, bit is_col> {
   def _B : sme_mem_ld_ss_inst<0b0, 0b00, mnemonic # "b",
class sme_mem_st_ss_base<bit Q, bit V, bits<2> msz, dag ins,
   let hasSideEffects = 1;
 }
 
 class sme_mem_st_ss_inst<bit Q, bits<2> msz, string mnemonic,
                          MatrixTileVectorOperand tile_ty, bit is_col,
                          Operand imm_ty, RegisterOperand gpr_ty>
     : sme_mem_st_ss_base<
         Q, is_col, msz,
-        (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg,
+        (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg,
              GPR64sp:$Rn, gpr_ty:$Rm),
         mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
 
 multiclass sme_mem_st_ss_aliases<string inst, bit is_col> {
   defm NAME : sme_mem_ss_aliases<"st1", inst, is_col>;
 }
 
 multiclass sme_mem_st_ss_patterns<Instruction Inst, SDPatternOperator Store,
                                   Operand offset_ty,
                                   ComplexPattern imm2tile,
                                   ComplexPattern addr,
                                   ComplexPattern tileslice> {
   // base, tileslice
-  def : Pat<(Store PPR3bAny:$pg, GPR64sp:$base, (imm2tile untyped:$tile),
+  def : Pat<(Store PPRAny_p0to7:$pg, GPR64sp:$base, (imm2tile untyped:$tile),
                    (i32 (tileslice MatrixIndexGPR32Op12_15:$idx, offset_ty:$imm))),
             (Inst $tile, $idx, $imm, $pg, $base, XZR)>;
 
   // reg + reg, tileslice
   let AddedComplexity = 1 in {
-    def : Pat<(Store PPR3bAny:$pg, (addr GPR64sp:$base, GPR64:$offset),
+    def : Pat<(Store PPRAny_p0to7:$pg, (addr GPR64sp:$base, GPR64:$offset),
                      (imm2tile untyped:$tile),
                      (i32 (tileslice MatrixIndexGPR32Op12_15:$idx, offset_ty:$imm))),
               (Inst $tile, $idx, $imm, $pg, $base, $offset)>;
   }
 }
 
 multiclass sme_mem_st_v_ss<string mnemonic, bit is_col> {
   def _B : sme_mem_st_ss_inst<0b0, 0b00, mnemonic # "b",
class sme_vector_to_tile_base<bit Q, bit V, bits<2> sz, dag outs, dag ins,
   let Inst{9-5}   = Zn;
   let Inst{4}     = 0b0;
 }
 
 class sme_vector_to_tile_inst<bit Q, bits<2> sz, MatrixTileVectorOperand tile_ty,
                               bit is_col, Operand imm_ty, ZPRRegOp zpr_ty,
                               string mnemonic>
     : sme_vector_to_tile_base<Q, is_col, sz, (outs tile_ty:$ZAd),
-        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, zpr_ty:$Zn),
+        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, zpr_ty:$Zn),
         mnemonic, "\t$ZAd[$Rv, $imm], $Pg/m, $Zn">{
 
   let Constraints = "$ZAd = $_ZAd";
 }
 
 
 multiclass sme_vector_to_tile_aliases<Instruction inst,
                                       MatrixTileVectorOperand tile_ty,
                                       ZPRRegOp zpr_ty, Operand imm_ty> {
   def : InstAlias<"mov\t$ZAd[$Rv, $imm], $Pg/m, $Zn",
-                  (inst tile_ty:$ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, zpr_ty:$Zn), 1>;
+                  (inst tile_ty:$ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, zpr_ty:$Zn), 1>;
 }
 
 multiclass sme_vector_to_tile_patterns<Instruction inst, ValueType zpr_vt,
                                        ValueType ppr_vt, Operand imm_ty,
                                        Operand offset_ty,
                                        SDPatternOperator op,
                                        ComplexPattern tileslice> {
   def : Pat<(op imm_ty:$tile, MatrixIndexGPR32Op12_15:$idx,
-                (ppr_vt PPR3bAny:$pg), (zpr_vt ZPRAny:$zn)),
+                (ppr_vt PPRAny_p0to7:$pg), (zpr_vt ZPRAny:$zn)),
             (inst imm_ty:$tile, $idx, 0, $pg, $zn)>;
   let AddedComplexity = 1 in {
     def : Pat<(op imm_ty:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
                                                 offset_ty:$imm)),
-                  (ppr_vt PPR3bAny:$pg), (zpr_vt ZPRAny:$zn)),
+                  (ppr_vt PPRAny_p0to7:$pg), (zpr_vt ZPRAny:$zn)),
               (inst imm_ty:$tile, $idx, $imm, $pg, $zn)>;
   }
 }
 
 class sme_mova_insert_pseudo
     : Pseudo<(outs), (ins i64imm:$tile, MatrixIndexGPR32Op12_15:$idx,
-                          i64imm:$imm, PPR3bAny:$pg, ZPRAny:$zn), []>,
+                          i64imm:$imm, PPRAny_p0to7:$pg, ZPRAny:$zn), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
 }
 
 multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> {
   def _B : sme_vector_to_tile_inst<0b0, 0b00, !if(is_col, TileVectorOpV8,
                                                           TileVectorOpH8),
class sme_tile_to_vector_base<bit Q, bit V, bits<2> sz, dag outs, dag ins,
   let Inst{9}     = 0b0;
   let Inst{4-0}   = Zd;
 }
 
 class sme_tile_to_vector_inst<bit Q, bits<2> sz, ZPRRegOp zpr_ty,
                               MatrixTileVectorOperand tile_ty,
                               bit is_col, Operand imm_ty, string mnemonic>
     : sme_tile_to_vector_base<Q, is_col, sz, (outs zpr_ty:$Zd),
-        (ins zpr_ty:$_Zd, PPR3bAny:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
+        (ins zpr_ty:$_Zd, PPRAny_p0to7:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
         mnemonic, "\t$Zd, $Pg/m, $ZAn[$Rv, $imm]"> {
 
   let Constraints = "$Zd = $_Zd";
 }
 
 multiclass sme_tile_to_vector_aliases<Instruction inst, ZPRRegOp zpr_ty,
                                       MatrixTileVectorOperand tile_ty,
                                       Operand imm_ty > {
   def : InstAlias<"mov\t$Zd, $Pg/m, $ZAn[$Rv, $imm]",
-                  (inst zpr_ty:$Zd, PPR3bAny:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), 1>;
+                  (inst zpr_ty:$Zd, PPRAny_p0to7:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), 1>;
 }
 
 multiclass sme_tile_to_vector_patterns<Instruction inst, ValueType zpr_vt,
                                        ValueType ppr_vt, Operand offset_ty,
                                        ComplexPattern imm2tile,
                                        ComplexPattern tileslice,
                                        SDPatternOperator op> {
-  def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPR3bAny:$pg),
+  def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPRAny_p0to7:$pg),
                         (imm2tile untyped:$tile), MatrixIndexGPR32Op12_15:$idx)),
             (inst $passthru, $pg, $tile, $idx, 0)>;
   let AddedComplexity = 1 in {
-    def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPR3bAny:$pg),
+    def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPRAny_p0to7:$pg),
                           (imm2tile untyped:$tile),
                           (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
                                           offset_ty:$imm)))),
               (inst $passthru, $pg, $tile, $idx, $imm)>;
   }
 }
 
 multiclass sme_tile_to_vector_v<string mnemonic, bit is_col> {
def : Pat<(int_aarch64_sme_zero imm:$imm),
             (!cast<Instruction>(NAME # _PSEUDO) imm:$imm)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE2 Instructions
 //===----------------------------------------------------------------------===//
 
 class sve2_int_perm_revd<string asm>
-    : I<(outs ZPR128:$Zd), (ins ZPR128:$_Zd, PPR3bAny:$Pg, ZPR128:$Zn),
+    : I<(outs ZPR128:$Zd), (ins ZPR128:$_Zd, PPRAny_p0to7:$Pg, ZPR128:$Zn),
         asm, "\t$Zd, $Pg/m, $Zn", "", []>,
       Sched<[]> {
   bits<5> Zd;
   bits<3> Pg;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = 0b00; // size
   let Inst{21-13} = 0b101110100;

llvm/lib/Target/AArch64/SVEInstrFormats.td

class SVE_Shift_DupImm_All_Active_Pat<ValueType vt, SDPatternOperator op,
                                       ComplexPattern cast, Instruction inst>
 : Pat<(vt (op (pt (SVEAllActive)), vt:$Rn, (vt (splat_vector (it (cast i32:$imm)))))),
       (inst $Rn, i32:$imm)>;
 
 class SVE_2_Op_Fp_Imm_Pat<ValueType vt, SDPatternOperator op,
                           ValueType pt, ValueType it,
                           FPImmLeaf immL, int imm,
                           Instruction inst>
-: Pat<(vt (op (pt PPR_3b:$Pg), (vt ZPR:$Zs1), (vt (splat_vector (it immL))))),
+: Pat<(vt (op (pt PPR_p0to7:$Pg), (vt ZPR:$Zs1), (vt (splat_vector (it immL))))),
       (inst $Pg, $Zs1, imm)>;
 
 class SVE_2_Op_Fp_Imm_Pat_Zero<ValueType vt, SDPatternOperator op,
                               ValueType pt, ValueType it,
                               FPImmLeaf immL, int imm,
                               Instruction inst>
 : Pat<(vt (op pt:$Pg, (vselect pt:$Pg, vt:$Zs1, (SVEDup0)),
                       (vt (splat_vector (it immL))))),

 
 //
 // Pseudos for destructive operands
 //
 let hasNoSchedulingInfo = 1 in {
   class PredTwoOpPseudo<string name, ZPRRegOp zprty,
                         FalseLanesEnum flags = FalseLanesNone>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
+    Pseudo<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
     let FalseLanes = flags;
   }
 
   class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
                            FalseLanesEnum flags = FalseLanesNone>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
+    Pseudo<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zs1, immty:$imm), []> {
     let FalseLanes = flags;
   }
 
   class PredThreeOpPseudo<string name, ZPRRegOp zprty,
                           FalseLanesEnum flags = FalseLanesNone>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
+    Pseudo<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
     let FalseLanes = flags;
   }
 }
 
 //
 // Pseudos for passthru operands
 //
 let hasNoSchedulingInfo = 1 in {
   class PredOneOpPassthruPseudo<string name, ZPRRegOp zprty>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPR3bAny:$Pg, zprty:$Zs), []>;
+    Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPRAny_p0to7:$Pg, zprty:$Zs), []>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Predicate Misc Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_pfalse<bits<6> opc, string asm>
 : I<(outs PPR8:$Pd), (ins),

 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Arithmetic - Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm,
                          ZPRRegOp zprty,
                          Operand imm_ty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, imm_ty:$i1),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $i1",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bit i1;
   let Inst{31-24} = 0b01100101;
   let Inst{23-22} = sz;
multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, string Ps, Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator op> {
   def : SVE_2_Op_Fp_Imm_Pat<nxv4f32, op, nxv4i1, f32, A, 0, !cast<Instruction>(NAME # "_S")>;
   def : SVE_2_Op_Fp_Imm_Pat<nxv4f32, op, nxv4i1, f32, B, 1, !cast<Instruction>(NAME # "_S")>;
   def : SVE_2_Op_Fp_Imm_Pat<nxv2f64, op, nxv2i1, f64, A, 0, !cast<Instruction>(NAME # "_D")>;
   def : SVE_2_Op_Fp_Imm_Pat<nxv2f64, op, nxv2i1, f64, B, 1, !cast<Instruction>(NAME # "_D")>;
 }
 
 class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
                        ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<5> Zm;
   let Inst{31-24} = 0b01100101;
   let Inst{23-22} = sz;
multiclass sve_fp_3op_u_zd_ftsmul<bits<3> opc, string asm, SDPatternOperator op> {
   def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Fused Multiply-Add Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
+: I<(outs zprty:$Zda), (ins PPRAny_p0to7:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zda, $Pg/m, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zda;
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-24} = 0b01100101;
multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm, string Ps,
 
   def : SVE_4_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
   def : SVE_4_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
   def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm,
                          ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
   asm, "\t$Zdn, $Pg/m, $Zm, $Za",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Za;
   bits<5> Zdn;
   bits<5> Zm;
   let Inst{31-24} = 0b01100101;
def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, (i32 VectorIndexD32b_timm:$idx))),
             (!cast<Instruction>(NAME # _D) $Op1, $Op2, VectorIndexD32b_timm:$idx)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Complex Multiply-Add Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
+: I<(outs zprty:$Zda), (ins PPRAny_p0to7:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
                         complexrotateop:$imm),
   asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
   "", []>, Sched<[]> {
   bits<5> Zda;
   bits<3> Pg;
   bits<5> Zn;
   bits<5> Zm;
   bits<2> imm;
def : Pat<(nxv4f32 (op nxv4f32:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, (i32 VectorIndexD32b_timm:$idx), (i32 complexrotateop:$imm))),
             (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, VectorIndexD32b_timm:$idx, complexrotateop:$imm)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Complex Addition Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm,
                         complexrotateopodd:$imm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
   "",
   []>, Sched<[]> {
   bits<5> Zdn;
   bits<5> Zm;
   bits<3> Pg;
   bit imm;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE2 Floating Point Convert Group
 //===----------------------------------------------------------------------===//
 
 class sve2_fp_convert_precision<bits<4> opc, string asm,
                                 ZPRRegOp zprty1, ZPRRegOp zprty2>
-: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
+: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPRAny_p0to7:$Pg, zprty2:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
   bits<5> Zd;
   bits<5> Zn;
   bits<3> Pg;
   let Inst{31-24} = 0b01100100;
   let Inst{23-22} = opc{3-2};

 }
 
 //===----------------------------------------------------------------------===//
 // SVE2 Floating Point Pairwise Group
 //===----------------------------------------------------------------------===//
 
 class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
                             ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zm;
   bits<5> Zdn;
   let Inst{31-24} = 0b01100100;
   let Inst{23-22} = sz;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Unary Operations Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
                       RegisterOperand o_zprtype, ElementSizeEnum Sz>
-: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
+: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPRAny_p0to7:$Pg, i_zprtype:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zd;
   bits<5> Zn;
   let Inst{31-24} = 0b01100101;
   let Inst{23-22} = opc{6-5};

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Arithmetic - Binary Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
                                 string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<5> Zm;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = sz8_64;
   let Inst{21}    = 0b0;
   let Inst{20-19} = fmt;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Multiply-Add Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
                                 ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
   asm, "\t$Zdn, $Pg/m, $Zm, $Za",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<5> Za;
   bits<5> Zm;
   let Inst{31-24} = 0b00000100;
multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm, SDPatternOperator op> {
   def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
   def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
   def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
   def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
                             ZPRRegOp zprty>
-: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
+: I<(outs zprty:$Zda), (ins PPRAny_p0to7:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zda, $Pg/m, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zda;
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-24} = 0b00000100;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE2 Integer - Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
                           ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zm;
   bits<5> Zdn;
   let Inst{31-24} = 0b01000100;
   let Inst{23-22} = sz;
   let Inst{21-20} = 0b01;
   let Inst{20-16} = opc{5-1};
multiclass sve2_int_arith_pred<bits<6> opc, string asm, SDPatternOperator op,
   def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
   def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1,  nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
   def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1,  nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1,  nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve2_int_sadd_long_accum_pairwise<bits<2> sz, bit U, string asm,
                                         ZPRRegOp zprty1, ZPRRegOp zprty2>
-: I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn),
+: I<(outs zprty1:$Zda), (ins PPRAny_p0to7:$Pg, zprty1:$_Zda, zprty2:$Zn),
   asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
   bits<5> Zda;
   let Inst{31-24} = 0b01000100;
   let Inst{23-22} = sz;
   let Inst{21-17} = 0b00010;
   let Inst{16}    = U;
multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm, SDPatternOperator op> {
 
   def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv16i8, !cast<Instruction>(NAME # _H)>;
   def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv8i16, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv4i32, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
                             string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zd;
   bits<5> Zn;
   let Inst{31-24} = 0b01000100;
   let Inst{23-22} = sz;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Arithmetic - Unary Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
                              string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zd;
   bits<5> Zn;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = sz8_64;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Compare - Vectors Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
                   PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty1:$Zn, zprty2:$Zm),
   asm, "\t$Pd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<4> Pd;
   bits<3> Pg;
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-24} = 0b00100100;

 
 //===----------------------------------------------------------------------===//
 // SVE Integer Compare - Signed Immediate Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty,
                       Operand immtype>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, immtype:$imm5),
   asm, "\t$Pd, $Pg/z, $Zn, $imm5",
   "",
   []>, Sched<[]> {
   bits<4> Pd;
   bits<3> Pg;
   bits<5> Zn;
   bits<5> imm5;
   let Inst{31-24} = 0b00100101;
: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, immtype:$imm5),
   let Defs = [NZCV];
   let ElementSize = pprty.ElementSize;
   let isPTestLike = 1;
 }
 
 multiclass SVE_SETCC_Imm_Pat<CondCode cc, CondCode commuted_cc,
                              ValueType predvt, ValueType intvt,
                              Operand immtype, Instruction cmp> {
-  def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
+  def : Pat<(predvt (AArch64setcc_z (predvt PPR_p0to7:$Pg),
                                     (intvt ZPR:$Zs1),
                                     (intvt (splat_vector (immtype:$imm))),
                                     cc)),
             (cmp $Pg, $Zs1, immtype:$imm)>;
-  def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
+  def : Pat<(predvt (AArch64setcc_z (predvt PPR_p0to7:$Pg),
                                     (intvt (splat_vector (immtype:$imm))),
                                     (intvt ZPR:$Zs1),
                                     commuted_cc)),
             (cmp $Pg, $Zs1, immtype:$imm)>;
   def : Pat<(predvt (and predvt:$Pg,
                          (AArch64setcc_z (predvt (AArch64ptrue 31)),
                                          (intvt ZPR:$Zs1),
                                          (intvt (splat_vector (immtype:$imm))),

 
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Compare - Unsigned Immediate Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty, Operand immtype>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, immtype:$imm7),
   asm, "\t$Pd, $Pg/z, $Zn, $imm7",
   "",
   []>, Sched<[]> {
   bits<4> Pd;
   bits<3> Pg;
   bits<5> Zn;
   bits<7> imm7;
   let Inst{31-24} = 0b00100100;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Fast Reduction Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm,
                       ZPRRegOp zprty, FPRasZPROperand dstOpType>
-: I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs dstOpType:$Vd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Vd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
   bits<5> Zn;
   bits<5> Vd;
   bits<3> Pg;
   let Inst{31-24} = 0b01100101;
   let Inst{23-22} = sz;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Accumulating Reduction Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm,
                       ZPRRegOp zprty, FPRasZPROperand dstOpType>
-: I<(outs dstOpType:$Vdn), (ins PPR3bAny:$Pg, dstOpType:$_Vdn, zprty:$Zm),
+: I<(outs dstOpType:$Vdn), (ins PPRAny_p0to7:$Pg, dstOpType:$_Vdn, zprty:$Zm),
   asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
   "",
   []>,
   Sched<[]> {
   bits<3> Pg;
   bits<5> Vdn;
   bits<5> Zm;
   let Inst{31-24} = 0b01100101;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Compare - Vectors Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, zprty:$Zm),
   asm, "\t$Pd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<4> Pd;
   bits<3> Pg;
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-24} = 0b01100101;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Floating Point Compare - with Zero Group
 //===----------------------------------------------------------------------===//
 
 class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Pd, $Pg/z, $Zn, #0.0",
   "",
   []>, Sched<[]> {
   bits<4> Pd;
   bits<3> Pg;
   bits<5> Zn;
   let Inst{31-24} = 0b01100101;
   let Inst{23-22} = sz;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Bitwise Shift - Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
                                  ZPRRegOp zprty, Operand immtype>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, immtype:$imm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<6> imm;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = tsz8_64{3-2};
multiclass sve_int_bin_pred_shift_imm_right_zeroing_bhsd<SDPatternOperator op = null_frag> {
   def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv16i8, op, nxv16i1, nxv16i8, tvecshiftR8, !cast<Pseudo>(NAME # _ZERO_B)>;
   def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv8i16, op, nxv8i1, nxv8i16, tvecshiftR16, !cast<Pseudo>(NAME # _ZERO_H)>;
   def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv4i32, op, nxv4i1, nxv4i32, tvecshiftR32, !cast<Pseudo>(NAME # _ZERO_S)>;
   def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv2i64, op, nxv2i1, nxv2i64, tvecshiftR64, !cast<Pseudo>(NAME # _ZERO_D)>;
 }
 
 class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
                              string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty2:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<5> Zm;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = sz8_64;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Memory - Store Group
 //===----------------------------------------------------------------------===//
 
 class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
                      RegisterOperand VecList>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zt;
   bits<4> imm4;
   let Inst{31-25} = 0b1110010;

 }
 
 multiclass sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
                           RegisterOperand listty, ZPRRegOp zprty>
 {
   def NAME : sve_mem_cst_si<msz, esz, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, Operand immtype>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm4),
   asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zt;
   bits<4> imm4;
   let Inst{31-25} = 0b1110010;
: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm4),
   let mayStore = 1;
 }
 
 multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                           string asm, Operand immtype> {
   def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, RegisterOperand gprty>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rm;
   bits<5> Rn;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;
   let Inst{24-23} = sz;
   let Inst{22-21} = nregs;
   let Inst{20-16} = Rm;
   let Inst{15-13} = 0b011;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayStore = 1;
 }
 
 class sve_mem_cst_ss_base<bits<4> dtype, string asm,
                           RegisterOperand listty, RegisterOperand gprty>
-: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rm;
   bits<5> Rn;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;
   let Inst{24-21} = dtype;
   let Inst{20-16} = Rm;
   let Inst{15-13} = 0b010;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayStore = 1;
 }
 
 multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
                           RegisterOperand listty, ZPRRegOp zprty,
                           RegisterOperand gprty> {
   def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zt;
   bits<4> imm4;
   let Inst{31-25} = 0b1110010;
   let Inst{24-23} = msz;
   let Inst{22-20} = 0b001;
   let Inst{19-16} = imm4;
   let Inst{15-13} = 0b111;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayStore = 1;
 }
 
 multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty,
                             ZPRRegOp zprty> {
   def NAME : sve_mem_cstnt_si<msz, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty,
                             RegisterOperand gprty>
-: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rm;
   bits<5> Rn;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;
   let Inst{24-23} = msz;
   let Inst{22-21} = 0b00;
   let Inst{20-16} = Rm;
   let Inst{15-13} = 0b011;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayStore = 1;
 }
 
 multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
                             ZPRRegOp zprty, RegisterOperand gprty> {
   def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve2_mem_sstnt_vs_base<bits<3> opc, string asm,
                              RegisterOperand listty, ZPRRegOp zprty>
-: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
+: I<(outs), (ins listty:$Zt, PPRAny_p0to7:$Pg, zprty:$Zn, GPR64:$Rm),
   asm, "\t$Zt, $Pg, [$Zn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rm;
   bits<5> Zn;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;

 }
 
 multiclass sve2_mem_sstnt_vs_32_ptrs<bits<3> opc, string asm,
                              SDPatternOperator op,
                              ValueType vt> {
   def _REAL : sve2_mem_sstnt_vs_base<opc, asm, Z_s, ZPR32>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 1>;
 
-  def : Pat <(op (nxv4i32 ZPR32:$Zt), (nxv4i1 PPR3bAny:$Pg), (nxv4i32 ZPR32:$Zn), (i64 GPR64:$Rm), vt),
-             (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm)>;
+  def : Pat <(op (nxv4i32 ZPR32:$Zt), (nxv4i1 PPRAny_p0to7:$Pg), (nxv4i32 ZPR32:$Zn), (i64 GPR64:$Rm), vt),
+             (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm)>;
 }
 
 multiclass sve2_mem_sstnt_vs_64_ptrs<bits<3> opc, string asm,
                              SDPatternOperator op,
                              ValueType vt> {
   def _REAL : sve2_mem_sstnt_vs_base<opc, asm, Z_d, ZPR64>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 1>;
 
-  def : Pat <(op (nxv2i64 ZPR64:$Zt), (nxv2i1 PPR3bAny:$Pg), (nxv2i64 ZPR64:$Zn), (i64 GPR64:$Rm), vt),
-             (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm)>;
+  def : Pat <(op (nxv2i64 ZPR64:$Zt), (nxv2i1 PPRAny_p0to7:$Pg), (nxv2i64 ZPR64:$Zn), (i64 GPR64:$Rm), vt),
+             (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm)>;
 }
 
 class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
                      RegisterOperand VecList, RegisterOperand zprext>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;
multiclass sve_mem_32b_sst_sv_32_scaled<bits<3> opc, string asm,
                                     SDPatternOperator uxtw_op,
                                     RegisterOperand sxtw_opnd,
                                     RegisterOperand uxtw_opnd,
                                     ValueType vt > {
   def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, Z_s, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, Z_s, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
   def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 multiclass sve_mem_64b_sst_sv_32_scaled<bits<3> opc, string asm,
                                     SDPatternOperator sxtw_op,
                                     SDPatternOperator uxtw_op,
                                     RegisterOperand sxtw_opnd,
                                     RegisterOperand uxtw_opnd,
                                     ValueType vt > {
   def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, Z_d, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, Z_d, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
   def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 multiclass sve_mem_64b_sst_sv_32_unscaled<bits<3> opc, string asm,
                                          SDPatternOperator sxtw_op,
                                          SDPatternOperator uxtw_op,
                                          RegisterOperand sxtw_opnd,
                                          RegisterOperand uxtw_opnd,
                                          ValueType vt> {
   def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, Z_d, uxtw_opnd>;
   def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, Z_d, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
   def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _SXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 multiclass sve_mem_32b_sst_sv_32_unscaled<bits<3> opc, string asm,
                                           SDPatternOperator sxtw_op,
                                           SDPatternOperator uxtw_op,
                                           RegisterOperand sxtw_opnd,
                                           RegisterOperand uxtw_opnd,
                                           ValueType vt> {
   def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, Z_s, uxtw_opnd>;
   def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, Z_s, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
   def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _SXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm,
                       RegisterOperand zprext>
-: I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;

 
 multiclass sve_mem_sst_sv_64_scaled<bits<2> msz, string asm,
                                     SDPatternOperator op,
                                     RegisterOperand zprext,
                                     ValueType vt> {
   def _SCALED : sve_mem_sst_sv2<msz, 1, asm, zprext>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SCALED) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt),
             (!cast<Instruction>(NAME # _SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
 }
 
 multiclass sve_mem_sst_sv_64_unscaled<bits<2> msz, string asm,
                                       SDPatternOperator op,
                                       ValueType vt> {
   def NAME : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
+                 (!cast<Instruction>(NAME) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty,
                      RegisterOperand VecList, Operand imm_ty>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, zprty:$Zn, imm_ty:$imm5),
   asm, "\t$Zt, $Pg, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> imm5;
   bits<5> Zn;
   bits<5> Zt;
   let Inst{31-25} = 0b1110010;

 
 multiclass sve_mem_32b_sst_vi_ptrs<bits<3> opc, string asm,
                                    Operand imm_ty,
                                    SDPatternOperator op,
                                    ValueType vt> {
   def _IMM : sve_mem_sst_vi<opc, asm, ZPR32, Z_s, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 1>;
 
   def : Pat<(op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt),
             (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
 }
 
 multiclass sve_mem_64b_sst_vi_ptrs<bits<3> opc, string asm,
                                    Operand imm_ty,
                                    SDPatternOperator op,
                                    ValueType vt> {
   def _IMM : sve_mem_sst_vi<opc, asm, ZPR64, Z_d, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 1>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
             (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
 }
 
 class sve_mem_z_spill<string asm>
 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
   asm, "\t$Zt, [$Rn, $imm9, mul vl]",

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Permute Vector - Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm,
                             ZPRRegOp zprty, RegisterClass rt>
-: I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm),
+: I<(outs rt:$Rdn), (ins PPRAny_p0to7:$Pg, rt:$_Rdn, zprty:$Zm),
   asm, "\t$Rdn, $Pg, $_Rdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rdn;
   bits<5> Zm;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
multiclass sve_int_perm_clast_rz<bit ab, string asm, SDPatternOperator op> {
   def : SVE_3_Op_Pat<i32, op, nxv16i1, i32, nxv16i8, !cast<Instruction>(NAME # _B)>;
   def : SVE_3_Op_Pat<i32, op, nxv8i1,  i32, nxv8i16, !cast<Instruction>(NAME # _H)>;
   def : SVE_3_Op_Pat<i32, op, nxv4i1,  i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<i64, op, nxv2i1,  i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm,
                             ZPRRegOp zprty, RegisterClass rt>
-: I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm),
+: I<(outs rt:$Vdn), (ins PPRAny_p0to7:$Pg, rt:$_Vdn, zprty:$Zm),
   asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Vdn;
   bits<5> Zm;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
multiclass sve_int_perm_clast_vz<bit ab, string asm, SDPatternOperator op> {
   def : SVE_3_Op_Pat<f32, op, nxv4i1, f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<f64, op, nxv2i1, f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
 
   def : SVE_3_Op_Pat<bf16, op, nxv8i1, bf16, nxv8bf16, !cast<Instruction>(NAME # _H)>;
 }
 
 class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm,
                             ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<5> Zm;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
multiclass sve_int_perm_clast_zz<bit ab, string asm, SDPatternOperator op> {
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
 
   def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME # _H)>;
 }
 
 class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm,
                           ZPRRegOp zprty, RegisterClass resultRegType>
-: I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs resultRegType:$Rd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Rd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rd;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
multiclass sve_int_perm_last_r<bit ab, string asm, SDPatternOperator op> {
   def : SVE_2_Op_Pat<i32, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
   def : SVE_2_Op_Pat<i32, op, nxv8i1,  nxv8i16, !cast<Instruction>(NAME # _H)>;
   def : SVE_2_Op_Pat<i32, op, nxv4i1,  nxv4i32, !cast<Instruction>(NAME # _S)>;
   def : SVE_2_Op_Pat<i64, op, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm,
                           ZPRRegOp zprty, RegisterClass dstRegtype>
-: I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs dstRegtype:$Vd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Vd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Vd;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
multiclass sve_int_perm_last_v<bit ab, string asm, SDPatternOperator op> {
   def : SVE_2_Op_Pat<f32, op, nxv4i1,  nxv4f32, !cast<Instruction>(NAME # _S)>;
   def : SVE_2_Op_Pat<f32, op, nxv2i1,  nxv2f32, !cast<Instruction>(NAME # _S)>;
   def : SVE_2_Op_Pat<f64, op, nxv2i1,  nxv2f64, !cast<Instruction>(NAME # _D)>;
 
   def : SVE_2_Op_Pat<bf16, op, nxv8i1,  nxv8bf16, !cast<Instruction>(NAME # _H)>;
 }
 
 class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
   bits<5> Zm;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
multiclass sve_int_perm_splice<string asm, SDPatternOperator op> {
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1,  nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1,  nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
 
   def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME # _H)>;
 }
 
 class sve2_int_perm_splice_cons<bits<2> sz8_64, string asm,
                                ZPRRegOp zprty, RegisterOperand VecList>
-: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn),
+: I<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, VecList:$Zn),
   asm, "\t$Zd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
   bits<5> Zd;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
   let Inst{21-13} = 0b101101100;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zd;
 }
 
 multiclass sve2_int_perm_splice_cons<string asm> {
   def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8,  ZZ_b>;
   def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>;
   def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>;
   def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>;
 }
 
 class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm,
                        ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
   bits<5> Zd;
   bits<3> Pg;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;

 multiclass sve_int_perm_rev_revw<string asm, SDPatternOperator op> {
   def _D : sve_int_perm_rev<0b11, 0b10, asm, ZPR64>;
 
   def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
                          RegisterClass srcRegType>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, srcRegType:$Rn),
   asm, "\t$Zd, $Pg/m, $Rn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zd;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;

 
 multiclass sve_int_perm_cpy_r<string asm, SDPatternOperator op> {
   def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>;
   def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>;
   def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>;
   def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
 
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny_p0to7:$Pg, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny_p0to7:$Pg, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny_p0to7:$Pg, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny_p0to7:$Pg, GPR64sp:$Rn), 1>;
 
   def : Pat<(nxv16i8 (op nxv16i1:$pg, i32:$splat, nxv16i8:$passthru)),
             (!cast<Instruction>(NAME # _B) $passthru, $pg, $splat)>;
   def : Pat<(nxv8i16 (op nxv8i1:$pg, i32:$splat, nxv8i16:$passthru)),
             (!cast<Instruction>(NAME # _H) $passthru, $pg, $splat)>;
   def : Pat<(nxv4i32 (op nxv4i1:$pg, i32:$splat, nxv4i32:$passthru)),
             (!cast<Instruction>(NAME # _S) $passthru, $pg, $splat)>;
   def : Pat<(nxv2i64 (op nxv2i1:$pg, i64:$splat, nxv2i64:$passthru)),
             (!cast<Instruction>(NAME # _D) $passthru, $pg, $splat)>;
 }
 
 class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty,
                          RegisterClass srcRegtype>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, srcRegtype:$Vn),
   asm, "\t$Zd, $Pg/m, $Vn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Vn;
   bits<5> Zd;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;

 
 multiclass sve_int_perm_cpy_v<string asm, SDPatternOperator op> {
   def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
   def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
   def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>;
   def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
 
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny_p0to7:$Pg, FPR8:$Vn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny_p0to7:$Pg, FPR16:$Vn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny_p0to7:$Pg, FPR32:$Vn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny_p0to7:$Pg, FPR64:$Vn), 1>;
 
   def : Pat<(nxv8f16 (op nxv8i1:$pg, f16:$splat, nxv8f16:$passthru)),
             (!cast<Instruction>(NAME # _H) $passthru, $pg, $splat)>;
   def : Pat<(nxv2f32 (op nxv2i1:$pg, f32:$splat, nxv2f32:$passthru)),
             (!cast<Instruction>(NAME # _S) $passthru, $pg, $splat)>;
   def : Pat<(nxv4f32 (op nxv4i1:$pg, f32:$splat, nxv4f32:$passthru)),
             (!cast<Instruction>(NAME # _S) $passthru, $pg, $splat)>;
   def : Pat<(nxv2f64 (op nxv2i1:$pg, f64:$splat, nxv2f64:$passthru)),
             (!cast<Instruction>(NAME # _D) $passthru, $pg, $splat)>;
 
   def : Pat<(nxv8bf16 (op nxv8i1:$pg, bf16:$splat, nxv8bf16:$passthru)),
             (!cast<Instruction>(NAME # _H) $passthru, $pg, $splat)>;
 }
 
 class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zd;
   bits<5> Zn;
   let Inst{31-23} = 0b000001011;
   let Inst{22}    = sz;

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Memory - Contiguous Load Group
 //===----------------------------------------------------------------------===//
 
 class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
                           RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zt;
   bits<4> imm4;
   let Inst{31-25} = 0b1010010;
: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   let Defs = !if(nf, [FFR], []);
 }
 
 multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
                                RegisterOperand listty, ZPRRegOp zprty> {
   def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
-                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1, mayLoad = 1 in {
-  def "" : Pseudo<(outs listty:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), []>,
-           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4)>;
+  def "" : Pseudo<(outs listty:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4)>;
   }
 }
 
 multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
                           ZPRRegOp zprty>
 : sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
 
 class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
   bits<5> Rn;
   bits<4> imm4;
   let Inst{31-25} = 0b1010010;
   let Inst{24-23} = msz;
   let Inst{22-20} = 0b000;
   let Inst{19-16} = imm4;
   let Inst{15-13} = 0b111;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty,
                             ZPRRegOp zprty> {
   def NAME : sve_mem_cldnt_si_base<msz, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList,
                             RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rm;
   bits<5> Rn;
   bits<5> Zt;
   let Inst{31-25} = 0b1010010;
   let Inst{24-23} = msz;
   let Inst{22-21} = 0b00;
   let Inst{20-16} = Rm;
   let Inst{15-13} = 0b110;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty,
                             ZPRRegOp zprty, RegisterOperand gprty> {
   def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<5> Rn;
   bits<3> Pg;
   bits<4> imm4;
   let Inst{31-25} = 0b1010010;
   let Inst{24-23} = sz;
   let Inst{22-20} = 0;
   let Inst{19-16} = imm4;
   let Inst{15-13} = 0b001;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand listty,
                            ZPRRegOp zprty> {
   def NAME : sve_mem_ldqr_si<sz, asm, listty>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
 }
 
 class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList,
                       RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Rm;
   let Inst{31-25} = 0b1010010;
   let Inst{24-23} = sz;
   let Inst{22-21} = 0;
   let Inst{20-16} = Rm;
   let Inst{15-13} = 0;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty,
                            ZPRRegOp zprty, RegisterOperand gprty> {
   def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
                      RegisterOperand VecList, Operand immtype>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm6),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zt;
   bits<6> imm6;
   let Inst{31-25} = 0b1000010;
: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm6),
   let mayLoad = 1;
 }
 
 multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
                           RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> {
   def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) zlistty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
                           RegisterOperand VecList>
 : I<(outs VecList:$Zt), iops,
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
: I<(outs VecList:$Zt), iops,
 
   let mayLoad = 1;
   let Uses = !if(ff, [FFR], []);
   let Defs = !if(ff, [FFR], []);
 }
 
 multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
                           ZPRRegOp zprty, RegisterOperand gprty> {
-  def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+  def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
                                asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty,
                             ZPRRegOp zprty, RegisterOperand gprty> {
-  def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+  def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
                                   asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 1>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def "" : Pseudo<(outs listty:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), []>,
-           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm)>;
+  def "" : Pseudo<(outs listty:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm)>;
   }
 }
 
 multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty,
                             ZPRRegOp zprty>
 : sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>;
 
 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, Operand immtype>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
   bits<5> Rn;
   bits<4> imm4;
   let Inst{31-25} = 0b1010010;
: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm4),
   let mayLoad = 1;
 }
 
 multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                           string asm, Operand immtype> {
   def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rm;
   bits<5> Rn;
   bits<5> Zt;
   let Inst{31-25} = 0b1010010;

 //===----------------------------------------------------------------------===//
 // SVE Memory - 32-bit Gather and Unsized Contiguous Group
 //===----------------------------------------------------------------------===//
 
 // bit xs      is '1' if offsets are signed
 // bit scaled  is '1' if the offsets are scaled
 class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
                          RegisterOperand zprext>
-: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;
   bits<5> Zt;
   let Inst{31-25} = 0b1000010;
multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm,
                                         SDPatternOperator uxtw_op,
                                         RegisterOperand sxtw_opnd,
                                         RegisterOperand uxtw_opnd,
                                         ValueType vt> {
   def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>;
   def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv4i32 (uxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$indices), vt)),
             (!cast<Instruction>(NAME # _UXTW_SCALED) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
   def : Pat<(nxv4i32 (sxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$indices), vt)),
             (!cast<Instruction>(NAME # _SXTW_SCALED) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
 }
 
 multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
                                           SDPatternOperator sxtw_op,
                                           SDPatternOperator uxtw_op,
                                           RegisterOperand sxtw_opnd,
                                           RegisterOperand uxtw_opnd,
                                           ValueType vt> {
   def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>;
   def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv4i32 (uxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt)),
             (!cast<Instruction>(NAME # _UXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
   def : Pat<(nxv4i32 (sxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt)),
             (!cast<Instruction>(NAME # _SXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 
 class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
-: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
+: I<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5),
   asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
   bits<5> Zt;
   bits<5> imm5;
   let Inst{31-25} = 0b1000010;
: I<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5),
   let Uses = !if(!eq(opc{0}, 1), [FFR], []);
 }
 
 multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty,
                                       SDPatternOperator op, ValueType vt> {
   def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 1>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _IMM : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), []>,
-             PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5)>;
+  def _IMM : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5), []>,
+             PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5)>;
   }
 
   def : Pat<(nxv4i32 (op (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt)),
             (!cast<Instruction>(NAME # _IMM) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
 }
 
 class sve_mem_prfm_si<bits<2> msz, string asm>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
   asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]",
   "",
   []>, Sched<[]> {
   bits<5> Rn;
   bits<3> Pg;
   bits<6> imm6;
   bits<4> prfop;
   let Inst{31-22} = 0b1000010111;
   let Inst{21-16} = imm6;
   let Inst{15}    = 0b0;
   let Inst{14-13} = msz;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4}     = 0b0;
   let Inst{3-0}   = prfop;
 
   let hasSideEffects = 1;
 }
 
 multiclass sve_mem_prfm_si<bits<2> msz, string asm> {
   def NAME : sve_mem_prfm_si<msz, asm>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$prfop, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
   bits<5> Rm;
   bits<5> Rn;
   bits<3> Pg;
   bits<4> prfop;
   let Inst{31-25} = 0b1000010;
   let Inst{24-23} = opc{2-1};
   let Inst{22-21} = 0b00;
   let Inst{20-16} = Rm;
   let Inst{15}    = 0b1;
   let Inst{14}    = opc{0};
   let Inst{13}    = 0b0;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4}     = 0b0;
   let Inst{3-0}   = prfop;
 
   let hasSideEffects = 1;
 }
 
 class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
                           RegisterOperand zprext>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$prfop, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;
   bits<4> prfop;
   let Inst{31-23} = 0b100001000;

 multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm,
                                       RegisterOperand sxtw_opnd,
                                       RegisterOperand uxtw_opnd,
                                       SDPatternOperator op_sxtw,
                                       SDPatternOperator op_uxtw> {
   def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
 
-  def : Pat<(op_uxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def : Pat<(op_uxtw (nxv4i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
 
-  def : Pat<(op_sxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def : Pat<(op_sxtw (nxv4i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
 }
 
 class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5),
   asm, "\t$prfop, $Pg, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
   bits<5> imm5;
   bits<4> prfop;
   let Inst{31-25} = 0b1000010;
   let Inst{24-23} = msz;
   let Inst{22-21} = 0b00;
   let Inst{20-16} = imm5;
   let Inst{15-13} = 0b111;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Zn;
   let Inst{4}     = 0b0;
   let Inst{3-0}   = prfop;
 }
 
 multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty, SDPatternOperator op> {
   def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 1>;
 
-  def : Pat<(op (nxv4i1 PPR_3b:$Pg), (nxv4i32 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_3b:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
+  def : Pat<(op (nxv4i1 PPR_p0to7:$Pg), (nxv4i32 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
 }
 
 class sve_mem_z_fill<string asm>
 : I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9),
   asm, "\t$Zt, [$Rn, $imm9, mul vl]",
   "",
   []>, Sched<[]> {
   bits<5> Rn;
: I<(outs VecList:$Zt), iops,
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve2_mem_gldnt_vs_32_ptrs<bits<5> opc, string asm,
                                   SDPatternOperator op,
                                   ValueType vt> {
-  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm),
+  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm),
                                      asm, Z_s>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 1>;
 
-  def : Pat <(nxv4i32 (op (nxv4i1 PPR3bAny:$Pg), (nxv4i32 ZPR32:$Zd), (i64 GPR64:$Rm), vt)),
-             (!cast<Instruction>(NAME # _REAL) PPR3bAny:$Pg, ZPR32:$Zd, GPR64:$Rm)>;
+  def : Pat <(nxv4i32 (op (nxv4i1 PPRAny_p0to7:$Pg), (nxv4i32 ZPR32:$Zd), (i64 GPR64:$Rm), vt)),
+             (!cast<Instruction>(NAME # _REAL) PPRAny_p0to7:$Pg, ZPR32:$Zd, GPR64:$Rm)>;
 }
 
 multiclass sve2_mem_gldnt_vs_64_ptrs<bits<5> opc, string asm,
                                    SDPatternOperator op,
                                    ValueType vt> {
-  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm),
+  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm),
                                      asm, Z_d>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 1>;
 
-  def : Pat <(nxv2i64 (op (nxv2i1 PPR3bAny:$Pg), (nxv2i64 ZPR64:$Zd), (i64 GPR64:$Rm), vt)),
-             (!cast<Instruction>(NAME # _REAL) PPR3bAny:$Pg, ZPR64:$Zd, GPR64:$Rm)>;
+  def : Pat <(nxv2i64 (op (nxv2i1 PPRAny_p0to7:$Pg), (nxv2i64 ZPR64:$Zd), (i64 GPR64:$Rm), vt)),
+             (!cast<Instruction>(NAME # _REAL) PPRAny_p0to7:$Pg, ZPR64:$Zd, GPR64:$Rm)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Memory - 64-bit Gather Group
 //===----------------------------------------------------------------------===//
 
 // bit xs      is '1' if offsets are signed
 // bit scaled  is '1' if the offsets are scaled
 // bit lsl     is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
 class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
                          RegisterOperand zprext>
-: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;
   bits<5> Zt;
   let Inst{31-25} = 0b1100010;
multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm,
                                         SDPatternOperator uxtw_op,
                                         RegisterOperand sxtw_opnd,
                                         RegisterOperand uxtw_opnd,
                                         ValueType vt> {
   def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (uxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
             (!cast<Instruction>(NAME # _UXTW_SCALED) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
   def : Pat<(nxv2i64 (sxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
             (!cast<Instruction>(NAME # _SXTW_SCALED) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
 }
 
 multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
                                           SDPatternOperator sxtw_op,
                                           SDPatternOperator uxtw_op,
                                           RegisterOperand sxtw_opnd,
                                           RegisterOperand uxtw_opnd,
                                           ValueType vt> {
   def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>;
   def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (uxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
             (!cast<Instruction>(NAME # _UXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
   def : Pat<(nxv2i64 (sxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
             (!cast<Instruction>(NAME # _SXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
                                          SDPatternOperator op,
                                          RegisterOperand zprext, ValueType vt> {
   def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _SCALED : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), []>,
-                PseudoInstExpansion<(!cast<Instruction>(NAME # _SCALED_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
+  def _SCALED : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm), []>,
+                PseudoInstExpansion<(!cast<Instruction>(NAME # _SCALED_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
                      (!cast<Instruction>(NAME # _SCALED) PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
 }
 
 multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm,
                                            SDPatternOperator op, ValueType vt> {
   def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def "" : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), []>,
-           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm)>;
+  def "" : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
             (!cast<Instruction>(NAME) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
 }
 
 class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
-: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
+: I<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5),
   asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
   bits<5> Zt;
   bits<5> imm5;
   let Inst{31-25} = 0b1100010;
: I<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5),
   let Uses = !if(!eq(opc{0}, 1), [FFR], []);
 }
 
 multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty,
                                       SDPatternOperator op, ValueType vt> {
   def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
-                 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
+                 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 1>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _IMM : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), []>,
-                  PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5)>;
+  def _IMM : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5), []>,
+                  PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5)>;
   }
 
   def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt)),
             (!cast<Instruction>(NAME # _IMM) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
 }
 
 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
 class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
                           RegisterOperand zprext>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$prfop, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Zm;
   bits<4> prfop;
   let Inst{31-23} = 0b110001000;

 multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm,
                                           RegisterOperand sxtw_opnd,
                                           RegisterOperand uxtw_opnd,
                                           SDPatternOperator op_sxtw,
                                           SDPatternOperator op_uxtw> {
   def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
 
-  def : Pat<(op_uxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def : Pat<(op_uxtw (nxv2i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
 
-  def : Pat<(op_sxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def : Pat<(op_sxtw (nxv2i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
 
 }
 
 multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm,
                                           RegisterOperand zprext, SDPatternOperator frag> {
   def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
 
-  def : Pat<(frag (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 zprext:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
+  def : Pat<(frag (nxv2i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 zprext:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
 
 }
 
 class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5),
   asm, "\t$prfop, $Pg, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
   bits<5> imm5;
   bits<4> prfop;
   let Inst{31-25} = 0b1100010;
   let Inst{24-23} = msz;
   let Inst{22-21} = 0b00;
   let Inst{20-16} = imm5;
   let Inst{15-13} = 0b111;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Zn;
   let Inst{4}     = 0b0;
   let Inst{3-0}   = prfop;
 
   let hasSideEffects = 1;
 }
 
 multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty, SDPatternOperator op> {
   def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 1>;
 
-  def : Pat<(op (nxv2i1 PPR_3b:$Pg), (nxv2i64 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_3b:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
+  def : Pat<(op (nxv2i1 PPR_p0to7:$Pg), (nxv2i64 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Compute Vector Address Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm,
                                 ZPRRegOp zprty, RegisterOperand zprext>

 }
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Reduction Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
                      ZPRRegOp zprty, FPRasZPROperand dstOpType>
-: I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs dstOpType:$Vd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Vd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Vd;
   bits<5> Zn;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = sz8_32;
: I<(outs zprty:$Zd), iops,
   let Inst{4-0}   = Zd;
 
   let ElementSize = zprty.ElementSize;
 }
 
 multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> {
 let Constraints = "$Zd = $_Zd" in {
   def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m",
-                                (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>;
+                                (ins ZPR8:$_Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn)>;
   def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m",
-                                (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>;
+                                (ins ZPR16:$_Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn)>;
   def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m",
-                                (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>;
+                                (ins ZPR32:$_Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn)>;
   def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m",
-                                (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>;
+                                (ins ZPR64:$_Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn)>;
 }
 }
 
 multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> {
   def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z",
-                                (ins PPR3bAny:$Pg, ZPR8:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR8:$Zn)>;
   def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z",
-                                (ins PPR3bAny:$Pg, ZPR16:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR16:$Zn)>;
   def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z",
-                                (ins PPR3bAny:$Pg, ZPR32:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR32:$Zn)>;
   def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z",
-                                (ins PPR3bAny:$Pg, ZPR64:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR64:$Zn)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Propagate Break Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_brkp<bits<2> opc, string asm>
 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),

 }
 
 //===----------------------------------------------------------------------===//
 // SVE2 String Processing Group
 //===----------------------------------------------------------------------===//
 
 class sve2_char_match<bit sz, bit opc, string asm,
                       PPRRegOp pprty, ZPRRegOp zprty>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, zprty:$Zm),
   asm, "\t$Pd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<4> Pd;
   bits<3> Pg;
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-23} = 0b010001010;
: I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm),
   let Inst{4-0}   = Zd;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE2 Histogram Computation - Vector Group
 //===----------------------------------------------------------------------===//
 
 class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+: I<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<5> Zd;
   bits<5> Zn;
   bits<3> Pg;
   bits<5> Zm;
   let Inst{31-23} = 0b010001011;

 }
 
 multiclass sve_bfloat_matmul_longvecl_idx<bit BT, bit sub, string asm, SDPatternOperator op> {
   def NAME : sve_bfloat_matmul_longvecl_idx<BT, sub, asm>;
   def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, nxv8bf16, nxv8bf16, i64, VectorIndexH_timm, !cast<Instruction>(NAME)>;
 }
 
 class sve_bfloat_convert<bit N, string asm>
-: I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn),
+: I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> {
   bits<5> Zd;
   bits<3> Pg;
   bits<5> Zn;
   let Inst{31-25} = 0b0110010;
   let Inst{24}    = N;
   let Inst{23-13} = 0b10001010101;
   let Inst{12-10} = Pg;
multiclass sve_fp_matrix_mla<bit sz, string asm, ZPRRegOp zprty, SDPatternOperator op, ValueType vt> {
   def : SVE_3_Op_Pat<vt, op , vt, vt, vt, !cast<Instruction>(NAME)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Memory - Contiguous Load And Replicate 256-bit Group
 //===----------------------------------------------------------------------===//
 
 class sve_mem_ldor_si<bits<2> sz, string asm, RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s32:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s32:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<5> Rn;
   bits<3> Pg;
   bits<4> imm4;
   let Inst{31-25} = 0b1010010;
   let Inst{24-23} = sz;
   let Inst{22-20} = 0b010;
   let Inst{19-16} = imm4;
   let Inst{15-13} = 0b001;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve_mem_ldor_si<bits<2> sz, string asm, RegisterOperand listty,
                            ZPRRegOp zprty, ValueType Ty, ValueType PredTy, SDNode Ld1ro> {
   def NAME : sve_mem_ldor_si<sz, asm, listty>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s32:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s32:$imm4), 0>;
 
   // Base addressing mode
-  def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$Pg), GPR64sp:$base)),
-            (!cast<Instruction>(NAME) PPR3bAny:$Pg, GPR64sp:$base, (i64 0))>;
+  def : Pat<(Ty (Ld1ro (PredTy PPRAny_p0to7:$Pg), GPR64sp:$base)),
+            (!cast<Instruction>(NAME) PPRAny_p0to7:$Pg, GPR64sp:$base, (i64 0))>;
   let AddedComplexity = 2 in {
     // Reg + Imm addressing mode
-    def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$Pg), (add GPR64:$base, (i64 simm4s32:$imm)))),
+    def : Pat<(Ty (Ld1ro (PredTy PPRAny_p0to7:$Pg), (add GPR64:$base, (i64 simm4s32:$imm)))),
               (!cast<Instruction>(NAME) $Pg, $base, simm4s32:$imm)>;
   }
 }
 
 class sve_mem_ldor_ss<bits<2> sz, string asm, RegisterOperand VecList,
                       RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
   bits<5> Rn;
   bits<5> Rm;
   let Inst{31-25} = 0b1010010;
   let Inst{24-23} = sz;
   let Inst{22-21} = 0b01;
   let Inst{20-16} = Rm;
   let Inst{15-13} = 0;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
 }
 
 multiclass sve_mem_ldor_ss<bits<2> sz, string asm, RegisterOperand listty,
                            ZPRRegOp zprty, RegisterOperand gprty, ValueType Ty,
                            ValueType PredTy, SDNode Ld1ro, ComplexPattern AddrCP> {
   def NAME : sve_mem_ldor_ss<sz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 
-  def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$gp), (AddrCP GPR64sp:$base, gprty:$offset))),
-            (!cast<Instruction>(NAME) PPR3bAny:$gp, GPR64sp:$base, gprty:$offset)>;
+  def : Pat<(Ty (Ld1ro (PredTy PPRAny_p0to7:$gp), (AddrCP GPR64sp:$base, gprty:$offset))),
+            (!cast<Instruction>(NAME) PPRAny_p0to7:$gp, GPR64sp:$base, gprty:$offset)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Interleave 128-bit Elements Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_perm_bin_perm_128_zz<bits<2> opc, bit P, string asm>
 : I<(outs ZPR128:$Zd), (ins ZPR128:$Zn, ZPR128:$Zm),

llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
   %1 = tail call <vscale x 4 x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
   ret <vscale x 4 x float> %1
 }
 
 ; Function Attrs: nounwind readnone
 ; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
-; CHECK: [[ARG4:%[0-9]+]]:ppr_3b = COPY [[ARG3]]
+; CHECK: [[ARG4:%[0-9]+]]:ppr_p0to7 = COPY [[ARG3]]
 ; CHECK: INLINEASM {{.*}} [[ARG4]]
 define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
   %1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
   ret <vscale x 8 x half> %1
 }
 
 ; Function Attrs: nounwind readnone
 ; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z0
 ; CHECK: [[ARG2:%[0-9]+]]:ppr = COPY $p0
 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY [[ARG2]]
 ; CHECK: [[ARG4:%[0-9]+]]:zpr = COPY [[ARG1]]
 ; CHECK: INLINEASM {{.*}} [[ARG3]]
 define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn) {
   %1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn)
   ret <vscale x 4 x i32> %1
 }

llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s
 
 ; Test that z8 and z9, passed in by reference, are correctly loaded from x0 and x1.
 ; i.e. z0 =  %z0
 ;         :
 ;      z7 =  %z7
 ;      x0 = &%z8
 ;      x1 = &%z9
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 4 x i32> %z8, <vscale x 4 x i32> %z9) {
 ; CHECK: name: callee_with_many_sve_arg
 ; CHECK-DAG: [[BASE:%[0-9]+]]:gpr64common = COPY $x1
-; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
+; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
 ; CHECK-DAG: [[RES:%[0-9]+]]:zpr = LD1W_IMM killed [[PTRUE]], [[BASE]]
 ; CHECK-DAG: $z0 = COPY [[RES]]
 ; CHECK:     RET_ReallyLR implicit $z0
   ret <vscale x 4 x i32> %z9
 }
 
 ; Test that z8 and z9 are passed by reference.
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @caller_with_many_sve_arg(<vscale x 4 x i32> %z) {
 ; CHECK: name: caller_with_many_sve_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
 ; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16,
 ; CHECK-NEXT:     stack-id: scalable-vector
-; CHECK-DAG:  [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
+; CHECK-DAG:  [[PTRUE:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
 ; CHECK-DAG:  ST1W_IMM %{{[0-9]+}}, [[PTRUE]], %stack.1, 0
 ; CHECK-DAG:  ST1W_IMM %{{[0-9]+}}, [[PTRUE]], %stack.0, 0
 ; CHECK-DAG:  [[BASE2:%[0-9]+]]:gpr64sp = ADDXri %stack.1, 0
 ; CHECK-DAG:  [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
 ; CHECK-DAG:  $x0 = COPY [[BASE1]]
 ; CHECK-DAG:  $x1 = COPY [[BASE2]]
 ; CHECK-NEXT: BL @callee_with_many_sve_arg
 ; CHECK:      RET_ReallyLR implicit $z0

 ;        [sp] =  &%z8
 ;      [sp+8] =  &%z9
 ;
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x0, i64 %x1, i64 %x2, i64 %x3, i64 %x4, i64 %x5, i64 %x6, i64 %x7, <vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 2 x i64> %z8, <vscale x 4 x i32> %z9) {
 ; CHECK: name: callee_with_many_gpr_sve_arg
 ; CHECK: fixedStack:
 ; CHECK:      - { id: 0, type: default, offset: 8, size: 8, alignment: 8, stack-id: default,
 ; CHECK-DAG: [[BASE:%[0-9]+]]:gpr64common = LDRXui %fixed-stack.0, 0
-; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
+; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
 ; CHECK-DAG: [[RES:%[0-9]+]]:zpr = LD1W_IMM killed [[PTRUE]], killed [[BASE]]
 ; CHECK-DAG: $z0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit $z0
   ret <vscale x 4 x i32> %z9
 }
 
 ; Test that z8 and z9 are passed by reference, where reference is passed on the stack.
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @caller_with_many_gpr_sve_arg(i64 %x, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2) {
 ; CHECK: name: caller_with_many_gpr_sve_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
 ; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16,
 ; CHECK-NEXT:     stack-id: scalable-vector
-; CHECK-DAG: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31
-; CHECK-DAG: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31
+; CHECK-DAG: [[PTRUE_S:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
+; CHECK-DAG: [[PTRUE_D:%[0-9]+]]:ppr_p0to7 = PTRUE_D 31
 ; CHECK-DAG: ST1D_IMM %{{[0-9]+}}, killed [[PTRUE_D]], %stack.0, 0
 ; CHECK-DAG: ST1W_IMM %{{[0-9]+}}, killed [[PTRUE_S]], %stack.1, 0
 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0
 ; CHECK-DAG: [[BASE2:%[0-9]+]]:gpr64common = ADDXri %stack.1, 0
 ; CHECK-DAG: [[SP:%[0-9]+]]:gpr64sp = COPY $sp
 ; CHECK-DAG: STRXui killed [[BASE1]], [[SP]], 0
 ; CHECK-DAG: STRXui killed [[BASE2]], [[SP]], 1
 ; CHECK:     BL @callee_with_many_gpr_sve_arg
 ; CHECK:     RET_ReallyLR implicit $z0
   %ret = call aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2, <vscale x 4 x i32> %z)
   ret <vscale x 4 x i32> %ret
 }

llvm/test/CodeGen/AArch64/sve-localstackalloc.mir

 name:            insert_32i8_idx
 alignment:       4
 tracksRegLiveness: true
 registers:
   - { id: 0, class: zpr, preferred-register: '' }
   - { id: 1, class: zpr, preferred-register: '' }
   - { id: 2, class: gpr32, preferred-register: '' }
   - { id: 3, class: gpr64, preferred-register: '' }
-  - { id: 5, class: ppr_3b, preferred-register: '' }
+  - { id: 5, class: ppr_p0to7, preferred-register: '' }
   - { id: 6, class: gpr64sp, preferred-register: '' }
   - { id: 7, class: zpr, preferred-register: '' }
   - { id: 8, class: zpr, preferred-register: '' }
 liveins:
   - { reg: '$z0', virtual-reg: '%0' }
   - { reg: '$z1', virtual-reg: '%1' }
   - { reg: '$w0', virtual-reg: '%2' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 # CHECK-LABEL: name: insert_32i8_idx
 # CHECK: localFrameSize:  0
 stack:
   - { id: 0, name: '', type: default, offset: 0, size: 32, alignment: 16,
       stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 machineFunctionInfo: {}
 body:             |
   bb.0 (%ir-block.0):
     liveins: $z0, $z1, $w0
 
     %2:gpr32 = COPY $w0
     %1:zpr = COPY $z1
     %0:zpr = COPY $z0
-    %5:ppr_3b = PTRUE_B 31
+    %5:ppr_p0to7 = PTRUE_B 31
     %6:gpr64sp = ADDXri %stack.0, 0, 0
     ST1B_IMM %1, %5, %6, 1 :: (store unknown-size, align 16)
     ST1B_IMM %0, %5, %stack.0, 0 :: (store unknown-size into %stack.0, align 16)
     %7:zpr = LD1B_IMM %5, %6, 1 :: (load unknown-size from %stack.0 + 16, align 16)
     %8:zpr = LD1B_IMM %5, %stack.0, 0 :: (load unknown-size from %stack.0, align 16)
     $z0 = COPY %8
     $z1 = COPY %7
     RET_ReallyLR implicit $z0, implicit $z1
 
 ...

llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir

 # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 # RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 
 # Test instruction sequences where PTEST is redundant and thus gets removed.
 ---
 name:            cmpeq_nxv16i8
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; Here we check the expected sequence with subsequent tests
     ; just asserting there is no PTEST instruction.
     ;
     ; CHECK-LABEL: name: cmpeq_nxv16i8
     ; CHECK: %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def $nzcv
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, killed %3, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_nxv8i16
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
   - { id: 7, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_nxv8i16
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_PPzZZ_H %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
     %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
     $w0 = COPY %7
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_nxv4i32
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
   - { id: 7, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_nxv4i32
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_PPzZZ_S %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
     %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
     $w0 = COPY %7
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_nxv2i64
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
   - { id: 7, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_nxv2i64
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_PPzZZ_D %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
     %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
     $w0 = COPY %7
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv16i8
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv16i8
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = PTRUE_B 31
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv8i16
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: ppr }
   - { id: 5, class: gpr32 }
   - { id: 6, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv8i16
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_H %0, %1, 0, implicit-def dead $nzcv
     PTEST_PP %0, %2, implicit-def $nzcv
     %5:gpr32 = COPY $wzr
     %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
     $w0 = COPY %6
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv4i32
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: ppr }
   - { id: 5, class: gpr32 }
   - { id: 6, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv4i32
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_S %0, %1, 0, implicit-def dead $nzcv
     PTEST_PP %0, %2, implicit-def $nzcv
     %5:gpr32 = COPY $wzr
     %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
     $w0 = COPY %6
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv2i64
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: ppr }
   - { id: 5, class: gpr32 }
   - { id: 6, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv2i64
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_D %0, %1, 0, implicit-def dead $nzcv
     PTEST_PP %0, %2, implicit-def $nzcv
     %5:gpr32 = COPY $wzr
     %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
     $w0 = COPY %6
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_wide_nxv16i8
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_wide_nxv16i8
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %3:ppr = CMPEQ_WIDE_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, killed %3, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_wide_nxv8i16
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
   - { id: 7, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_wide_nxv8i16
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_WIDE_PPzZZ_H %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
     %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
     $w0 = COPY %7
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_wide_nxv4i32
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
   - { id: 7, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_wide_nxv4i32
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_WIDE_PPzZZ_S %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
     %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
     $w0 = COPY %7
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv16i8_ptest_not_all_active
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv16i8_ptest_not_all_active
     ; CHECK: %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     ; CHECK-NEXT: %3:ppr = PTRUE_B 0
     ; CHECK-NEXT: PTEST_PP killed %3, killed %2, implicit-def $nzcv
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = PTRUE_B 0
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv16i8_ptest_of_halfs
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv16i8_ptest_of_halfs
     ; CHECK: %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     ; CHECK-NEXT: %3:ppr = PTRUE_H 31
     ; CHECK-NEXT: PTEST_PP killed %3, killed %2, implicit-def $nzcv
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = PTRUE_H 31
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_imm_nxv16i8_ptest_with_unique_pg
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$p1', virtual-reg: '%3' }
   - { reg: '$z0', virtual-reg: '%1' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $p1, $z0
 
     ; CHECK-LABEL: name: cmpeq_imm_nxv16i8_ptest_with_unique_pg
     ; CHECK: %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     ; CHECK-NEXT: %3:ppr = COPY $p1
     ; CHECK-NEXT: PTEST_PP killed %3, killed %2, implicit-def $nzcv
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = COPY $p1
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmpeq_nxv16i8_ptest_with_matching_operands
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
   - { id: 3, class: ppr }
   - { id: 4, class: gpr32 }
   - { id: 5, class: gpr32 }
 liveins:
   - { reg: '$p0', virtual-reg: '%0' }
   - { reg: '$z0', virtual-reg: '%1' }
   - { reg: '$z1', virtual-reg: '%2' }
 frameInfo:
   maxCallFrameSize: 0
 body:             |
   bb.0:
     liveins: $p0, $z0, $z1
 
     ; CHECK-LABEL: name: cmpeq_nxv16i8_ptest_with_matching_operands
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %3, killed %3, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
     %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     $w0 = COPY %5
     RET_ReallyLR implicit $w0
 
 ...
 ## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 # CHECK: {{.*}}

llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir

 # RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
 # Test that RDFFR followed by PTEST is replaced with RDFFRS.
 ---
 # CHECK-LABEL: name:{{\s*}} substitute_rdffr_pp_with_rdffrs_pp
 name:                       substitute_rdffr_pp_with_rdffrs_pp
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $ffr, $p0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
 
     ; CHECK: RDFFRS_PPz
     ; CHECK-NOT: PTEST
-    %1:ppr_3b = RDFFR_PPz %0:ppr_3b
-    PTEST_PP killed %0:ppr_3b, killed %1:ppr_3b, implicit-def $nzcv
+    %1:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
+    PTEST_PP killed %0:ppr_p0to7, killed %1:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %2:gpr32 = COPY $wzr
     %3:gpr32 = CSINCWr killed %2, $wzr, 0, implicit $nzcv
     $w0 = COPY %3
     RET_ReallyLR implicit $w0
 ...
 ---
 # CHECK-LABEL: name:{{\s*}} fail_to_substitute_rdffr_pp_with_rdffrs_pp_differing_mask
 name:                       fail_to_substitute_rdffr_pp_with_rdffrs_pp_differing_mask
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $ffr, $p0, $p1
-    %0:ppr_3b = COPY $p0
-    %1:ppr_3b = COPY $p1
+    %0:ppr_p0to7 = COPY $p0
+    %1:ppr_p0to7 = COPY $p1
 
     ; CHECK: RDFFR_PPz
     ; CHECK: PTEST
-    %2:ppr_3b = RDFFR_PPz %0:ppr_3b
-    PTEST_PP killed %1:ppr_3b, killed %2:ppr_3b, implicit-def $nzcv
+    %2:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
+    PTEST_PP killed %1:ppr_p0to7, killed %2:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %3:gpr32 = COPY $wzr
     %4:gpr32 = CSINCWr killed %3, $wzr, 0, implicit $nzcv
     $w0 = COPY %4
     RET_ReallyLR implicit $w0
 ...
 ---
 # CHECK-LABEL: name:{{\s*}} fail_to_substitute_rdffr_pp_with_rdffrs_pp_nzcv_clobbered
 name:                       fail_to_substitute_rdffr_pp_with_rdffrs_pp_nzcv_clobbered
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $ffr, $p0, $x0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
 
     ; CHECK: RDFFR_PPz
     ; CHECK-NEXT: ADDSXrr
     ; CHECK-NEXT: PTEST_PP
-    %1:ppr_3b = RDFFR_PPz %0:ppr_3b
+    %1:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
     ; Clobber nzcv
     $x0 = ADDSXrr $x0, $x0, implicit-def $nzcv
-    PTEST_PP killed %0:ppr_3b, killed %1:ppr_3b, implicit-def $nzcv
+    PTEST_PP killed %0:ppr_p0to7, killed %1:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %2:gpr32 = COPY $wzr
     %3:gpr32 = CSINCWr killed %2, $wzr, 0, implicit $nzcv
     $w0 = COPY %3
     RET_ReallyLR implicit $w0
 ...
 ---
 # CHECK-LABEL: name:{{\s*}} fail_to_substitute_rdffr_pp_with_rdffrs_pp_nzcv_flags_used_between
 name:                       fail_to_substitute_rdffr_pp_with_rdffrs_pp_nzcv_flags_used_between
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $ffr, $p0, $x0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
 
     $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
 
     ; CHECK: RDFFR_PPz
     ; CHECK-NEXT: CSINCWr
     ; CHECK-NEXT: PTEST_PP
-    %1:ppr_3b = RDFFR_PPz %0:ppr_3b
+    %1:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
     ; Consume nzcv
     %2:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
-    PTEST_PP killed %0:ppr_3b, killed %1:ppr_3b, implicit-def $nzcv
+    PTEST_PP killed %0:ppr_p0to7, killed %1:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %3:gpr32 = COPY $wzr
     %4:gpr32 = CSINCWr killed %3, $wzr, 0, implicit $nzcv
     $w0 = ORRWrs %4, %2, 1
     RET_ReallyLR implicit $w0