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Differential D135974

[AArch64] Replace sme-i64 by sme-i16i64 and sme-f64 by sme-f64f64
ClosedPublic

Authored by CarolineConcatto on Oct 14 2022, 10:45 AM.

Details

Reviewers
sdesmalen
kmclaughlin
c-rhodes
Commits
rG579ca5e7e106: [AArch64] Replace sme-i64 by sme-i16i64 and sme-f64 by sme-f64f64
Summary

The names in developer.arm for these SME features are:

HaveSMEI16I64 and HaveSMEF64F64

so the new flag names are consistent with the documentation page

Diff Detail

Revision Contents

Diff 468835

llvm/include/llvm/Support/AArch64TargetParser.h

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesenum ArchExtKind : uint64_t {
AEK_I8MM = 1 << 30, // FEAT_I8MM AEK_I8MM = 1 << 30, // FEAT_I8MM
AEK_F32MM = 1ULL << 31, // FEAT_F32MM AEK_F32MM = 1ULL << 31, // FEAT_F32MM
AEK_F64MM = 1ULL << 32, // FEAT_F64MM AEK_F64MM = 1ULL << 32, // FEAT_F64MM
AEK_LS64 = 1ULL << 33, // FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA AEK_LS64 = 1ULL << 33, // FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA
AEK_BRBE = 1ULL << 34, // FEAT_BRBE AEK_BRBE = 1ULL << 34, // FEAT_BRBE
AEK_PAUTH = 1ULL << 35, // FEAT_PAuth AEK_PAUTH = 1ULL << 35, // FEAT_PAuth
AEK_FLAGM = 1ULL << 36, // FEAT_FlagM AEK_FLAGM = 1ULL << 36, // FEAT_FlagM
AEK_SME = 1ULL << 37, // FEAT_SME AEK_SME = 1ULL << 37, // FEAT_SME
AEK_SMEF64 = 1ULL << 38, // FEAT_SME_F64F64 AEK_SMEF64F64 = 1ULL << 38, // FEAT_SME_F64F64
AEK_SMEI64 = 1ULL << 39, // FEAT_SME_I16I64 AEK_SMEI16I64 = 1ULL << 39, // FEAT_SME_I16I64
AEK_HBC = 1ULL << 40, // FEAT_HBC AEK_HBC = 1ULL << 40, // FEAT_HBC
AEK_MOPS = 1ULL << 41, // FEAT_MOPS AEK_MOPS = 1ULL << 41, // FEAT_MOPS
AEK_PERFMON = 1ULL << 42, // FEAT_PMUv3 AEK_PERFMON = 1ULL << 42, // FEAT_PMUv3
AEK_SME2 = 1ULL << 43, // FEAT_SME2 AEK_SME2 = 1ULL << 43, // FEAT_SME2
}; };
enum class ArchKind { enum class ArchKind {
#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
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llvm/include/llvm/Support/AArch64TargetParser.def

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
AARCH64_ARCH_EXT_NAME("f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm") AARCH64_ARCH_EXT_NAME("f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm")
AARCH64_ARCH_EXT_NAME("f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm") AARCH64_ARCH_EXT_NAME("f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm")
AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme") AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme")
AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64, "+ls64", "-ls64") AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64, "+ls64", "-ls64")
AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE, "+brbe", "-brbe") AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE, "+brbe", "-brbe")
AARCH64_ARCH_EXT_NAME("pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth") AARCH64_ARCH_EXT_NAME("pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth")
AARCH64_ARCH_EXT_NAME("flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm") AARCH64_ARCH_EXT_NAME("flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm")
AARCH64_ARCH_EXT_NAME("sme", AArch64::AEK_SME, "+sme", "-sme") AARCH64_ARCH_EXT_NAME("sme", AArch64::AEK_SME, "+sme", "-sme")
AARCH64_ARCH_EXT_NAME("sme-f64", AArch64::AEK_SMEF64, "+sme-f64", "-sme-f64") AARCH64_ARCH_EXT_NAME("sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64")
AARCH64_ARCH_EXT_NAME("sme-i64", AArch64::AEK_SMEI64, "+sme-i64", "-sme-i64") AARCH64_ARCH_EXT_NAME("sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64")
AARCH64_ARCH_EXT_NAME("sme2", AArch64::AEK_SME2, "+sme2", "-sme2") AARCH64_ARCH_EXT_NAME("sme2", AArch64::AEK_SME2, "+sme2", "-sme2")
AARCH64_ARCH_EXT_NAME("hbc", AArch64::AEK_HBC, "+hbc", "-hbc") AARCH64_ARCH_EXT_NAME("hbc", AArch64::AEK_HBC, "+hbc", "-hbc")
AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops", "-mops") AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops", "-mops")
AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon") AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon")
#undef AARCH64_ARCH_EXT_NAME #undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME #ifndef AARCH64_CPU_NAME
#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
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llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Linesdef FeatureEnhancedCounterVirtualization :
"true", "Enable enhanced counter virtualization extension (FEAT_ECV)">; "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">;
def FeatureRME : SubtargetFeature<"rme", "HasRME", def FeatureRME : SubtargetFeature<"rme", "HasRME",
"true", "Enable Realm Management Extension (FEAT_RME)">; "true", "Enable Realm Management Extension (FEAT_RME)">;
def FeatureSME : SubtargetFeature<"sme", "HasSME", "true", def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
"Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>; "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true", def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true",
"Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>; "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>;
def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true", def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true",
"Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true",
"Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true", def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
"Apple A7 (the CPU formerly known as Cyclone)">; "Apple A7 (the CPU formerly known as Cyclone)">;
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME]; HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME];
} }
def PAUnsupported : AArch64Unsupported { def PAUnsupported : AArch64Unsupported {
let F = [HasPAuth]; let F = [HasPAuth];
} }
def SMEUnsupported : AArch64Unsupported { def SMEUnsupported : AArch64Unsupported {
let F = [HasSME, HasSMEF64, HasSMEI64, HasSME2]; let F = [HasSME, HasSMEF64F64, HasSMEI16I64, HasSME2];
} }
include "AArch64SchedA53.td" include "AArch64SchedA53.td"
include "AArch64SchedA55.td" include "AArch64SchedA55.td"
include "AArch64SchedA57.td" include "AArch64SchedA57.td"
include "AArch64SchedCyclone.td" include "AArch64SchedCyclone.td"
include "AArch64SchedFalkor.td" include "AArch64SchedFalkor.td"
include "AArch64SchedKryo.td" include "AArch64SchedKryo.td"
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llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">, def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">; AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">;
def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">, def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">; AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">;
def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">, def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2BitPerm), "sve2-bitperm">; AssemblerPredicateWithAll<(all_of FeatureSVE2BitPerm), "sve2-bitperm">;
def HasSME : Predicate<"Subtarget->hasSME()">, def HasSME : Predicate<"Subtarget->hasSME()">,
AssemblerPredicateWithAll<(all_of FeatureSME), "sme">; AssemblerPredicateWithAll<(all_of FeatureSME), "sme">;
def HasSMEF64 : Predicate<"Subtarget->hasSMEF64()">, def HasSMEF64F64 : Predicate<"Subtarget->hasSMEF64F64()">,
AssemblerPredicateWithAll<(all_of FeatureSMEF64), "sme-f64">; AssemblerPredicateWithAll<(all_of FeatureSMEF64F64), "sme-f64f64">;
def HasSMEI64 : Predicate<"Subtarget->hasSMEI64()">, def HasSMEI16I64 : Predicate<"Subtarget->hasSMEI16I64()">,
AssemblerPredicateWithAll<(all_of FeatureSMEI64), "sme-i64">; AssemblerPredicateWithAll<(all_of FeatureSMEI16I64), "sme-i16i64">;
def HasSME2 : Predicate<"Subtarget->hasSME2()">, def HasSME2 : Predicate<"Subtarget->hasSME2()">,
AssemblerPredicate<(all_of FeatureSME2), "sme2">; AssemblerPredicate<(all_of FeatureSME2), "sme2">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode, // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified. // they should be enabled if either has been specified.
def HasSVEorSME def HasSVEorSME
: Predicate<"Subtarget->hasSVE() || Subtarget->hasSME()">, : Predicate<"Subtarget->hasSVE() || Subtarget->hasSME()">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME), AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
"sve or sme">; "sve or sme">;
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llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Show All 37 Lines
def ADDSVL_XXI : sve_int_arith_vl<0b0, "addsvl", /*streaming_sve=*/0b1>; def ADDSVL_XXI : sve_int_arith_vl<0b0, "addsvl", /*streaming_sve=*/0b1>;
def ADDHA_MPPZ_S : sme_add_vector_to_tile_u32<0b0, "addha">; def ADDHA_MPPZ_S : sme_add_vector_to_tile_u32<0b0, "addha">;
def ADDVA_MPPZ_S : sme_add_vector_to_tile_u32<0b1, "addva">; def ADDVA_MPPZ_S : sme_add_vector_to_tile_u32<0b1, "addva">;
def : Pat<(AArch64rdsvl (i32 simm6_32b:$imm)), (RDSVLI_XI simm6_32b:$imm)>; def : Pat<(AArch64rdsvl (i32 simm6_32b:$imm)), (RDSVLI_XI simm6_32b:$imm)>;
} }
let Predicates = [HasSMEI64] in { let Predicates = [HasSMEI16I64] in {
def ADDHA_MPPZ_D : sme_add_vector_to_tile_u64<0b0, "addha">; def ADDHA_MPPZ_D : sme_add_vector_to_tile_u64<0b0, "addha">;
def ADDVA_MPPZ_D : sme_add_vector_to_tile_u64<0b1, "addva">; def ADDVA_MPPZ_D : sme_add_vector_to_tile_u64<0b1, "addva">;
} }
let Predicates = [HasSME] in { let Predicates = [HasSME] in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Outer products // Outer products
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm BFMOPA_MPPZZ : sme_bf16_outer_product<0b0, "bfmopa", int_aarch64_sme_mopa_wide>; defm BFMOPA_MPPZZ : sme_bf16_outer_product<0b0, "bfmopa", int_aarch64_sme_mopa_wide>;
defm BFMOPS_MPPZZ : sme_bf16_outer_product<0b1, "bfmops", int_aarch64_sme_mops_wide>; defm BFMOPS_MPPZZ : sme_bf16_outer_product<0b1, "bfmops", int_aarch64_sme_mops_wide>;
defm FMOPA_MPPZZ_S : sme_outer_product_fp32<0b0, "fmopa", int_aarch64_sme_mopa>; defm FMOPA_MPPZZ_S : sme_outer_product_fp32<0b0, "fmopa", int_aarch64_sme_mopa>;
defm FMOPS_MPPZZ_S : sme_outer_product_fp32<0b1, "fmops", int_aarch64_sme_mops>; defm FMOPS_MPPZZ_S : sme_outer_product_fp32<0b1, "fmops", int_aarch64_sme_mops>;
} }
let Predicates = [HasSMEF64] in { let Predicates = [HasSMEF64F64] in {
defm FMOPA_MPPZZ_D : sme_outer_product_fp64<0b0, "fmopa", int_aarch64_sme_mopa>; defm FMOPA_MPPZZ_D : sme_outer_product_fp64<0b0, "fmopa", int_aarch64_sme_mopa>;
defm FMOPS_MPPZZ_D : sme_outer_product_fp64<0b1, "fmops", int_aarch64_sme_mops>; defm FMOPS_MPPZZ_D : sme_outer_product_fp64<0b1, "fmops", int_aarch64_sme_mops>;
} }
let Predicates = [HasSME] in { let Predicates = [HasSME] in {
defm FMOPAL_MPPZZ : sme_f16_outer_product<0b0, "fmopa", int_aarch64_sme_mopa_wide>; defm FMOPAL_MPPZZ : sme_f16_outer_product<0b0, "fmopa", int_aarch64_sme_mopa_wide>;
defm FMOPSL_MPPZZ : sme_f16_outer_product<0b1, "fmops", int_aarch64_sme_mops_wide>; defm FMOPSL_MPPZZ : sme_f16_outer_product<0b1, "fmops", int_aarch64_sme_mops_wide>;
defm SMOPA_MPPZZ_S : sme_int_outer_product_i32<0b000, "smopa", int_aarch64_sme_smopa_wide>; defm SMOPA_MPPZZ_S : sme_int_outer_product_i32<0b000, "smopa", int_aarch64_sme_smopa_wide>;
defm SMOPS_MPPZZ_S : sme_int_outer_product_i32<0b001, "smops", int_aarch64_sme_smops_wide>; defm SMOPS_MPPZZ_S : sme_int_outer_product_i32<0b001, "smops", int_aarch64_sme_smops_wide>;
defm UMOPA_MPPZZ_S : sme_int_outer_product_i32<0b110, "umopa", int_aarch64_sme_umopa_wide>; defm UMOPA_MPPZZ_S : sme_int_outer_product_i32<0b110, "umopa", int_aarch64_sme_umopa_wide>;
defm UMOPS_MPPZZ_S : sme_int_outer_product_i32<0b111, "umops", int_aarch64_sme_umops_wide>; defm UMOPS_MPPZZ_S : sme_int_outer_product_i32<0b111, "umops", int_aarch64_sme_umops_wide>;
defm SUMOPA_MPPZZ_S : sme_int_outer_product_i32<0b010, "sumopa", int_aarch64_sme_sumopa_wide>; defm SUMOPA_MPPZZ_S : sme_int_outer_product_i32<0b010, "sumopa", int_aarch64_sme_sumopa_wide>;
defm SUMOPS_MPPZZ_S : sme_int_outer_product_i32<0b011, "sumops", int_aarch64_sme_sumops_wide>; defm SUMOPS_MPPZZ_S : sme_int_outer_product_i32<0b011, "sumops", int_aarch64_sme_sumops_wide>;
defm USMOPA_MPPZZ_S : sme_int_outer_product_i32<0b100, "usmopa", int_aarch64_sme_usmopa_wide>; defm USMOPA_MPPZZ_S : sme_int_outer_product_i32<0b100, "usmopa", int_aarch64_sme_usmopa_wide>;
defm USMOPS_MPPZZ_S : sme_int_outer_product_i32<0b101, "usmops", int_aarch64_sme_usmops_wide>; defm USMOPS_MPPZZ_S : sme_int_outer_product_i32<0b101, "usmops", int_aarch64_sme_usmops_wide>;
} }
let Predicates = [HasSMEI64] in { let Predicates = [HasSMEI16I64] in {
defm SMOPA_MPPZZ_D : sme_int_outer_product_i64<0b000, "smopa", int_aarch64_sme_smopa_wide>; defm SMOPA_MPPZZ_D : sme_int_outer_product_i64<0b000, "smopa", int_aarch64_sme_smopa_wide>;
defm SMOPS_MPPZZ_D : sme_int_outer_product_i64<0b001, "smops", int_aarch64_sme_smops_wide>; defm SMOPS_MPPZZ_D : sme_int_outer_product_i64<0b001, "smops", int_aarch64_sme_smops_wide>;
defm UMOPA_MPPZZ_D : sme_int_outer_product_i64<0b110, "umopa", int_aarch64_sme_umopa_wide>; defm UMOPA_MPPZZ_D : sme_int_outer_product_i64<0b110, "umopa", int_aarch64_sme_umopa_wide>;
defm UMOPS_MPPZZ_D : sme_int_outer_product_i64<0b111, "umops", int_aarch64_sme_umops_wide>; defm UMOPS_MPPZZ_D : sme_int_outer_product_i64<0b111, "umops", int_aarch64_sme_umops_wide>;
defm SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa", int_aarch64_sme_sumopa_wide>; defm SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa", int_aarch64_sme_sumopa_wide>;
defm SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops", int_aarch64_sme_sumops_wide>; defm SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops", int_aarch64_sme_sumops_wide>;
defm USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa", int_aarch64_sme_usmopa_wide>; defm USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa", int_aarch64_sme_usmopa_wide>;
defm USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops", int_aarch64_sme_usmops_wide>; defm USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops", int_aarch64_sme_usmops_wide>;
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llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 3,291 Lines • ▼ Show 20 Lines const FeatureBitset Features;
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}}, {"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}}, {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
{"ls64", {AArch64::FeatureLS64}}, {"ls64", {AArch64::FeatureLS64}},
{"xs", {AArch64::FeatureXS}}, {"xs", {AArch64::FeatureXS}},
{"pauth", {AArch64::FeaturePAuth}}, {"pauth", {AArch64::FeaturePAuth}},
{"flagm", {AArch64::FeatureFlagM}}, {"flagm", {AArch64::FeatureFlagM}},
{"rme", {AArch64::FeatureRME}}, {"rme", {AArch64::FeatureRME}},
{"sme", {AArch64::FeatureSME}}, {"sme", {AArch64::FeatureSME}},
{"sme-f64", {AArch64::FeatureSMEF64}}, {"sme-f64f64", {AArch64::FeatureSMEF64F64}},
{"sme-i64", {AArch64::FeatureSMEI64}}, {"sme-i16i64", {AArch64::FeatureSMEI16I64}},
{"hbc", {AArch64::FeatureHBC}}, {"hbc", {AArch64::FeatureHBC}},
{"mops", {AArch64::FeatureMOPS}}, {"mops", {AArch64::FeatureMOPS}},
// FIXME: Unsupported extensions // FIXME: Unsupported extensions
{"lor", {}}, {"lor", {}},
{"rdma", {}}, {"rdma", {}},
{"profile", {}}, {"profile", {}},
}; };
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llvm/lib/Target/AArch64/SMEInstrFormats.td

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 Linesdef : Pat<(int_aarch64_sme_addha
imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm), imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
(nxv4i32 ZPR32:$zn)), (nxv4i32 ZPR32:$zn)),
(ADDHA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>; (ADDHA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
def : Pat<(int_aarch64_sme_addva def : Pat<(int_aarch64_sme_addva
imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm), imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
(nxv4i32 ZPR32:$zn)), (nxv4i32 ZPR32:$zn)),
(ADDVA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>; (ADDVA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
let Predicates = [HasSMEI64] in { let Predicates = [HasSMEI16I64] in {
def ADDHA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>; def ADDHA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
def ADDVA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>; def ADDVA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
def : Pat<(int_aarch64_sme_addha def : Pat<(int_aarch64_sme_addha
imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm), imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
(nxv2i64 ZPR64:$zn)), (nxv2i64 ZPR64:$zn)),
(ADDHA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>; (ADDHA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
def : Pat<(int_aarch64_sme_addva def : Pat<(int_aarch64_sme_addva
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llvm/test/CodeGen/AArch64/sme-intrinsics-add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-i64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-i16i64 -verify-machineinstrs < %s | FileCheck %s
define void @addha_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn) { define void @addha_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn) {
; CHECK-LABEL: addha_s: ; CHECK-LABEL: addha_s:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: addha za0.s, p0/m, p1/m, z0.s ; CHECK-NEXT: addha za0.s, p0/m, p1/m, z0.s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sme.addha.nxv4i32(i64 0, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn) call void @llvm.aarch64.sme.addha.nxv4i32(i64 0, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn)
ret void ret void
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llvm/test/CodeGen/AArch64/sme-intrinsics-mopa.ll

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; CHECK-LABEL: usmopa_d: ; CHECK-LABEL: usmopa_d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: usmopa za7.d, p0/m, p1/m, z0.h, z1.h ; CHECK-NEXT: usmopa za7.d, p0/m, p1/m, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i64 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) call void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i64 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
ret void ret void
} }
attributes #0 = { "target-features"="+sme-i64" } attributes #0 = { "target-features"="+sme-i16i64" }
attributes #1 = { "target-features"="+sme-f64" } attributes #1 = { "target-features"="+sme-f64f64" }
declare void @llvm.aarch64.sme.mopa.wide.nxv8bf16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) declare void @llvm.aarch64.sme.mopa.wide.nxv8bf16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare void @llvm.aarch64.sme.mopa.wide.nxv8f16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) declare void @llvm.aarch64.sme.mopa.wide.nxv8f16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
declare void @llvm.aarch64.sme.mopa.nxv4f32(i64, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) declare void @llvm.aarch64.sme.mopa.nxv4f32(i64, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
declare void @llvm.aarch64.sme.mopa.nxv2f64(i64, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) declare void @llvm.aarch64.sme.mopa.nxv2f64(i64, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
declare void @llvm.aarch64.sme.smopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.smopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.smopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.smopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare void @llvm.aarch64.sme.umopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.umopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.umopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.umopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare void @llvm.aarch64.sme.sumopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.sumopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.sumopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.sumopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare void @llvm.aarch64.sme.usmopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.usmopa.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.usmopa.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)

llvm/test/CodeGen/AArch64/sme-intrinsics-mops.ll

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-LABEL: usmops_d: ; CHECK-LABEL: usmops_d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: usmops za7.d, p0/m, p1/m, z0.h, z1.h ; CHECK-NEXT: usmops za7.d, p0/m, p1/m, z0.h, z1.h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sme.usmops.wide.nxv8i16(i64 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) call void @llvm.aarch64.sme.usmops.wide.nxv8i16(i64 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
ret void ret void
} }
attributes #0 = { "target-features"="+sme-i64" } attributes #0 = { "target-features"="+sme-i16i64" }
attributes #1 = { "target-features"="+sme-f64" } attributes #1 = { "target-features"="+sme-f64f64" }
declare void @llvm.aarch64.sme.mops.wide.nxv8bf16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) declare void @llvm.aarch64.sme.mops.wide.nxv8bf16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare void @llvm.aarch64.sme.mops.wide.nxv8f16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) declare void @llvm.aarch64.sme.mops.wide.nxv8f16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
declare void @llvm.aarch64.sme.mops.nxv4f32(i64, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) declare void @llvm.aarch64.sme.mops.nxv4f32(i64, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
declare void @llvm.aarch64.sme.mops.nxv2f64(i64, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) declare void @llvm.aarch64.sme.mops.nxv2f64(i64, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
declare void @llvm.aarch64.sme.smops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.smops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.smops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.smops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare void @llvm.aarch64.sme.umops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.umops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.umops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.umops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare void @llvm.aarch64.sme.sumops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.sumops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.sumops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.sumops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare void @llvm.aarch64.sme.usmops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) declare void @llvm.aarch64.sme.usmops.wide.nxv16i8(i64, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare void @llvm.aarch64.sme.usmops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) declare void @llvm.aarch64.sme.usmops.wide.nxv8i16(i64, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)

llvm/test/MC/AArch64/SME/addha-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
addha za4.s, p0/m, p0/m, z0.s addha za4.s, p0/m, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addha za4.s, p0/m, p0/m, z0.s // CHECK-NEXT: addha za4.s, p0/m, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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llvm/test/MC/AArch64/SME/addha-u64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
addha za0.d, p0/m, p0/m, z0.d addha za0.d, p0/m, p0/m, z0.d
// CHECK-INST: addha za0.d, p0/m, p0/m, z0.d // CHECK-INST: addha za0.d, p0/m, p0/m, z0.d
// CHECK-ENCODING: [0x00,0x00,0xd0,0xc0] // CHECK-ENCODING: [0x00,0x00,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d00000 <unknown> // CHECK-UNKNOWN: c0d00000 <unknown>
addha za5.d, p5/m, p2/m, z10.d addha za5.d, p5/m, p2/m, z10.d
// CHECK-INST: addha za5.d, p5/m, p2/m, z10.d // CHECK-INST: addha za5.d, p5/m, p2/m, z10.d
// CHECK-ENCODING: [0x45,0x55,0xd0,0xc0] // CHECK-ENCODING: [0x45,0x55,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d05545 <unknown> // CHECK-UNKNOWN: c0d05545 <unknown>
addha za7.d, p3/m, p7/m, z13.d addha za7.d, p3/m, p7/m, z13.d
// CHECK-INST: addha za7.d, p3/m, p7/m, z13.d // CHECK-INST: addha za7.d, p3/m, p7/m, z13.d
// CHECK-ENCODING: [0xa7,0xed,0xd0,0xc0] // CHECK-ENCODING: [0xa7,0xed,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d0eda7 <unknown> // CHECK-UNKNOWN: c0d0eda7 <unknown>
addha za7.d, p7/m, p7/m, z31.d addha za7.d, p7/m, p7/m, z31.d
// CHECK-INST: addha za7.d, p7/m, p7/m, z31.d // CHECK-INST: addha za7.d, p7/m, p7/m, z31.d
// CHECK-ENCODING: [0xe7,0xff,0xd0,0xc0] // CHECK-ENCODING: [0xe7,0xff,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d0ffe7 <unknown> // CHECK-UNKNOWN: c0d0ffe7 <unknown>
addha za5.d, p3/m, p0/m, z17.d addha za5.d, p3/m, p0/m, z17.d
// CHECK-INST: addha za5.d, p3/m, p0/m, z17.d // CHECK-INST: addha za5.d, p3/m, p0/m, z17.d
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xc0] // CHECK-ENCODING: [0x25,0x0e,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d00e25 <unknown> // CHECK-UNKNOWN: c0d00e25 <unknown>
addha za1.d, p1/m, p4/m, z1.d addha za1.d, p1/m, p4/m, z1.d
// CHECK-INST: addha za1.d, p1/m, p4/m, z1.d // CHECK-INST: addha za1.d, p1/m, p4/m, z1.d
// CHECK-ENCODING: [0x21,0x84,0xd0,0xc0] // CHECK-ENCODING: [0x21,0x84,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d08421 <unknown> // CHECK-UNKNOWN: c0d08421 <unknown>
addha za0.d, p5/m, p2/m, z19.d addha za0.d, p5/m, p2/m, z19.d
// CHECK-INST: addha za0.d, p5/m, p2/m, z19.d // CHECK-INST: addha za0.d, p5/m, p2/m, z19.d
// CHECK-ENCODING: [0x60,0x56,0xd0,0xc0] // CHECK-ENCODING: [0x60,0x56,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d05660 <unknown> // CHECK-UNKNOWN: c0d05660 <unknown>
addha za0.d, p6/m, p0/m, z12.d addha za0.d, p6/m, p0/m, z12.d
// CHECK-INST: addha za0.d, p6/m, p0/m, z12.d // CHECK-INST: addha za0.d, p6/m, p0/m, z12.d
// CHECK-ENCODING: [0x80,0x19,0xd0,0xc0] // CHECK-ENCODING: [0x80,0x19,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d01980 <unknown> // CHECK-UNKNOWN: c0d01980 <unknown>
addha za1.d, p2/m, p6/m, z1.d addha za1.d, p2/m, p6/m, z1.d
// CHECK-INST: addha za1.d, p2/m, p6/m, z1.d // CHECK-INST: addha za1.d, p2/m, p6/m, z1.d
// CHECK-ENCODING: [0x21,0xc8,0xd0,0xc0] // CHECK-ENCODING: [0x21,0xc8,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d0c821 <unknown> // CHECK-UNKNOWN: c0d0c821 <unknown>
addha za5.d, p2/m, p0/m, z22.d addha za5.d, p2/m, p0/m, z22.d
// CHECK-INST: addha za5.d, p2/m, p0/m, z22.d // CHECK-INST: addha za5.d, p2/m, p0/m, z22.d
// CHECK-ENCODING: [0xc5,0x0a,0xd0,0xc0] // CHECK-ENCODING: [0xc5,0x0a,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d00ac5 <unknown> // CHECK-UNKNOWN: c0d00ac5 <unknown>
addha za2.d, p5/m, p7/m, z9.d addha za2.d, p5/m, p7/m, z9.d
// CHECK-INST: addha za2.d, p5/m, p7/m, z9.d // CHECK-INST: addha za2.d, p5/m, p7/m, z9.d
// CHECK-ENCODING: [0x22,0xf5,0xd0,0xc0] // CHECK-ENCODING: [0x22,0xf5,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d0f522 <unknown> // CHECK-UNKNOWN: c0d0f522 <unknown>
addha za7.d, p2/m, p5/m, z12.d addha za7.d, p2/m, p5/m, z12.d
// CHECK-INST: addha za7.d, p2/m, p5/m, z12.d // CHECK-INST: addha za7.d, p2/m, p5/m, z12.d
// CHECK-ENCODING: [0x87,0xa9,0xd0,0xc0] // CHECK-ENCODING: [0x87,0xa9,0xd0,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d0a987 <unknown> // CHECK-UNKNOWN: c0d0a987 <unknown>

llvm/test/MC/AArch64/SME/addva-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
addva za4.s, p0/m, p0/m, z0.s addva za4.s, p0/m, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addva za4.s, p0/m, p0/m, z0.s // CHECK-NEXT: addva za4.s, p0/m, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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llvm/test/MC/AArch64/SME/addva-u64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
addva za0.d, p0/m, p0/m, z0.d addva za0.d, p0/m, p0/m, z0.d
// CHECK-INST: addva za0.d, p0/m, p0/m, z0.d // CHECK-INST: addva za0.d, p0/m, p0/m, z0.d
// CHECK-ENCODING: [0x00,0x00,0xd1,0xc0] // CHECK-ENCODING: [0x00,0x00,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d10000 <unknown> // CHECK-UNKNOWN: c0d10000 <unknown>
addva za5.d, p5/m, p2/m, z10.d addva za5.d, p5/m, p2/m, z10.d
// CHECK-INST: addva za5.d, p5/m, p2/m, z10.d // CHECK-INST: addva za5.d, p5/m, p2/m, z10.d
// CHECK-ENCODING: [0x45,0x55,0xd1,0xc0] // CHECK-ENCODING: [0x45,0x55,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d15545 <unknown> // CHECK-UNKNOWN: c0d15545 <unknown>
addva za7.d, p3/m, p7/m, z13.d addva za7.d, p3/m, p7/m, z13.d
// CHECK-INST: addva za7.d, p3/m, p7/m, z13.d // CHECK-INST: addva za7.d, p3/m, p7/m, z13.d
// CHECK-ENCODING: [0xa7,0xed,0xd1,0xc0] // CHECK-ENCODING: [0xa7,0xed,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d1eda7 <unknown> // CHECK-UNKNOWN: c0d1eda7 <unknown>
addva za7.d, p7/m, p7/m, z31.d addva za7.d, p7/m, p7/m, z31.d
// CHECK-INST: addva za7.d, p7/m, p7/m, z31.d // CHECK-INST: addva za7.d, p7/m, p7/m, z31.d
// CHECK-ENCODING: [0xe7,0xff,0xd1,0xc0] // CHECK-ENCODING: [0xe7,0xff,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d1ffe7 <unknown> // CHECK-UNKNOWN: c0d1ffe7 <unknown>
addva za5.d, p3/m, p0/m, z17.d addva za5.d, p3/m, p0/m, z17.d
// CHECK-INST: addva za5.d, p3/m, p0/m, z17.d // CHECK-INST: addva za5.d, p3/m, p0/m, z17.d
// CHECK-ENCODING: [0x25,0x0e,0xd1,0xc0] // CHECK-ENCODING: [0x25,0x0e,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d10e25 <unknown> // CHECK-UNKNOWN: c0d10e25 <unknown>
addva za1.d, p1/m, p4/m, z1.d addva za1.d, p1/m, p4/m, z1.d
// CHECK-INST: addva za1.d, p1/m, p4/m, z1.d // CHECK-INST: addva za1.d, p1/m, p4/m, z1.d
// CHECK-ENCODING: [0x21,0x84,0xd1,0xc0] // CHECK-ENCODING: [0x21,0x84,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d18421 <unknown> // CHECK-UNKNOWN: c0d18421 <unknown>
addva za0.d, p5/m, p2/m, z19.d addva za0.d, p5/m, p2/m, z19.d
// CHECK-INST: addva za0.d, p5/m, p2/m, z19.d // CHECK-INST: addva za0.d, p5/m, p2/m, z19.d
// CHECK-ENCODING: [0x60,0x56,0xd1,0xc0] // CHECK-ENCODING: [0x60,0x56,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d15660 <unknown> // CHECK-UNKNOWN: c0d15660 <unknown>
addva za0.d, p6/m, p0/m, z12.d addva za0.d, p6/m, p0/m, z12.d
// CHECK-INST: addva za0.d, p6/m, p0/m, z12.d // CHECK-INST: addva za0.d, p6/m, p0/m, z12.d
// CHECK-ENCODING: [0x80,0x19,0xd1,0xc0] // CHECK-ENCODING: [0x80,0x19,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d11980 <unknown> // CHECK-UNKNOWN: c0d11980 <unknown>
addva za1.d, p2/m, p6/m, z1.d addva za1.d, p2/m, p6/m, z1.d
// CHECK-INST: addva za1.d, p2/m, p6/m, z1.d // CHECK-INST: addva za1.d, p2/m, p6/m, z1.d
// CHECK-ENCODING: [0x21,0xc8,0xd1,0xc0] // CHECK-ENCODING: [0x21,0xc8,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d1c821 <unknown> // CHECK-UNKNOWN: c0d1c821 <unknown>
addva za5.d, p2/m, p0/m, z22.d addva za5.d, p2/m, p0/m, z22.d
// CHECK-INST: addva za5.d, p2/m, p0/m, z22.d // CHECK-INST: addva za5.d, p2/m, p0/m, z22.d
// CHECK-ENCODING: [0xc5,0x0a,0xd1,0xc0] // CHECK-ENCODING: [0xc5,0x0a,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d10ac5 <unknown> // CHECK-UNKNOWN: c0d10ac5 <unknown>
addva za2.d, p5/m, p7/m, z9.d addva za2.d, p5/m, p7/m, z9.d
// CHECK-INST: addva za2.d, p5/m, p7/m, z9.d // CHECK-INST: addva za2.d, p5/m, p7/m, z9.d
// CHECK-ENCODING: [0x22,0xf5,0xd1,0xc0] // CHECK-ENCODING: [0x22,0xf5,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d1f522 <unknown> // CHECK-UNKNOWN: c0d1f522 <unknown>
addva za7.d, p2/m, p5/m, z12.d addva za7.d, p2/m, p5/m, z12.d
// CHECK-INST: addva za7.d, p2/m, p5/m, z12.d // CHECK-INST: addva za7.d, p2/m, p5/m, z12.d
// CHECK-ENCODING: [0x87,0xa9,0xd1,0xc0] // CHECK-ENCODING: [0x87,0xa9,0xd1,0xc0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: c0d1a987 <unknown> // CHECK-UNKNOWN: c0d1a987 <unknown>

llvm/test/MC/AArch64/SME/directives-negative.s

// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
.arch_extension sme .arch_extension sme
.arch_extension nosme .arch_extension nosme
smstart smstart
// CHECK: error: instruction requires: sme // CHECK: error: instruction requires: sme
// CHECK-NEXT: smstart // CHECK-NEXT: smstart
.arch_extension sme-f64 .arch_extension sme-f64f64
.arch_extension nosme-f64 .arch_extension nosme-f64f64
fmopa za0.d, p0/m, p0/m, z0.d, z0.d fmopa za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK: error: instruction requires: sme-f64 // CHECK: error: instruction requires: sme-f64f64
// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
.arch_extension sme-i64 .arch_extension sme-i16i64
.arch_extension nosme-i64 .arch_extension nosme-i16i64
addha za0.d, p0/m, p0/m, z0.d addha za0.d, p0/m, p0/m, z0.d
// CHECK: error: instruction requires: sme-i64 // CHECK: error: instruction requires: sme-i16i64
// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d // CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d
.arch armv9-a+sme .arch armv9-a+sme
.arch armv9-a+nosme .arch armv9-a+nosme
smstart smstart
// CHECK: error: instruction requires: sme // CHECK: error: instruction requires: sme
// CHECK-NEXT: smstart // CHECK-NEXT: smstart
.arch armv9-a+sme-f64 .arch armv9-a+sme-f64f64
.arch armv9-a+nosme-f64 .arch armv9-a+nosme-f64f64
fmopa za0.d, p0/m, p0/m, z0.d, z0.d fmopa za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK: error: instruction requires: sme-f64 // CHECK: error: instruction requires: sme-f64f64
// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
.arch armv9-a+sme-i64 .arch armv9-a+sme-i16i64
.arch armv9-a+nosme-i64 .arch armv9-a+nosme-i16i64
addha za0.d, p0/m, p0/m, z0.d addha za0.d, p0/m, p0/m, z0.d
// CHECK: error: instruction requires: sme-i64 // CHECK: error: instruction requires: sme-i16i64
// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d // CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d

llvm/test/MC/AArch64/SME/directives.s

// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s // RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
.arch_extension sme .arch_extension sme
smstart smstart
// CHECK: smstart // CHECK: smstart
.arch_extension nosme .arch_extension nosme
.arch_extension sme-f64 .arch_extension sme-f64f64
fmopa za0.d, p0/m, p0/m, z0.d, z0.d fmopa za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
.arch_extension nosme-f64 .arch_extension nosme-f64f64
.arch_extension sme-i64 .arch_extension sme-i16i64
addha za0.d, p0/m, p0/m, z0.d addha za0.d, p0/m, p0/m, z0.d
// CHECK: addha za0.d, p0/m, p0/m, z0.d // CHECK: addha za0.d, p0/m, p0/m, z0.d
.arch_extension nosme-i64 .arch_extension nosme-i16i64
.arch armv9-a+sme .arch armv9-a+sme
smstart smstart
// CHECK: smstart // CHECK: smstart
.arch armv9-a+nosme .arch armv9-a+nosme
.arch armv9-a+sme-f64 .arch armv9-a+sme-f64f64
fmopa za0.d, p0/m, p0/m, z0.d, z0.d fmopa za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
.arch armv9-a+nosme-f64 .arch armv9-a+nosme-f64f64
.arch armv9-a+sme-i64 .arch armv9-a+sme-i16i64
addha za0.d, p0/m, p0/m, z0.d addha za0.d, p0/m, p0/m, z0.d
// CHECK: addha za0.d, p0/m, p0/m, z0.d // CHECK: addha za0.d, p0/m, p0/m, z0.d

llvm/test/MC/AArch64/SME/feature.s

// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sme < %s | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sme < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sme-f64 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sme-f64f64 < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sme-i64 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sme-i16i64 < %s | FileCheck %s
// Verify +sme flags imply streaming compatible SVE instructions. // Verify +sme flags imply streaming compatible SVE instructions.
tbx z0.b, z1.b, z2.b tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b // CHECK: tbx z0.b, z1.b, z2.b
// Verify +sme flags imply +bf16 // Verify +sme flags imply +bf16
bfdot z0.s, z1.h, z2.h bfdot z0.s, z1.h, z2.h
// CHECK-INST: bfdot z0.s, z1.h, z2.h // CHECK-INST: bfdot z0.s, z1.h, z2.h

llvm/test/MC/AArch64/SME/fmopa-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-f64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-f64f64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
// non-widening // non-widening
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llvm/test/MC/AArch64/SME/fmopa-fp64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64f64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64f64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-f64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-f64f64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64f64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64f64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f64f64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Non-widening (double-precision) // Non-widening (double-precision)
fmopa za0.d, p0/m, p0/m, z0.d, z0.d fmopa za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK-INST: fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK-INST: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x00,0xc0,0x80] // CHECK-ENCODING: [0x00,0x00,0xc0,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c00000 <unknown> // CHECK-UNKNOWN: 80c00000 <unknown>
fmopa za5.d, p5/m, p2/m, z10.d, z21.d fmopa za5.d, p5/m, p2/m, z10.d, z21.d
// CHECK-INST: fmopa za5.d, p5/m, p2/m, z10.d, z21.d // CHECK-INST: fmopa za5.d, p5/m, p2/m, z10.d, z21.d
// CHECK-ENCODING: [0x45,0x55,0xd5,0x80] // CHECK-ENCODING: [0x45,0x55,0xd5,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80d55545 <unknown> // CHECK-UNKNOWN: 80d55545 <unknown>
fmopa za7.d, p3/m, p7/m, z13.d, z8.d fmopa za7.d, p3/m, p7/m, z13.d, z8.d
// CHECK-INST: fmopa za7.d, p3/m, p7/m, z13.d, z8.d // CHECK-INST: fmopa za7.d, p3/m, p7/m, z13.d, z8.d
// CHECK-ENCODING: [0xa7,0xed,0xc8,0x80] // CHECK-ENCODING: [0xa7,0xed,0xc8,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c8eda7 <unknown> // CHECK-UNKNOWN: 80c8eda7 <unknown>
fmopa za7.d, p7/m, p7/m, z31.d, z31.d fmopa za7.d, p7/m, p7/m, z31.d, z31.d
// CHECK-INST: fmopa za7.d, p7/m, p7/m, z31.d, z31.d // CHECK-INST: fmopa za7.d, p7/m, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xe7,0xff,0xdf,0x80] // CHECK-ENCODING: [0xe7,0xff,0xdf,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80dfffe7 <unknown> // CHECK-UNKNOWN: 80dfffe7 <unknown>
fmopa za5.d, p3/m, p0/m, z17.d, z16.d fmopa za5.d, p3/m, p0/m, z17.d, z16.d
// CHECK-INST: fmopa za5.d, p3/m, p0/m, z17.d, z16.d // CHECK-INST: fmopa za5.d, p3/m, p0/m, z17.d, z16.d
// CHECK-ENCODING: [0x25,0x0e,0xd0,0x80] // CHECK-ENCODING: [0x25,0x0e,0xd0,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80d00e25 <unknown> // CHECK-UNKNOWN: 80d00e25 <unknown>
fmopa za1.d, p1/m, p4/m, z1.d, z30.d fmopa za1.d, p1/m, p4/m, z1.d, z30.d
// CHECK-INST: fmopa za1.d, p1/m, p4/m, z1.d, z30.d // CHECK-INST: fmopa za1.d, p1/m, p4/m, z1.d, z30.d
// CHECK-ENCODING: [0x21,0x84,0xde,0x80] // CHECK-ENCODING: [0x21,0x84,0xde,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80de8421 <unknown> // CHECK-UNKNOWN: 80de8421 <unknown>
fmopa za0.d, p5/m, p2/m, z19.d, z20.d fmopa za0.d, p5/m, p2/m, z19.d, z20.d
// CHECK-INST: fmopa za0.d, p5/m, p2/m, z19.d, z20.d // CHECK-INST: fmopa za0.d, p5/m, p2/m, z19.d, z20.d
// CHECK-ENCODING: [0x60,0x56,0xd4,0x80] // CHECK-ENCODING: [0x60,0x56,0xd4,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80d45660 <unknown> // CHECK-UNKNOWN: 80d45660 <unknown>
fmopa za0.d, p6/m, p0/m, z12.d, z2.d fmopa za0.d, p6/m, p0/m, z12.d, z2.d
// CHECK-INST: fmopa za0.d, p6/m, p0/m, z12.d, z2.d // CHECK-INST: fmopa za0.d, p6/m, p0/m, z12.d, z2.d
// CHECK-ENCODING: [0x80,0x19,0xc2,0x80] // CHECK-ENCODING: [0x80,0x19,0xc2,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c21980 <unknown> // CHECK-UNKNOWN: 80c21980 <unknown>
fmopa za1.d, p2/m, p6/m, z1.d, z26.d fmopa za1.d, p2/m, p6/m, z1.d, z26.d
// CHECK-INST: fmopa za1.d, p2/m, p6/m, z1.d, z26.d // CHECK-INST: fmopa za1.d, p2/m, p6/m, z1.d, z26.d
// CHECK-ENCODING: [0x21,0xc8,0xda,0x80] // CHECK-ENCODING: [0x21,0xc8,0xda,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80dac821 <unknown> // CHECK-UNKNOWN: 80dac821 <unknown>
fmopa za5.d, p2/m, p0/m, z22.d, z30.d fmopa za5.d, p2/m, p0/m, z22.d, z30.d
// CHECK-INST: fmopa za5.d, p2/m, p0/m, z22.d, z30.d // CHECK-INST: fmopa za5.d, p2/m, p0/m, z22.d, z30.d
// CHECK-ENCODING: [0xc5,0x0a,0xde,0x80] // CHECK-ENCODING: [0xc5,0x0a,0xde,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80de0ac5 <unknown> // CHECK-UNKNOWN: 80de0ac5 <unknown>
fmopa za2.d, p5/m, p7/m, z9.d, z1.d fmopa za2.d, p5/m, p7/m, z9.d, z1.d
// CHECK-INST: fmopa za2.d, p5/m, p7/m, z9.d, z1.d // CHECK-INST: fmopa za2.d, p5/m, p7/m, z9.d, z1.d
// CHECK-ENCODING: [0x22,0xf5,0xc1,0x80] // CHECK-ENCODING: [0x22,0xf5,0xc1,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c1f522 <unknown> // CHECK-UNKNOWN: 80c1f522 <unknown>
fmopa za7.d, p2/m, p5/m, z12.d, z11.d fmopa za7.d, p2/m, p5/m, z12.d, z11.d
// CHECK-INST: fmopa za7.d, p2/m, p5/m, z12.d, z11.d // CHECK-INST: fmopa za7.d, p2/m, p5/m, z12.d, z11.d
// CHECK-ENCODING: [0x87,0xa9,0xcb,0x80] // CHECK-ENCODING: [0x87,0xa9,0xcb,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80cba987 <unknown> // CHECK-UNKNOWN: 80cba987 <unknown>

llvm/test/MC/AArch64/SME/fmops-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-f64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-f64f64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
// non-widening // non-widening
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SME/fmops-fp64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64f64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64f64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-f64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-f64f64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f64f64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f64f64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f64f64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Non-widening (double-precision) // Non-widening (double-precision)
fmops za0.d, p0/m, p0/m, z0.d, z0.d fmops za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK-INST: fmops za0.d, p0/m, p0/m, z0.d, z0.d // CHECK-INST: fmops za0.d, p0/m, p0/m, z0.d, z0.d
// CHECK-ENCODING: [0x10,0x00,0xc0,0x80] // CHECK-ENCODING: [0x10,0x00,0xc0,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c00010 <unknown> // CHECK-UNKNOWN: 80c00010 <unknown>
fmops za5.d, p5/m, p2/m, z10.d, z21.d fmops za5.d, p5/m, p2/m, z10.d, z21.d
// CHECK-INST: fmops za5.d, p5/m, p2/m, z10.d, z21.d // CHECK-INST: fmops za5.d, p5/m, p2/m, z10.d, z21.d
// CHECK-ENCODING: [0x55,0x55,0xd5,0x80] // CHECK-ENCODING: [0x55,0x55,0xd5,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80d55555 <unknown> // CHECK-UNKNOWN: 80d55555 <unknown>
fmops za7.d, p3/m, p7/m, z13.d, z8.d fmops za7.d, p3/m, p7/m, z13.d, z8.d
// CHECK-INST: fmops za7.d, p3/m, p7/m, z13.d, z8.d // CHECK-INST: fmops za7.d, p3/m, p7/m, z13.d, z8.d
// CHECK-ENCODING: [0xb7,0xed,0xc8,0x80] // CHECK-ENCODING: [0xb7,0xed,0xc8,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c8edb7 <unknown> // CHECK-UNKNOWN: 80c8edb7 <unknown>
fmops za7.d, p7/m, p7/m, z31.d, z31.d fmops za7.d, p7/m, p7/m, z31.d, z31.d
// CHECK-INST: fmops za7.d, p7/m, p7/m, z31.d, z31.d // CHECK-INST: fmops za7.d, p7/m, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xf7,0xff,0xdf,0x80] // CHECK-ENCODING: [0xf7,0xff,0xdf,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80dffff7 <unknown> // CHECK-UNKNOWN: 80dffff7 <unknown>
fmops za5.d, p3/m, p0/m, z17.d, z16.d fmops za5.d, p3/m, p0/m, z17.d, z16.d
// CHECK-INST: fmops za5.d, p3/m, p0/m, z17.d, z16.d // CHECK-INST: fmops za5.d, p3/m, p0/m, z17.d, z16.d
// CHECK-ENCODING: [0x35,0x0e,0xd0,0x80] // CHECK-ENCODING: [0x35,0x0e,0xd0,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80d00e35 <unknown> // CHECK-UNKNOWN: 80d00e35 <unknown>
fmops za1.d, p1/m, p4/m, z1.d, z30.d fmops za1.d, p1/m, p4/m, z1.d, z30.d
// CHECK-INST: fmops za1.d, p1/m, p4/m, z1.d, z30.d // CHECK-INST: fmops za1.d, p1/m, p4/m, z1.d, z30.d
// CHECK-ENCODING: [0x31,0x84,0xde,0x80] // CHECK-ENCODING: [0x31,0x84,0xde,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80de8431 <unknown> // CHECK-UNKNOWN: 80de8431 <unknown>
fmops za0.d, p5/m, p2/m, z19.d, z20.d fmops za0.d, p5/m, p2/m, z19.d, z20.d
// CHECK-INST: fmops za0.d, p5/m, p2/m, z19.d, z20.d // CHECK-INST: fmops za0.d, p5/m, p2/m, z19.d, z20.d
// CHECK-ENCODING: [0x70,0x56,0xd4,0x80] // CHECK-ENCODING: [0x70,0x56,0xd4,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80d45670 <unknown> // CHECK-UNKNOWN: 80d45670 <unknown>
fmops za0.d, p6/m, p0/m, z12.d, z2.d fmops za0.d, p6/m, p0/m, z12.d, z2.d
// CHECK-INST: fmops za0.d, p6/m, p0/m, z12.d, z2.d // CHECK-INST: fmops za0.d, p6/m, p0/m, z12.d, z2.d
// CHECK-ENCODING: [0x90,0x19,0xc2,0x80] // CHECK-ENCODING: [0x90,0x19,0xc2,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c21990 <unknown> // CHECK-UNKNOWN: 80c21990 <unknown>
fmops za1.d, p2/m, p6/m, z1.d, z26.d fmops za1.d, p2/m, p6/m, z1.d, z26.d
// CHECK-INST: fmops za1.d, p2/m, p6/m, z1.d, z26.d // CHECK-INST: fmops za1.d, p2/m, p6/m, z1.d, z26.d
// CHECK-ENCODING: [0x31,0xc8,0xda,0x80] // CHECK-ENCODING: [0x31,0xc8,0xda,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80dac831 <unknown> // CHECK-UNKNOWN: 80dac831 <unknown>
fmops za5.d, p2/m, p0/m, z22.d, z30.d fmops za5.d, p2/m, p0/m, z22.d, z30.d
// CHECK-INST: fmops za5.d, p2/m, p0/m, z22.d, z30.d // CHECK-INST: fmops za5.d, p2/m, p0/m, z22.d, z30.d
// CHECK-ENCODING: [0xd5,0x0a,0xde,0x80] // CHECK-ENCODING: [0xd5,0x0a,0xde,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80de0ad5 <unknown> // CHECK-UNKNOWN: 80de0ad5 <unknown>
fmops za2.d, p5/m, p7/m, z9.d, z1.d fmops za2.d, p5/m, p7/m, z9.d, z1.d
// CHECK-INST: fmops za2.d, p5/m, p7/m, z9.d, z1.d // CHECK-INST: fmops za2.d, p5/m, p7/m, z9.d, z1.d
// CHECK-ENCODING: [0x32,0xf5,0xc1,0x80] // CHECK-ENCODING: [0x32,0xf5,0xc1,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80c1f532 <unknown> // CHECK-UNKNOWN: 80c1f532 <unknown>
fmops za7.d, p2/m, p5/m, z12.d, z11.d fmops za7.d, p2/m, p5/m, z12.d, z11.d
// CHECK-INST: fmops za7.d, p2/m, p5/m, z12.d, z11.d // CHECK-INST: fmops za7.d, p2/m, p5/m, z12.d, z11.d
// CHECK-ENCODING: [0x97,0xa9,0xcb,0x80] // CHECK-ENCODING: [0x97,0xa9,0xcb,0x80]
// CHECK-ERROR: instruction requires: sme-f64 // CHECK-ERROR: instruction requires: sme-f64f64
// CHECK-UNKNOWN: 80cba997 <unknown> // CHECK-UNKNOWN: 80cba997 <unknown>

llvm/test/MC/AArch64/SME/smopa-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
smopa za0.d, p0/m, p0/m, z0.h, z0.h smopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: smopa za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: smopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0xc0,0xa0] // CHECK-ENCODING: [0x00,0x00,0xc0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c00000 <unknown> // CHECK-UNKNOWN: a0c00000 <unknown>
smopa za5.d, p5/m, p2/m, z10.h, z21.h smopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: smopa za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: smopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x45,0x55,0xd5,0xa0] // CHECK-ENCODING: [0x45,0x55,0xd5,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0d55545 <unknown> // CHECK-UNKNOWN: a0d55545 <unknown>
smopa za7.d, p3/m, p7/m, z13.h, z8.h smopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: smopa za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: smopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xa7,0xed,0xc8,0xa0] // CHECK-ENCODING: [0xa7,0xed,0xc8,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c8eda7 <unknown> // CHECK-UNKNOWN: a0c8eda7 <unknown>
smopa za7.d, p7/m, p7/m, z31.h, z31.h smopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: smopa za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: smopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xe7,0xff,0xdf,0xa0] // CHECK-ENCODING: [0xe7,0xff,0xdf,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0dfffe7 <unknown> // CHECK-UNKNOWN: a0dfffe7 <unknown>
smopa za5.d, p3/m, p0/m, z17.h, z16.h smopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: smopa za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: smopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xa0] // CHECK-ENCODING: [0x25,0x0e,0xd0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0d00e25 <unknown> // CHECK-UNKNOWN: a0d00e25 <unknown>
smopa za1.d, p1/m, p4/m, z1.h, z30.h smopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: smopa za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: smopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x21,0x84,0xde,0xa0] // CHECK-ENCODING: [0x21,0x84,0xde,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0de8421 <unknown> // CHECK-UNKNOWN: a0de8421 <unknown>
smopa za0.d, p5/m, p2/m, z19.h, z20.h smopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: smopa za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: smopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x60,0x56,0xd4,0xa0] // CHECK-ENCODING: [0x60,0x56,0xd4,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0d45660 <unknown> // CHECK-UNKNOWN: a0d45660 <unknown>
smopa za0.d, p6/m, p0/m, z12.h, z2.h smopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: smopa za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: smopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x80,0x19,0xc2,0xa0] // CHECK-ENCODING: [0x80,0x19,0xc2,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c21980 <unknown> // CHECK-UNKNOWN: a0c21980 <unknown>
smopa za1.d, p2/m, p6/m, z1.h, z26.h smopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: smopa za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: smopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x21,0xc8,0xda,0xa0] // CHECK-ENCODING: [0x21,0xc8,0xda,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0dac821 <unknown> // CHECK-UNKNOWN: a0dac821 <unknown>
smopa za5.d, p2/m, p0/m, z22.h, z30.h smopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: smopa za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: smopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xc5,0x0a,0xde,0xa0] // CHECK-ENCODING: [0xc5,0x0a,0xde,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0de0ac5 <unknown> // CHECK-UNKNOWN: a0de0ac5 <unknown>
smopa za2.d, p5/m, p7/m, z9.h, z1.h smopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: smopa za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: smopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xa0] // CHECK-ENCODING: [0x22,0xf5,0xc1,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c1f522 <unknown> // CHECK-UNKNOWN: a0c1f522 <unknown>
smopa za7.d, p2/m, p5/m, z12.h, z11.h smopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: smopa za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: smopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x87,0xa9,0xcb,0xa0] // CHECK-ENCODING: [0x87,0xa9,0xcb,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0cba987 <unknown> // CHECK-UNKNOWN: a0cba987 <unknown>

llvm/test/MC/AArch64/SME/smopa-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
smopa za4.s, p0/m, p0/m, z0.b, z0.b smopa za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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llvm/test/MC/AArch64/SME/smops-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
smops za0.d, p0/m, p0/m, z0.h, z0.h smops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: smops za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: smops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x10,0x00,0xc0,0xa0] // CHECK-ENCODING: [0x10,0x00,0xc0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c00010 <unknown> // CHECK-UNKNOWN: a0c00010 <unknown>
smops za5.d, p5/m, p2/m, z10.h, z21.h smops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: smops za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: smops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x55,0xd5,0xa0] // CHECK-ENCODING: [0x55,0x55,0xd5,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0d55555 <unknown> // CHECK-UNKNOWN: a0d55555 <unknown>
smops za7.d, p3/m, p7/m, z13.h, z8.h smops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: smops za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: smops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xed,0xc8,0xa0] // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c8edb7 <unknown> // CHECK-UNKNOWN: a0c8edb7 <unknown>
smops za7.d, p7/m, p7/m, z31.h, z31.h smops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: smops za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: smops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xf7,0xff,0xdf,0xa0] // CHECK-ENCODING: [0xf7,0xff,0xdf,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0dffff7 <unknown> // CHECK-UNKNOWN: a0dffff7 <unknown>
smops za5.d, p3/m, p0/m, z17.h, z16.h smops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: smops za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: smops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x35,0x0e,0xd0,0xa0] // CHECK-ENCODING: [0x35,0x0e,0xd0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0d00e35 <unknown> // CHECK-UNKNOWN: a0d00e35 <unknown>
smops za1.d, p1/m, p4/m, z1.h, z30.h smops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: smops za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: smops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x31,0x84,0xde,0xa0] // CHECK-ENCODING: [0x31,0x84,0xde,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0de8431 <unknown> // CHECK-UNKNOWN: a0de8431 <unknown>
smops za0.d, p5/m, p2/m, z19.h, z20.h smops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: smops za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: smops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x70,0x56,0xd4,0xa0] // CHECK-ENCODING: [0x70,0x56,0xd4,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0d45670 <unknown> // CHECK-UNKNOWN: a0d45670 <unknown>
smops za0.d, p6/m, p0/m, z12.h, z2.h smops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: smops za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: smops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x90,0x19,0xc2,0xa0] // CHECK-ENCODING: [0x90,0x19,0xc2,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c21990 <unknown> // CHECK-UNKNOWN: a0c21990 <unknown>
smops za1.d, p2/m, p6/m, z1.h, z26.h smops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: smops za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: smops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x31,0xc8,0xda,0xa0] // CHECK-ENCODING: [0x31,0xc8,0xda,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0dac831 <unknown> // CHECK-UNKNOWN: a0dac831 <unknown>
smops za5.d, p2/m, p0/m, z22.h, z30.h smops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: smops za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: smops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xd5,0x0a,0xde,0xa0] // CHECK-ENCODING: [0xd5,0x0a,0xde,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0de0ad5 <unknown> // CHECK-UNKNOWN: a0de0ad5 <unknown>
smops za2.d, p5/m, p7/m, z9.h, z1.h smops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: smops za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: smops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x32,0xf5,0xc1,0xa0] // CHECK-ENCODING: [0x32,0xf5,0xc1,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0c1f532 <unknown> // CHECK-UNKNOWN: a0c1f532 <unknown>
smops za7.d, p2/m, p5/m, z12.h, z11.h smops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: smops za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: smops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x97,0xa9,0xcb,0xa0] // CHECK-ENCODING: [0x97,0xa9,0xcb,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0cba997 <unknown> // CHECK-UNKNOWN: a0cba997 <unknown>

llvm/test/MC/AArch64/SME/smops-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
smops za4.s, p0/m, p0/m, z0.b, z0.b smops za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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llvm/test/MC/AArch64/SME/sumopa-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sumopa za0.d, p0/m, p0/m, z0.h, z0.h sumopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: sumopa za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: sumopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0xe0,0xa0] // CHECK-ENCODING: [0x00,0x00,0xe0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e00000 <unknown> // CHECK-UNKNOWN: a0e00000 <unknown>
sumopa za5.d, p5/m, p2/m, z10.h, z21.h sumopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: sumopa za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: sumopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x45,0x55,0xf5,0xa0] // CHECK-ENCODING: [0x45,0x55,0xf5,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0f55545 <unknown> // CHECK-UNKNOWN: a0f55545 <unknown>
sumopa za7.d, p3/m, p7/m, z13.h, z8.h sumopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: sumopa za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: sumopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xa7,0xed,0xe8,0xa0] // CHECK-ENCODING: [0xa7,0xed,0xe8,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e8eda7 <unknown> // CHECK-UNKNOWN: a0e8eda7 <unknown>
sumopa za7.d, p7/m, p7/m, z31.h, z31.h sumopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: sumopa za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: sumopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xe7,0xff,0xff,0xa0] // CHECK-ENCODING: [0xe7,0xff,0xff,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0ffffe7 <unknown> // CHECK-UNKNOWN: a0ffffe7 <unknown>
sumopa za5.d, p3/m, p0/m, z17.h, z16.h sumopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: sumopa za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: sumopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x25,0x0e,0xf0,0xa0] // CHECK-ENCODING: [0x25,0x0e,0xf0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0f00e25 <unknown> // CHECK-UNKNOWN: a0f00e25 <unknown>
sumopa za1.d, p1/m, p4/m, z1.h, z30.h sumopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: sumopa za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: sumopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x21,0x84,0xfe,0xa0] // CHECK-ENCODING: [0x21,0x84,0xfe,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fe8421 <unknown> // CHECK-UNKNOWN: a0fe8421 <unknown>
sumopa za0.d, p5/m, p2/m, z19.h, z20.h sumopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: sumopa za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: sumopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x60,0x56,0xf4,0xa0] // CHECK-ENCODING: [0x60,0x56,0xf4,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0f45660 <unknown> // CHECK-UNKNOWN: a0f45660 <unknown>
sumopa za0.d, p6/m, p0/m, z12.h, z2.h sumopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: sumopa za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: sumopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x80,0x19,0xe2,0xa0] // CHECK-ENCODING: [0x80,0x19,0xe2,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e21980 <unknown> // CHECK-UNKNOWN: a0e21980 <unknown>
sumopa za1.d, p2/m, p6/m, z1.h, z26.h sumopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: sumopa za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: sumopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x21,0xc8,0xfa,0xa0] // CHECK-ENCODING: [0x21,0xc8,0xfa,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fac821 <unknown> // CHECK-UNKNOWN: a0fac821 <unknown>
sumopa za5.d, p2/m, p0/m, z22.h, z30.h sumopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: sumopa za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: sumopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xc5,0x0a,0xfe,0xa0] // CHECK-ENCODING: [0xc5,0x0a,0xfe,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fe0ac5 <unknown> // CHECK-UNKNOWN: a0fe0ac5 <unknown>
sumopa za2.d, p5/m, p7/m, z9.h, z1.h sumopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: sumopa za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: sumopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x22,0xf5,0xe1,0xa0] // CHECK-ENCODING: [0x22,0xf5,0xe1,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e1f522 <unknown> // CHECK-UNKNOWN: a0e1f522 <unknown>
sumopa za7.d, p2/m, p5/m, z12.h, z11.h sumopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: sumopa za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: sumopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x87,0xa9,0xeb,0xa0] // CHECK-ENCODING: [0x87,0xa9,0xeb,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0eba987 <unknown> // CHECK-UNKNOWN: a0eba987 <unknown>

llvm/test/MC/AArch64/SME/sumopa-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
sumopa za4.s, p0/m, p0/m, z0.b, z0.b sumopa za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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llvm/test/MC/AArch64/SME/sumops-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sumops za0.d, p0/m, p0/m, z0.h, z0.h sumops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: sumops za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: sumops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x10,0x00,0xe0,0xa0] // CHECK-ENCODING: [0x10,0x00,0xe0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e00010 <unknown> // CHECK-UNKNOWN: a0e00010 <unknown>
sumops za5.d, p5/m, p2/m, z10.h, z21.h sumops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: sumops za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: sumops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x55,0xf5,0xa0] // CHECK-ENCODING: [0x55,0x55,0xf5,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0f55555 <unknown> // CHECK-UNKNOWN: a0f55555 <unknown>
sumops za7.d, p3/m, p7/m, z13.h, z8.h sumops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: sumops za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: sumops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xa0] // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e8edb7 <unknown> // CHECK-UNKNOWN: a0e8edb7 <unknown>
sumops za7.d, p7/m, p7/m, z31.h, z31.h sumops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: sumops za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: sumops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xf7,0xff,0xff,0xa0] // CHECK-ENCODING: [0xf7,0xff,0xff,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fffff7 <unknown> // CHECK-UNKNOWN: a0fffff7 <unknown>
sumops za5.d, p3/m, p0/m, z17.h, z16.h sumops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: sumops za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: sumops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x35,0x0e,0xf0,0xa0] // CHECK-ENCODING: [0x35,0x0e,0xf0,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0f00e35 <unknown> // CHECK-UNKNOWN: a0f00e35 <unknown>
sumops za1.d, p1/m, p4/m, z1.h, z30.h sumops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: sumops za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: sumops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x31,0x84,0xfe,0xa0] // CHECK-ENCODING: [0x31,0x84,0xfe,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fe8431 <unknown> // CHECK-UNKNOWN: a0fe8431 <unknown>
sumops za0.d, p5/m, p2/m, z19.h, z20.h sumops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: sumops za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: sumops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x70,0x56,0xf4,0xa0] // CHECK-ENCODING: [0x70,0x56,0xf4,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0f45670 <unknown> // CHECK-UNKNOWN: a0f45670 <unknown>
sumops za0.d, p6/m, p0/m, z12.h, z2.h sumops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: sumops za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: sumops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x90,0x19,0xe2,0xa0] // CHECK-ENCODING: [0x90,0x19,0xe2,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e21990 <unknown> // CHECK-UNKNOWN: a0e21990 <unknown>
sumops za1.d, p2/m, p6/m, z1.h, z26.h sumops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: sumops za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: sumops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x31,0xc8,0xfa,0xa0] // CHECK-ENCODING: [0x31,0xc8,0xfa,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fac831 <unknown> // CHECK-UNKNOWN: a0fac831 <unknown>
sumops za5.d, p2/m, p0/m, z22.h, z30.h sumops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: sumops za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: sumops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xd5,0x0a,0xfe,0xa0] // CHECK-ENCODING: [0xd5,0x0a,0xfe,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0fe0ad5 <unknown> // CHECK-UNKNOWN: a0fe0ad5 <unknown>
sumops za2.d, p5/m, p7/m, z9.h, z1.h sumops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: sumops za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: sumops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x32,0xf5,0xe1,0xa0] // CHECK-ENCODING: [0x32,0xf5,0xe1,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0e1f532 <unknown> // CHECK-UNKNOWN: a0e1f532 <unknown>
sumops za7.d, p2/m, p5/m, z12.h, z11.h sumops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: sumops za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: sumops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x97,0xa9,0xeb,0xa0] // CHECK-ENCODING: [0x97,0xa9,0xeb,0xa0]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a0eba997 <unknown> // CHECK-UNKNOWN: a0eba997 <unknown>

llvm/test/MC/AArch64/SME/sumops-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
sumops za4.s, p0/m, p0/m, z0.b, z0.b sumops za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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llvm/test/MC/AArch64/SME/umopa-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
umopa za0.d, p0/m, p0/m, z0.h, z0.h umopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: umopa za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: umopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0xe0,0xa1] // CHECK-ENCODING: [0x00,0x00,0xe0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e00000 <unknown> // CHECK-UNKNOWN: a1e00000 <unknown>
umopa za5.d, p5/m, p2/m, z10.h, z21.h umopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: umopa za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: umopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x45,0x55,0xf5,0xa1] // CHECK-ENCODING: [0x45,0x55,0xf5,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1f55545 <unknown> // CHECK-UNKNOWN: a1f55545 <unknown>
umopa za7.d, p3/m, p7/m, z13.h, z8.h umopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: umopa za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: umopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xa7,0xed,0xe8,0xa1] // CHECK-ENCODING: [0xa7,0xed,0xe8,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e8eda7 <unknown> // CHECK-UNKNOWN: a1e8eda7 <unknown>
umopa za7.d, p7/m, p7/m, z31.h, z31.h umopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: umopa za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: umopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xe7,0xff,0xff,0xa1] // CHECK-ENCODING: [0xe7,0xff,0xff,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1ffffe7 <unknown> // CHECK-UNKNOWN: a1ffffe7 <unknown>
umopa za5.d, p3/m, p0/m, z17.h, z16.h umopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: umopa za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: umopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x25,0x0e,0xf0,0xa1] // CHECK-ENCODING: [0x25,0x0e,0xf0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1f00e25 <unknown> // CHECK-UNKNOWN: a1f00e25 <unknown>
umopa za1.d, p1/m, p4/m, z1.h, z30.h umopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: umopa za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: umopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x21,0x84,0xfe,0xa1] // CHECK-ENCODING: [0x21,0x84,0xfe,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fe8421 <unknown> // CHECK-UNKNOWN: a1fe8421 <unknown>
umopa za0.d, p5/m, p2/m, z19.h, z20.h umopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: umopa za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: umopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x60,0x56,0xf4,0xa1] // CHECK-ENCODING: [0x60,0x56,0xf4,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1f45660 <unknown> // CHECK-UNKNOWN: a1f45660 <unknown>
umopa za0.d, p6/m, p0/m, z12.h, z2.h umopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: umopa za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: umopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x80,0x19,0xe2,0xa1] // CHECK-ENCODING: [0x80,0x19,0xe2,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e21980 <unknown> // CHECK-UNKNOWN: a1e21980 <unknown>
umopa za1.d, p2/m, p6/m, z1.h, z26.h umopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: umopa za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: umopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x21,0xc8,0xfa,0xa1] // CHECK-ENCODING: [0x21,0xc8,0xfa,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fac821 <unknown> // CHECK-UNKNOWN: a1fac821 <unknown>
umopa za5.d, p2/m, p0/m, z22.h, z30.h umopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: umopa za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: umopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xc5,0x0a,0xfe,0xa1] // CHECK-ENCODING: [0xc5,0x0a,0xfe,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fe0ac5 <unknown> // CHECK-UNKNOWN: a1fe0ac5 <unknown>
umopa za2.d, p5/m, p7/m, z9.h, z1.h umopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: umopa za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: umopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x22,0xf5,0xe1,0xa1] // CHECK-ENCODING: [0x22,0xf5,0xe1,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e1f522 <unknown> // CHECK-UNKNOWN: a1e1f522 <unknown>
umopa za7.d, p2/m, p5/m, z12.h, z11.h umopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: umopa za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: umopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x87,0xa9,0xeb,0xa1] // CHECK-ENCODING: [0x87,0xa9,0xeb,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1eba987 <unknown> // CHECK-UNKNOWN: a1eba987 <unknown>

llvm/test/MC/AArch64/SME/umopa-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
umopa za4.s, p0/m, p0/m, z0.b, z0.b umopa za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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llvm/test/MC/AArch64/SME/umops-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
umops za0.d, p0/m, p0/m, z0.h, z0.h umops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: umops za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: umops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x10,0x00,0xe0,0xa1] // CHECK-ENCODING: [0x10,0x00,0xe0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e00010 <unknown> // CHECK-UNKNOWN: a1e00010 <unknown>
umops za5.d, p5/m, p2/m, z10.h, z21.h umops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: umops za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: umops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x55,0xf5,0xa1] // CHECK-ENCODING: [0x55,0x55,0xf5,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1f55555 <unknown> // CHECK-UNKNOWN: a1f55555 <unknown>
umops za7.d, p3/m, p7/m, z13.h, z8.h umops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: umops za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: umops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xa1] // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e8edb7 <unknown> // CHECK-UNKNOWN: a1e8edb7 <unknown>
umops za7.d, p7/m, p7/m, z31.h, z31.h umops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: umops za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: umops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xf7,0xff,0xff,0xa1] // CHECK-ENCODING: [0xf7,0xff,0xff,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fffff7 <unknown> // CHECK-UNKNOWN: a1fffff7 <unknown>
umops za5.d, p3/m, p0/m, z17.h, z16.h umops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: umops za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: umops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x35,0x0e,0xf0,0xa1] // CHECK-ENCODING: [0x35,0x0e,0xf0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1f00e35 <unknown> // CHECK-UNKNOWN: a1f00e35 <unknown>
umops za1.d, p1/m, p4/m, z1.h, z30.h umops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: umops za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: umops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x31,0x84,0xfe,0xa1] // CHECK-ENCODING: [0x31,0x84,0xfe,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fe8431 <unknown> // CHECK-UNKNOWN: a1fe8431 <unknown>
umops za0.d, p5/m, p2/m, z19.h, z20.h umops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: umops za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: umops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x70,0x56,0xf4,0xa1] // CHECK-ENCODING: [0x70,0x56,0xf4,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1f45670 <unknown> // CHECK-UNKNOWN: a1f45670 <unknown>
umops za0.d, p6/m, p0/m, z12.h, z2.h umops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: umops za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: umops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x90,0x19,0xe2,0xa1] // CHECK-ENCODING: [0x90,0x19,0xe2,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e21990 <unknown> // CHECK-UNKNOWN: a1e21990 <unknown>
umops za1.d, p2/m, p6/m, z1.h, z26.h umops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: umops za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: umops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x31,0xc8,0xfa,0xa1] // CHECK-ENCODING: [0x31,0xc8,0xfa,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fac831 <unknown> // CHECK-UNKNOWN: a1fac831 <unknown>
umops za5.d, p2/m, p0/m, z22.h, z30.h umops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: umops za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: umops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xd5,0x0a,0xfe,0xa1] // CHECK-ENCODING: [0xd5,0x0a,0xfe,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1fe0ad5 <unknown> // CHECK-UNKNOWN: a1fe0ad5 <unknown>
umops za2.d, p5/m, p7/m, z9.h, z1.h umops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: umops za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: umops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x32,0xf5,0xe1,0xa1] // CHECK-ENCODING: [0x32,0xf5,0xe1,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1e1f532 <unknown> // CHECK-UNKNOWN: a1e1f532 <unknown>
umops za7.d, p2/m, p5/m, z12.h, z11.h umops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: umops za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: umops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x97,0xa9,0xeb,0xa1] // CHECK-ENCODING: [0x97,0xa9,0xeb,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1eba997 <unknown> // CHECK-UNKNOWN: a1eba997 <unknown>

llvm/test/MC/AArch64/SME/umops-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
umops za4.s, p0/m, p0/m, z0.b, z0.b umops za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SME/usmopa-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
usmopa za0.d, p0/m, p0/m, z0.h, z0.h usmopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: usmopa za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: usmopa za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0xc0,0xa1] // CHECK-ENCODING: [0x00,0x00,0xc0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c00000 <unknown> // CHECK-UNKNOWN: a1c00000 <unknown>
usmopa za5.d, p5/m, p2/m, z10.h, z21.h usmopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: usmopa za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: usmopa za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x45,0x55,0xd5,0xa1] // CHECK-ENCODING: [0x45,0x55,0xd5,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1d55545 <unknown> // CHECK-UNKNOWN: a1d55545 <unknown>
usmopa za7.d, p3/m, p7/m, z13.h, z8.h usmopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: usmopa za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: usmopa za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xa7,0xed,0xc8,0xa1] // CHECK-ENCODING: [0xa7,0xed,0xc8,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c8eda7 <unknown> // CHECK-UNKNOWN: a1c8eda7 <unknown>
usmopa za7.d, p7/m, p7/m, z31.h, z31.h usmopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: usmopa za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: usmopa za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xe7,0xff,0xdf,0xa1] // CHECK-ENCODING: [0xe7,0xff,0xdf,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1dfffe7 <unknown> // CHECK-UNKNOWN: a1dfffe7 <unknown>
usmopa za5.d, p3/m, p0/m, z17.h, z16.h usmopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: usmopa za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: usmopa za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x25,0x0e,0xd0,0xa1] // CHECK-ENCODING: [0x25,0x0e,0xd0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1d00e25 <unknown> // CHECK-UNKNOWN: a1d00e25 <unknown>
usmopa za1.d, p1/m, p4/m, z1.h, z30.h usmopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: usmopa za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: usmopa za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x21,0x84,0xde,0xa1] // CHECK-ENCODING: [0x21,0x84,0xde,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1de8421 <unknown> // CHECK-UNKNOWN: a1de8421 <unknown>
usmopa za0.d, p5/m, p2/m, z19.h, z20.h usmopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: usmopa za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: usmopa za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x60,0x56,0xd4,0xa1] // CHECK-ENCODING: [0x60,0x56,0xd4,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1d45660 <unknown> // CHECK-UNKNOWN: a1d45660 <unknown>
usmopa za0.d, p6/m, p0/m, z12.h, z2.h usmopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: usmopa za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: usmopa za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x80,0x19,0xc2,0xa1] // CHECK-ENCODING: [0x80,0x19,0xc2,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c21980 <unknown> // CHECK-UNKNOWN: a1c21980 <unknown>
usmopa za1.d, p2/m, p6/m, z1.h, z26.h usmopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: usmopa za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: usmopa za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x21,0xc8,0xda,0xa1] // CHECK-ENCODING: [0x21,0xc8,0xda,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1dac821 <unknown> // CHECK-UNKNOWN: a1dac821 <unknown>
usmopa za5.d, p2/m, p0/m, z22.h, z30.h usmopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: usmopa za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: usmopa za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xc5,0x0a,0xde,0xa1] // CHECK-ENCODING: [0xc5,0x0a,0xde,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1de0ac5 <unknown> // CHECK-UNKNOWN: a1de0ac5 <unknown>
usmopa za2.d, p5/m, p7/m, z9.h, z1.h usmopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: usmopa za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: usmopa za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x22,0xf5,0xc1,0xa1] // CHECK-ENCODING: [0x22,0xf5,0xc1,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c1f522 <unknown> // CHECK-UNKNOWN: a1c1f522 <unknown>
usmopa za7.d, p2/m, p5/m, z12.h, z11.h usmopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: usmopa za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: usmopa za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x87,0xa9,0xcb,0xa1] // CHECK-ENCODING: [0x87,0xa9,0xcb,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1cba987 <unknown> // CHECK-UNKNOWN: a1cba987 <unknown>

llvm/test/MC/AArch64/SME/usmopa-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
usmopa za4.s, p0/m, p0/m, z0.b, z0.b usmopa za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SME/usmops-64.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=+sme-i64 - | FileCheck %s --check-prefix=CHECK-INST // RUN: | llvm-objdump -d --mattr=+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-i16i64 < %s \
// RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN // RUN: | llvm-objdump -d --mattr=-sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches. // Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i64 < %s \ // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-i16i64 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i64 -disassemble -show-encoding \ // RUN: | llvm-mc -triple=aarch64 -mattr=+sme-i16i64 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
usmops za0.d, p0/m, p0/m, z0.h, z0.h usmops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-INST: usmops za0.d, p0/m, p0/m, z0.h, z0.h // CHECK-INST: usmops za0.d, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x10,0x00,0xc0,0xa1] // CHECK-ENCODING: [0x10,0x00,0xc0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c00010 <unknown> // CHECK-UNKNOWN: a1c00010 <unknown>
usmops za5.d, p5/m, p2/m, z10.h, z21.h usmops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-INST: usmops za5.d, p5/m, p2/m, z10.h, z21.h // CHECK-INST: usmops za5.d, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x55,0xd5,0xa1] // CHECK-ENCODING: [0x55,0x55,0xd5,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1d55555 <unknown> // CHECK-UNKNOWN: a1d55555 <unknown>
usmops za7.d, p3/m, p7/m, z13.h, z8.h usmops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-INST: usmops za7.d, p3/m, p7/m, z13.h, z8.h // CHECK-INST: usmops za7.d, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0xed,0xc8,0xa1] // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c8edb7 <unknown> // CHECK-UNKNOWN: a1c8edb7 <unknown>
usmops za7.d, p7/m, p7/m, z31.h, z31.h usmops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-INST: usmops za7.d, p7/m, p7/m, z31.h, z31.h // CHECK-INST: usmops za7.d, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xf7,0xff,0xdf,0xa1] // CHECK-ENCODING: [0xf7,0xff,0xdf,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1dffff7 <unknown> // CHECK-UNKNOWN: a1dffff7 <unknown>
usmops za5.d, p3/m, p0/m, z17.h, z16.h usmops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-INST: usmops za5.d, p3/m, p0/m, z17.h, z16.h // CHECK-INST: usmops za5.d, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x35,0x0e,0xd0,0xa1] // CHECK-ENCODING: [0x35,0x0e,0xd0,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1d00e35 <unknown> // CHECK-UNKNOWN: a1d00e35 <unknown>
usmops za1.d, p1/m, p4/m, z1.h, z30.h usmops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-INST: usmops za1.d, p1/m, p4/m, z1.h, z30.h // CHECK-INST: usmops za1.d, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x31,0x84,0xde,0xa1] // CHECK-ENCODING: [0x31,0x84,0xde,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1de8431 <unknown> // CHECK-UNKNOWN: a1de8431 <unknown>
usmops za0.d, p5/m, p2/m, z19.h, z20.h usmops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-INST: usmops za0.d, p5/m, p2/m, z19.h, z20.h // CHECK-INST: usmops za0.d, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x70,0x56,0xd4,0xa1] // CHECK-ENCODING: [0x70,0x56,0xd4,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1d45670 <unknown> // CHECK-UNKNOWN: a1d45670 <unknown>
usmops za0.d, p6/m, p0/m, z12.h, z2.h usmops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-INST: usmops za0.d, p6/m, p0/m, z12.h, z2.h // CHECK-INST: usmops za0.d, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x90,0x19,0xc2,0xa1] // CHECK-ENCODING: [0x90,0x19,0xc2,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c21990 <unknown> // CHECK-UNKNOWN: a1c21990 <unknown>
usmops za1.d, p2/m, p6/m, z1.h, z26.h usmops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-INST: usmops za1.d, p2/m, p6/m, z1.h, z26.h // CHECK-INST: usmops za1.d, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x31,0xc8,0xda,0xa1] // CHECK-ENCODING: [0x31,0xc8,0xda,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1dac831 <unknown> // CHECK-UNKNOWN: a1dac831 <unknown>
usmops za5.d, p2/m, p0/m, z22.h, z30.h usmops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-INST: usmops za5.d, p2/m, p0/m, z22.h, z30.h // CHECK-INST: usmops za5.d, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xd5,0x0a,0xde,0xa1] // CHECK-ENCODING: [0xd5,0x0a,0xde,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1de0ad5 <unknown> // CHECK-UNKNOWN: a1de0ad5 <unknown>
usmops za2.d, p5/m, p7/m, z9.h, z1.h usmops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-INST: usmops za2.d, p5/m, p7/m, z9.h, z1.h // CHECK-INST: usmops za2.d, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x32,0xf5,0xc1,0xa1] // CHECK-ENCODING: [0x32,0xf5,0xc1,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1c1f532 <unknown> // CHECK-UNKNOWN: a1c1f532 <unknown>
usmops za7.d, p2/m, p5/m, z12.h, z11.h usmops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-INST: usmops za7.d, p2/m, p5/m, z12.h, z11.h // CHECK-INST: usmops za7.d, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x97,0xa9,0xcb,0xa1] // CHECK-ENCODING: [0x97,0xa9,0xcb,0xa1]
// CHECK-ERROR: instruction requires: sme-i64 // CHECK-ERROR: instruction requires: sme-i16i64
// CHECK-UNKNOWN: a1cba997 <unknown> // CHECK-UNKNOWN: a1cba997 <unknown>

llvm/test/MC/AArch64/SME/usmops-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- // // ------------------------------------------------------------------------- //
// Invalid tile // Invalid tile
// //
// expected: .s => za0-za3, .d => za0-za7 // expected: .s => za0-za3, .d => za0-za7
usmops za4.s, p0/m, p0/m, z0.b, z0.b usmops za4.s, p0/m, p0/m, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/unittests/Support/TargetParserTest.cpp

Show First 20 Lines • Show All 1,497 Lines • ▼ Show 20 Lines std::vector<uint64_t> Extensions = {
AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_RAS, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_RAS,
AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2AES, AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2AES,
AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM, AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_RCPC, AArch64::AEK_RAND, AArch64::AEK_MTE, AArch64::AEK_RCPC, AArch64::AEK_RAND, AArch64::AEK_MTE,
AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_PREDRES,
AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_F32MM, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_F32MM,
AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64, AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64, AArch64::AEK_SMEI64, AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS, AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
AArch64::AEK_PERFMON}; AArch64::AEK_PERFMON};
std::vector<StringRef> Features; std::vector<StringRef> Features;
uint64_t ExtVal = 0; uint64_t ExtVal = 0;
for (auto Ext : Extensions) for (auto Ext : Extensions)
ExtVal |= Ext; ExtVal |= Ext;
Show All 40 LinesTEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+f32mm")); EXPECT_TRUE(llvm::is_contained(Features, "+f32mm"));
EXPECT_TRUE(llvm::is_contained(Features, "+f64mm")); EXPECT_TRUE(llvm::is_contained(Features, "+f64mm"));
EXPECT_TRUE(llvm::is_contained(Features, "+tme")); EXPECT_TRUE(llvm::is_contained(Features, "+tme"));
EXPECT_TRUE(llvm::is_contained(Features, "+ls64")); EXPECT_TRUE(llvm::is_contained(Features, "+ls64"));
EXPECT_TRUE(llvm::is_contained(Features, "+brbe")); EXPECT_TRUE(llvm::is_contained(Features, "+brbe"));
EXPECT_TRUE(llvm::is_contained(Features, "+pauth")); EXPECT_TRUE(llvm::is_contained(Features, "+pauth"));
EXPECT_TRUE(llvm::is_contained(Features, "+flagm")); EXPECT_TRUE(llvm::is_contained(Features, "+flagm"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme")); EXPECT_TRUE(llvm::is_contained(Features, "+sme"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-f64")); EXPECT_TRUE(llvm::is_contained(Features, "+sme-f64f64"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-i64")); EXPECT_TRUE(llvm::is_contained(Features, "+sme-i16i64"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme2")); EXPECT_TRUE(llvm::is_contained(Features, "+sme2"));
EXPECT_TRUE(llvm::is_contained(Features, "+hbc")); EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
EXPECT_TRUE(llvm::is_contained(Features, "+mops")); EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
EXPECT_TRUE(llvm::is_contained(Features, "+perfmon")); EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
// Assuming we listed every extension above, this should produce the same // Assuming we listed every extension above, this should produce the same
// result. (note that AEK_NONE doesn't have a name so it won't be in the // result. (note that AEK_NONE doesn't have a name so it won't be in the
// result despite its bit being set) // result despite its bit being set)
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines const char *ArchExt[][4] = {
{"pauth", "nopauth", "+pauth", "-pauth"}, {"pauth", "nopauth", "+pauth", "-pauth"},
{"ssbs", "nossbs", "+ssbs", "-ssbs"}, {"ssbs", "nossbs", "+ssbs", "-ssbs"},
{"sb", "nosb", "+sb", "-sb"}, {"sb", "nosb", "+sb", "-sb"},
{"predres", "nopredres", "+predres", "-predres"}, {"predres", "nopredres", "+predres", "-predres"},
{"i8mm", "noi8mm", "+i8mm", "-i8mm"}, {"i8mm", "noi8mm", "+i8mm", "-i8mm"},
{"f32mm", "nof32mm", "+f32mm", "-f32mm"}, {"f32mm", "nof32mm", "+f32mm", "-f32mm"},
{"f64mm", "nof64mm", "+f64mm", "-f64mm"}, {"f64mm", "nof64mm", "+f64mm", "-f64mm"},
{"sme", "nosme", "+sme", "-sme"}, {"sme", "nosme", "+sme", "-sme"},
{"sme-f64", "nosme-f64", "+sme-f64", "-sme-f64"}, {"sme-f64f64", "nosme-f64f64", "+sme-f64f64", "-sme-f64f64"},
{"sme-i64", "nosme-i64", "+sme-i64", "-sme-i64"}, {"sme-i16i64", "nosme-i16i64", "+sme-i16i64", "-sme-i16i64"},
{"sme2", "nosme2", "+sme2", "-sme2"}, {"sme2", "nosme2", "+sme2", "-sme2"},
{"hbc", "nohbc", "+hbc", "-hbc"}, {"hbc", "nohbc", "+hbc", "-hbc"},
{"mops", "nomops", "+mops", "-mops"}, {"mops", "nomops", "+mops", "-mops"},
{"pmuv3", "nopmuv3", "+perfmon", "-perfmon"}, {"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
}; };
for (unsigned i = 0; i < std::size(ArchExt); i++) { for (unsigned i = 0; i < std::size(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]), EXPECT_EQ(StringRef(ArchExt[i][2]),
AArch64::getArchExtFeature(ArchExt[i][0])); AArch64::getArchExtFeature(ArchExt[i][0]));
EXPECT_EQ(StringRef(ArchExt[i][3]), EXPECT_EQ(StringRef(ArchExt[i][3]),
AArch64::getArchExtFeature(ArchExt[i][1])); AArch64::getArchExtFeature(ArchExt[i][1]));
} }
} }
} // namespace } // namespace