[RegisterScavenger][RISCV] Don't search for FrameSetup instrs if we were searching from Non-FrameSetup instrs

[StephenFan]

Summary

Otherwise, the spill position may point to position where before
FrameSetup instructions. In which case, the spill instruction may store
to caller's frame since the stack pointer has not been adjustted.

Fixes https://github.com/llvm/llvm-project/issues/58286

[craig.topper]

llvm/lib/CodeGen/RegisterScavenging.cpp

378

I think "to where" should be removed from this sentence.

380

Use MI.getFlag?

[craig.topper]

If I understand correctly, the use of a vreg in the frame-setup allowed findSurvivorBackward to trigger this code

// Keep searching when we find a vreg since the spilled register will
// be usefull for this other vreg as well later.
bool FoundVReg = false;
for (const MachineOperand &MO : MI.operands()) {
  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
    FoundVReg = true;
    break;
  }
}
if (FoundVReg) {
  InstrCountDown = InstrLimit;
  Pos = I;
}

which caused the search to stop above the frame-setup. So another option might be to use T1 as the scratch register in frame-setup as was once proposed in an earlier revision of https://reviews.llvm.org/D61884

[craig.topper]

In D135693#3850055, @craig.topper wrote:

If I understand correctly, the use of a vreg in the frame-setup allowed findSurvivorBackward to trigger this code

// Keep searching when we find a vreg since the spilled register will
// be usefull for this other vreg as well later.
bool FoundVReg = false;
for (const MachineOperand &MO : MI.operands()) {
  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
    FoundVReg = true;
    break;
  }
}
if (FoundVReg) {
  InstrCountDown = InstrLimit;
  Pos = I;
}

which caused the search to stop above the frame-setup. So another option might be to use T1 as the scratch register in frame-setup as was once proposed in an earlier revision of https://reviews.llvm.org/D61884

But we can't use T1 with shrink wrapping and I've confirmed the same bug exists with shrink wrapping.

[StephenFan]

In D135693#3850538, @craig.topper wrote:

In D135693#3850055, @craig.topper wrote:

If I understand correctly, the use of a vreg in the frame-setup allowed findSurvivorBackward to trigger this code

// Keep searching when we find a vreg since the spilled register will
// be usefull for this other vreg as well later.
bool FoundVReg = false;
for (const MachineOperand &MO : MI.operands()) {
  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
    FoundVReg = true;
    break;
  }
}
if (FoundVReg) {
  InstrCountDown = InstrLimit;
  Pos = I;
}

which caused the search to stop above the frame-setup. So another option might be to use T1 as the scratch register in frame-setup as was once proposed in an earlier revision of https://reviews.llvm.org/D61884

But we can't use T1 with shrink wrapping and I've confirmed the same bug exists with shrink wrapping.

Thanks for looking into shrink-wrapping! Do you mind sharing your shrink-wrapping test cases? So that I can pick them as CodeGen/RISCV test cases.

[StephenFan]

1. Remove "to where" in comment.
2. Use MI. instead of I->
3. Update failed tests.

[StephenFan]

llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir

27

The code here seems incorrect. Here a1 is stored to 0(sp) before sub sp, sp, a1 but restored after sub sp, sp, a1.

llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

20

See the comment above.

[craig.topper]

llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir

37

This doens't look correct either.

[craig.topper]

In D135693#3851366, @StephenFan wrote:

In D135693#3850538, @craig.topper wrote:

In D135693#3850055, @craig.topper wrote:

If I understand correctly, the use of a vreg in the frame-setup allowed findSurvivorBackward to trigger this code

// Keep searching when we find a vreg since the spilled register will
// be usefull for this other vreg as well later.
bool FoundVReg = false;
for (const MachineOperand &MO : MI.operands()) {
  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
    FoundVReg = true;
    break;
  }
}
if (FoundVReg) {
  InstrCountDown = InstrLimit;
  Pos = I;
}

which caused the search to stop above the frame-setup. So another option might be to use T1 as the scratch register in frame-setup as was once proposed in an earlier revision of https://reviews.llvm.org/D61884

But we can't use T1 with shrink wrapping and I've confirmed the same bug exists with shrink wrapping.

Thanks for looking into shrink-wrapping! Do you mind sharing your shrink-wrapping test cases? So that I can pick them as CodeGen/RISCV test cases.

This was my shrink wrap case

@var = external global i32                                                       
                                                                                 
define void @func(i1 %c) {                                                       
  %space = alloca i32, align 4                                                   
  %stackspace = alloca[1024 x i32], align 4                                      
  br i1 %c, label %foo, label %bar                                               
                                                                                 
bar:                                                                             
                                                                                 
  ;; Load values to increase register pressure.                                  
  %v0 = load volatile i32, i32* @var                                             
  %v1 = load volatile i32, i32* @var                                             
  %v2 = load volatile i32, i32* @var                                             
  %v3 = load volatile i32, i32* @var                                             
  %v4 = load volatile i32, i32* @var                                             
  %v5 = load volatile i32, i32* @var                                             
  %v6 = load volatile i32, i32* @var                                             
  %v7 = load volatile i32, i32* @var                                             
  %v8 = load volatile i32, i32* @var                                             
  %v9 = load volatile i32, i32* @var                                             
  %v10 = load volatile i32, i32* @var                                            
  %v11 = load volatile i32, i32* @var                                            
  %v12 = load volatile i32, i32* @var                                            
  %v13 = load volatile i32, i32* @var                                            
                                                                                 
  store volatile i32 %v0, i32* %space                                            
                                                                                 
  ;; store values so they are used.                                              
  store volatile i32 %v0, i32* @var                                              
  store volatile i32 %v1, i32* @var                                              
  store volatile i32 %v2, i32* @var                                              
  store volatile i32 %v3, i32* @var                                              
  store volatile i32 %v4, i32* @var                                              
  store volatile i32 %v5, i32* @var                                              
  store volatile i32 %v6, i32* @var                                              
  store volatile i32 %v7, i32* @var                                              
  store volatile i32 %v8, i32* @var                                              
  store volatile i32 %v9, i32* @var                                              
  store volatile i32 %v10, i32* @var                                             
  store volatile i32 %v11, i32* @var                                             
  store volatile i32 %v12, i32* @var                                             
  store volatile i32 %v13, i32* @var                                             
  br label %foo                                                                  
                                                                                 
foo:                                                                             
  ret void                                                                       
}

[StephenFan]

Add FIXME.

[StephenFan]

llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir

37

This test case is tricky and rare. We may need to implement the target hook saveScavengerRegister to fix it. So I left a FIXME.

[StephenFan]

In D135693#3851758, @craig.topper wrote:

In D135693#3851366, @StephenFan wrote:

In D135693#3850538, @craig.topper wrote:

In D135693#3850055, @craig.topper wrote:

If I understand correctly, the use of a vreg in the frame-setup allowed findSurvivorBackward to trigger this code

// Keep searching when we find a vreg since the spilled register will
// be usefull for this other vreg as well later.
bool FoundVReg = false;
for (const MachineOperand &MO : MI.operands()) {
  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
    FoundVReg = true;
    break;
  }
}
if (FoundVReg) {
  InstrCountDown = InstrLimit;
  Pos = I;
}

which caused the search to stop above the frame-setup. So another option might be to use T1 as the scratch register in frame-setup as was once proposed in an earlier revision of https://reviews.llvm.org/D61884

But we can't use T1 with shrink wrapping and I've confirmed the same bug exists with shrink wrapping.

Thanks for looking into shrink-wrapping! Do you mind sharing your shrink-wrapping test cases? So that I can pick them as CodeGen/RISCV test cases.

This was my shrink wrap case

@var = external global i32                                                       
                                                                                 
define void @func(i1 %c) {                                                       
  %space = alloca i32, align 4                                                   
  %stackspace = alloca[1024 x i32], align 4                                      
  br i1 %c, label %foo, label %bar                                               
                                                                                 
bar:                                                                             
                                                                                 
  ;; Load values to increase register pressure.                                  
  %v0 = load volatile i32, i32* @var                                             
  %v1 = load volatile i32, i32* @var                                             
  %v2 = load volatile i32, i32* @var                                             
  %v3 = load volatile i32, i32* @var                                             
  %v4 = load volatile i32, i32* @var                                             
  %v5 = load volatile i32, i32* @var                                             
  %v6 = load volatile i32, i32* @var                                             
  %v7 = load volatile i32, i32* @var                                             
  %v8 = load volatile i32, i32* @var                                             
  %v9 = load volatile i32, i32* @var                                             
  %v10 = load volatile i32, i32* @var                                            
  %v11 = load volatile i32, i32* @var                                            
  %v12 = load volatile i32, i32* @var                                            
  %v13 = load volatile i32, i32* @var                                            
                                                                                 
  store volatile i32 %v0, i32* %space                                            
                                                                                 
  ;; store values so they are used.                                              
  store volatile i32 %v0, i32* @var                                              
  store volatile i32 %v1, i32* @var                                              
  store volatile i32 %v2, i32* @var                                              
  store volatile i32 %v3, i32* @var                                              
  store volatile i32 %v4, i32* @var                                              
  store volatile i32 %v5, i32* @var                                              
  store volatile i32 %v6, i32* @var                                              
  store volatile i32 %v7, i32* @var                                              
  store volatile i32 %v8, i32* @var                                              
  store volatile i32 %v9, i32* @var                                              
  store volatile i32 %v10, i32* @var                                             
  store volatile i32 %v11, i32* @var                                             
  store volatile i32 %v12, i32* @var                                             
  store volatile i32 %v13, i32* @var                                             
  br label %foo                                                                  
                                                                                 
foo:                                                                             
  ret void                                                                       
}

Thanks!

[StephenFan]

Typo

[StephenFan]

Add test case.

[StephenFan]

Ping :)

[craig.topper]

llvm/lib/CodeGen/RegisterScavenging.cpp

376

Can this be done in the FoundTo path? Does this matter before we find To?

[StephenFan]

Do check in FoundTo path.

[StephenFan]

llvm/lib/CodeGen/RegisterScavenging.cpp

376

You are right. It doesn't matter before we find To.

[craig.topper]

LGTM

llvm/lib/CodeGen/RegisterScavenging.cpp

findSurvivorBackwards(const MachineRegisterInfo &MRI,
   LiveRegUnits Used(TRI);
 
   assert(From->getParent() == To->getParent() &&
          "Target instruction is in other than current basic block, use "
          "enterBasicBlockEnd first");
 
   for (MachineBasicBlock::iterator I = From;; --I) {
     const MachineInstr &MI = *I;
 
     Used.accumulate(MI);
 
     if (I == To) {
       // See if one of the registers in RC wasn't used so far.
       for (MCPhysReg Reg : AllocationOrder) {
         if (!MRI.isReserved(Reg) && Used.available(Reg) &&
             LiveOut.available(Reg))
           return std::make_pair(Reg, MBB.end());
       }
       // Otherwise we will continue up to InstrLimit instructions to find
       // the register which is not defined/used for the longest time.
       FoundTo = true;
       Pos = To;
       // Note: It was fine so far to start our search at From, however now that
       // we have to spill, and can only place the restore after From then
       // add the regs used/defed by std::next(From) to the set.
       if (RestoreAfter)
         Used.accumulate(*std::next(From));
     }
     if (FoundTo) {
+      // Don't search to FrameSetup instructions if we were searching from
+      // Non-FrameSetup instructions. Otherwise, the spill position may point
+      // before FrameSetup instructions.
+      if (!From->getFlag(MachineInstr::FrameSetup) &&
+          MI.getFlag(MachineInstr::FrameSetup))
+        break;
+
       if (Survivor == 0 || !Used.available(Survivor)) {
         MCPhysReg AvilableReg = 0;
         for (MCPhysReg Reg : AllocationOrder) {
           if (!MRI.isReserved(Reg) && Used.available(Reg)) {
             AvilableReg = Reg;
             break;
           }
         }

llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir

 # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 # REQUIRES: asserts
 # RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \
 # RUN:     -verify-machineinstrs %s | FileCheck %s
 #
 # RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \
 # RUN:     -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \
 # RUN:     | FileCheck --check-prefix=DEBUG %s
 #
 # DEBUG: Adjusting emergency spill slots!
 # DEBUG: Adjusting offset of emergency spill slot #4 from -4112 to -8192
 
+# FIXME: The code generated here is incorrect. It stores a0 to 0(sp) before
+# sub sp, sp, a0 but restores it after sub sp, sp, a0. We may need to implement
+# the target hook saveScavengerRegister to solve it.
+
 --- |
   ; ModuleID = 'reduced.ll'
   source_filename = "frame_layout-1253b1.cpp"
   target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
   target triple = "riscv64"
 
   ; Function Attrs: nounwind
   define weak_odr dso_local void @foo(i8* %ay) nounwind {
   ; CHECK-LABEL: foo:
   ; CHECK:       # %bb.0: # %entry
   ; CHECK-NEXT:    addi sp, sp, -2032
   ; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    addi s0, sp, 2032
+  ; CHECK-NEXT:    sd a0, 0(sp)
+  ; CHECK-NEXT:    lui a0, 2
+  ; CHECK-NEXT:    addiw a0, a0, -2032
+  ; CHECK-NEXT:    sub sp, sp, a0
+  ; CHECK-NEXT:    srli a0, sp, 12
+  ; CHECK-NEXT:    slli sp, a0, 12
+  ; CHECK-NEXT:    ld a0, 0(sp)
   ; CHECK-NEXT:    sd a1, 0(sp)
-  ; CHECK-NEXT:    lui a1, 2
-  ; CHECK-NEXT:    addiw a1, a1, -2032
-  ; CHECK-NEXT:    sub sp, sp, a1
-  ; CHECK-NEXT:    srli a1, sp, 12
-  ; CHECK-NEXT:    slli sp, a1, 12
   ; CHECK-NEXT:    lui a1, 1
   ; CHECK-NEXT:    addiw a1, a1, -8
   ; CHECK-NEXT:    add a1, sp, a1
   ; CHECK-NEXT:    sd a0, 0(a1)
   ; CHECK-NEXT:    ld a1, 0(sp)
   ; CHECK-NEXT:    call foo@plt
   ; CHECK-NEXT:    lui a0, 2
   ; CHECK-NEXT:    sub sp, s0, a0
bb.0.entry:
     ; This way when we replace the frame index %stack.1 with its actual address
     ; we have to allocate a virtual register to compute it.
     ; A later run of the the register scavenger won't find an available register
     ; either so it will have to spill one to the emergency spill slot.
     PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
     PseudoRET
 
 ...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# DEBUG: {{.*}}

llvm/test/CodeGen/RISCV/pr58286.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv32 < %s | FileCheck --check-prefix=RV32I %s
+@var = external global i32
+
+define void @func() {
+; RV64I-LABEL: func:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    sub sp, sp, a0
+; RV64I-NEXT:    .cfi_def_cfa_offset 4112
+; RV64I-NEXT:    lui a0, %hi(var)
+; RV64I-NEXT:    lw a1, %lo(var)(a0)
+; RV64I-NEXT:    lw a2, %lo(var)(a0)
+; RV64I-NEXT:    lw a3, %lo(var)(a0)
+; RV64I-NEXT:    lw a4, %lo(var)(a0)
+; RV64I-NEXT:    lw a5, %lo(var)(a0)
+; RV64I-NEXT:    lw a6, %lo(var)(a0)
+; RV64I-NEXT:    lw a7, %lo(var)(a0)
+; RV64I-NEXT:    lw t0, %lo(var)(a0)
+; RV64I-NEXT:    lw t1, %lo(var)(a0)
+; RV64I-NEXT:    lw t2, %lo(var)(a0)
+; RV64I-NEXT:    lw t3, %lo(var)(a0)
+; RV64I-NEXT:    lw t4, %lo(var)(a0)
+; RV64I-NEXT:    lw t5, %lo(var)(a0)
+; RV64I-NEXT:    lw t6, %lo(var)(a0)
+; RV64I-NEXT:    sd s0, 0(sp)
+; RV64I-NEXT:    lui s0, 1
+; RV64I-NEXT:    addiw s0, s0, 12
+; RV64I-NEXT:    add s0, sp, s0
+; RV64I-NEXT:    sw a1, 0(s0)
+; RV64I-NEXT:    ld s0, 0(sp)
+; RV64I-NEXT:    sw a1, %lo(var)(a0)
+; RV64I-NEXT:    sw a2, %lo(var)(a0)
+; RV64I-NEXT:    sw a3, %lo(var)(a0)
+; RV64I-NEXT:    sw a4, %lo(var)(a0)
+; RV64I-NEXT:    sw a5, %lo(var)(a0)
+; RV64I-NEXT:    sw a6, %lo(var)(a0)
+; RV64I-NEXT:    sw a7, %lo(var)(a0)
+; RV64I-NEXT:    sw t0, %lo(var)(a0)
+; RV64I-NEXT:    sw t1, %lo(var)(a0)
+; RV64I-NEXT:    sw t2, %lo(var)(a0)
+; RV64I-NEXT:    sw t3, %lo(var)(a0)
+; RV64I-NEXT:    sw t4, %lo(var)(a0)
+; RV64I-NEXT:    sw t5, %lo(var)(a0)
+; RV64I-NEXT:    sw t6, %lo(var)(a0)
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    add sp, sp, a0
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: func:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    sub sp, sp, a0
+; RV32I-NEXT:    .cfi_def_cfa_offset 4112
+; RV32I-NEXT:    lui a0, %hi(var)
+; RV32I-NEXT:    lw a1, %lo(var)(a0)
+; RV32I-NEXT:    lw a2, %lo(var)(a0)
+; RV32I-NEXT:    lw a3, %lo(var)(a0)
+; RV32I-NEXT:    lw a4, %lo(var)(a0)
+; RV32I-NEXT:    lw a5, %lo(var)(a0)
+; RV32I-NEXT:    lw a6, %lo(var)(a0)
+; RV32I-NEXT:    lw a7, %lo(var)(a0)
+; RV32I-NEXT:    lw t0, %lo(var)(a0)
+; RV32I-NEXT:    lw t1, %lo(var)(a0)
+; RV32I-NEXT:    lw t2, %lo(var)(a0)
+; RV32I-NEXT:    lw t3, %lo(var)(a0)
+; RV32I-NEXT:    lw t4, %lo(var)(a0)
+; RV32I-NEXT:    lw t5, %lo(var)(a0)
+; RV32I-NEXT:    lw t6, %lo(var)(a0)
+; RV32I-NEXT:    sw s0, 0(sp)
+; RV32I-NEXT:    lui s0, 1
+; RV32I-NEXT:    addi s0, s0, 12
+; RV32I-NEXT:    add s0, sp, s0
+; RV32I-NEXT:    sw a1, 0(s0)
+; RV32I-NEXT:    lw s0, 0(sp)
+; RV32I-NEXT:    sw a1, %lo(var)(a0)
+; RV32I-NEXT:    sw a2, %lo(var)(a0)
+; RV32I-NEXT:    sw a3, %lo(var)(a0)
+; RV32I-NEXT:    sw a4, %lo(var)(a0)
+; RV32I-NEXT:    sw a5, %lo(var)(a0)
+; RV32I-NEXT:    sw a6, %lo(var)(a0)
+; RV32I-NEXT:    sw a7, %lo(var)(a0)
+; RV32I-NEXT:    sw t0, %lo(var)(a0)
+; RV32I-NEXT:    sw t1, %lo(var)(a0)
+; RV32I-NEXT:    sw t2, %lo(var)(a0)
+; RV32I-NEXT:    sw t3, %lo(var)(a0)
+; RV32I-NEXT:    sw t4, %lo(var)(a0)
+; RV32I-NEXT:    sw t5, %lo(var)(a0)
+; RV32I-NEXT:    sw t6, %lo(var)(a0)
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    add sp, sp, a0
+; RV32I-NEXT:    ret
+  %space = alloca i32, align 4
+  %stackspace = alloca[1024 x i32], align 4
+
+  ;; Load values to increase register pressure.
+  %v0 = load volatile i32, i32* @var
+  %v1 = load volatile i32, i32* @var
+  %v2 = load volatile i32, i32* @var
+  %v3 = load volatile i32, i32* @var
+  %v4 = load volatile i32, i32* @var
+  %v5 = load volatile i32, i32* @var
+  %v6 = load volatile i32, i32* @var
+  %v7 = load volatile i32, i32* @var
+  %v8 = load volatile i32, i32* @var
+  %v9 = load volatile i32, i32* @var
+  %v10 = load volatile i32, i32* @var
+  %v11 = load volatile i32, i32* @var
+  %v12 = load volatile i32, i32* @var
+  %v13 = load volatile i32, i32* @var
+
+  store volatile i32 %v0, i32* %space
+
+  ;; store values so they are used.
+  store volatile i32 %v0, i32* @var
+  store volatile i32 %v1, i32* @var
+  store volatile i32 %v2, i32* @var
+  store volatile i32 %v3, i32* @var
+  store volatile i32 %v4, i32* @var
+  store volatile i32 %v5, i32* @var
+  store volatile i32 %v6, i32* @var
+  store volatile i32 %v7, i32* @var
+  store volatile i32 %v8, i32* @var
+  store volatile i32 %v9, i32* @var
+  store volatile i32 %v10, i32* @var
+  store volatile i32 %v11, i32* @var
+  store volatile i32 %v12, i32* @var
+  store volatile i32 %v13, i32* @var
+
+  ret void
+}
+
+define void @shrink_wrap(i1 %c) {
+; RV64I-LABEL: shrink_wrap:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    bnez a0, .LBB1_2
+; RV64I-NEXT:  # %bb.1: # %bar
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    sub sp, sp, a0
+; RV64I-NEXT:    .cfi_def_cfa_offset 4112
+; RV64I-NEXT:    lui a0, %hi(var)
+; RV64I-NEXT:    lw a1, %lo(var)(a0)
+; RV64I-NEXT:    lw a2, %lo(var)(a0)
+; RV64I-NEXT:    lw a3, %lo(var)(a0)
+; RV64I-NEXT:    lw a4, %lo(var)(a0)
+; RV64I-NEXT:    lw a5, %lo(var)(a0)
+; RV64I-NEXT:    lw a6, %lo(var)(a0)
+; RV64I-NEXT:    lw a7, %lo(var)(a0)
+; RV64I-NEXT:    lw t0, %lo(var)(a0)
+; RV64I-NEXT:    lw t1, %lo(var)(a0)
+; RV64I-NEXT:    lw t2, %lo(var)(a0)
+; RV64I-NEXT:    lw t3, %lo(var)(a0)
+; RV64I-NEXT:    lw t4, %lo(var)(a0)
+; RV64I-NEXT:    lw t5, %lo(var)(a0)
+; RV64I-NEXT:    lw t6, %lo(var)(a0)
+; RV64I-NEXT:    sd s0, 0(sp)
+; RV64I-NEXT:    lui s0, 1
+; RV64I-NEXT:    addiw s0, s0, 12
+; RV64I-NEXT:    add s0, sp, s0
+; RV64I-NEXT:    sw a1, 0(s0)
+; RV64I-NEXT:    ld s0, 0(sp)
+; RV64I-NEXT:    sw a1, %lo(var)(a0)
+; RV64I-NEXT:    sw a2, %lo(var)(a0)
+; RV64I-NEXT:    sw a3, %lo(var)(a0)
+; RV64I-NEXT:    sw a4, %lo(var)(a0)
+; RV64I-NEXT:    sw a5, %lo(var)(a0)
+; RV64I-NEXT:    sw a6, %lo(var)(a0)
+; RV64I-NEXT:    sw a7, %lo(var)(a0)
+; RV64I-NEXT:    sw t0, %lo(var)(a0)
+; RV64I-NEXT:    sw t1, %lo(var)(a0)
+; RV64I-NEXT:    sw t2, %lo(var)(a0)
+; RV64I-NEXT:    sw t3, %lo(var)(a0)
+; RV64I-NEXT:    sw t4, %lo(var)(a0)
+; RV64I-NEXT:    sw t5, %lo(var)(a0)
+; RV64I-NEXT:    sw t6, %lo(var)(a0)
+; RV64I-NEXT:    lui a0, 1
+; RV64I-NEXT:    addiw a0, a0, 16
+; RV64I-NEXT:    add sp, sp, a0
+; RV64I-NEXT:  .LBB1_2: # %foo
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: shrink_wrap:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    bnez a0, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %bar
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    sub sp, sp, a0
+; RV32I-NEXT:    .cfi_def_cfa_offset 4112
+; RV32I-NEXT:    lui a0, %hi(var)
+; RV32I-NEXT:    lw a1, %lo(var)(a0)
+; RV32I-NEXT:    lw a2, %lo(var)(a0)
+; RV32I-NEXT:    lw a3, %lo(var)(a0)
+; RV32I-NEXT:    lw a4, %lo(var)(a0)
+; RV32I-NEXT:    lw a5, %lo(var)(a0)
+; RV32I-NEXT:    lw a6, %lo(var)(a0)
+; RV32I-NEXT:    lw a7, %lo(var)(a0)
+; RV32I-NEXT:    lw t0, %lo(var)(a0)
+; RV32I-NEXT:    lw t1, %lo(var)(a0)
+; RV32I-NEXT:    lw t2, %lo(var)(a0)
+; RV32I-NEXT:    lw t3, %lo(var)(a0)
+; RV32I-NEXT:    lw t4, %lo(var)(a0)
+; RV32I-NEXT:    lw t5, %lo(var)(a0)
+; RV32I-NEXT:    lw t6, %lo(var)(a0)
+; RV32I-NEXT:    sw s0, 0(sp)
+; RV32I-NEXT:    lui s0, 1
+; RV32I-NEXT:    addi s0, s0, 12
+; RV32I-NEXT:    add s0, sp, s0
+; RV32I-NEXT:    sw a1, 0(s0)
+; RV32I-NEXT:    lw s0, 0(sp)
+; RV32I-NEXT:    sw a1, %lo(var)(a0)
+; RV32I-NEXT:    sw a2, %lo(var)(a0)
+; RV32I-NEXT:    sw a3, %lo(var)(a0)
+; RV32I-NEXT:    sw a4, %lo(var)(a0)
+; RV32I-NEXT:    sw a5, %lo(var)(a0)
+; RV32I-NEXT:    sw a6, %lo(var)(a0)
+; RV32I-NEXT:    sw a7, %lo(var)(a0)
+; RV32I-NEXT:    sw t0, %lo(var)(a0)
+; RV32I-NEXT:    sw t1, %lo(var)(a0)
+; RV32I-NEXT:    sw t2, %lo(var)(a0)
+; RV32I-NEXT:    sw t3, %lo(var)(a0)
+; RV32I-NEXT:    sw t4, %lo(var)(a0)
+; RV32I-NEXT:    sw t5, %lo(var)(a0)
+; RV32I-NEXT:    sw t6, %lo(var)(a0)
+; RV32I-NEXT:    lui a0, 1
+; RV32I-NEXT:    addi a0, a0, 16
+; RV32I-NEXT:    add sp, sp, a0
+; RV32I-NEXT:  .LBB1_2: # %foo
+; RV32I-NEXT:    ret
+  %space = alloca i32, align 4
+  %stackspace = alloca[1024 x i32], align 4
+  br i1 %c, label %foo, label %bar
+
+bar:
+
+  ;; Load values to increase register pressure.
+  %v0 = load volatile i32, i32* @var
+  %v1 = load volatile i32, i32* @var
+  %v2 = load volatile i32, i32* @var
+  %v3 = load volatile i32, i32* @var
+  %v4 = load volatile i32, i32* @var
+  %v5 = load volatile i32, i32* @var
+  %v6 = load volatile i32, i32* @var
+  %v7 = load volatile i32, i32* @var
+  %v8 = load volatile i32, i32* @var
+  %v9 = load volatile i32, i32* @var
+  %v10 = load volatile i32, i32* @var
+  %v11 = load volatile i32, i32* @var
+  %v12 = load volatile i32, i32* @var
+  %v13 = load volatile i32, i32* @var
+
+  store volatile i32 %v0, i32* %space
+
+  ;; store values so they are used.
+  store volatile i32 %v0, i32* @var
+  store volatile i32 %v1, i32* @var
+  store volatile i32 %v2, i32* @var
+  store volatile i32 %v3, i32* @var
+  store volatile i32 %v4, i32* @var
+  store volatile i32 %v5, i32* @var
+  store volatile i32 %v6, i32* @var
+  store volatile i32 %v7, i32* @var
+  store volatile i32 %v8, i32* @var
+  store volatile i32 %v9, i32* @var
+  store volatile i32 %v10, i32* @var
+  store volatile i32 %v11, i32* @var
+  store volatile i32 %v12, i32* @var
+  store volatile i32 %v13, i32* @var
+  br label %foo
+
+foo:
+  ret void
+}

llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

--- |
   ; CHECK-NEXT:    .cfi_def_cfa_offset 2032
   ; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    .cfi_offset ra, -8
   ; CHECK-NEXT:    .cfi_offset s0, -16
   ; CHECK-NEXT:    addi s0, sp, 2032
   ; CHECK-NEXT:    .cfi_def_cfa s0, 0
   ; CHECK-NEXT:    addi sp, sp, -272
   ; CHECK-NEXT:    sd a0, 8(sp)
   ; CHECK-NEXT:    csrr a0, vlenb
   ; CHECK-NEXT:    sd a1, 0(sp)
   ; CHECK-NEXT:    lui a1, 1
   ; CHECK-NEXT:    addiw a1, a1, -1024
   ; CHECK-NEXT:    mul a0, a0, a1
   ; CHECK-NEXT:    ld a1, 0(sp)
   ; CHECK-NEXT:    sub sp, sp, a0
+  ; CHECK-NEXT:    ld a0, 8(sp)
   ; CHECK-NEXT:    andi sp, sp, -128
+  ; CHECK-NEXT:    sd a0, 8(sp)
   ; CHECK-NEXT:    lui a0, 1
   ; CHECK-NEXT:    addiw a0, a0, -1808
   ; CHECK-NEXT:    add a0, sp, a0
   ; CHECK-NEXT:    vs1r.v v25, (a0) # Unknown-size Folded Spill
   ; CHECK-NEXT:    ld a0, 8(sp)
   ; CHECK-NEXT:    call spillslot@plt
   ; CHECK-NEXT:    addi sp, s0, -2048
   ; CHECK-NEXT:    addi sp, sp, -256