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Differential D134720

[RISCV][NFC] Add test for extractelt of vector types that should be split.
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Authored by jacquesguan on Sep 27 2022, 1:51 AM.

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reames
craig.topper
asb
luismarques
frasercrmck
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rG67bce07964da: [RISCV][NFC] Add test for extractelt of vector types that should be split.

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jacquesguan created this revision.Sep 27 2022, 1:51 AM
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jacquesguan requested review of this revision.Sep 27 2022, 1:51 AM
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Harbormaster completed remote builds in B188893: Diff 463152.Sep 27 2022, 3:14 AM
reames accepted this revision.Sep 27 2022, 7:21 AM

LGTM w/suggestion.

llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
603

Can you add a test for vscale x 16 - 1 as the index? (Or anything else guaranteed to land in the second lmul8 register after splitting.)

This revision is now accepted and ready to land.Sep 27 2022, 7:21 AM
jacquesguan updated this revision to Diff 463400.Sep 27 2022, 7:39 PM

address comment.

Harbormaster completed remote builds in B189070: Diff 463400.Sep 27 2022, 8:24 PM
frasercrmck retitled this revision from [RISCV][NFC] Add test for extractelt of vector types that should be splitted. to [RISCV][NFC] Add test for extractelt of vector types that should be split..Sep 27 2022, 10:31 PM
Closed by commit rG67bce07964da: [RISCV][NFC] Add test for extractelt of vector types that should be split. (authored by jacquesguan). · Explain WhySep 27 2022, 11:44 PM
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rG67bce07964da: [RISCV][NFC] Add test for extractelt of vector types that should be split..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
54 lines
42 lines
54 lines
54 lines

Diff 463152

llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

Show First 20 Lines • Show All 573 Lines • ▼ Show 20 Lines
; CHECK-NEXT: fdiv.s fa0, ft1, ft0 ; CHECK-NEXT: fdiv.s fa0, ft1, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0 %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%bo = fdiv <vscale x 4 x float> %x, %splat %bo = fdiv <vscale x 4 x float> %x, %splat
%ext = extractelement <vscale x 4 x float> %bo, i32 0 %ext = extractelement <vscale x 4 x float> %bo, i32 0
ret float %ext ret float %ext
} }
define double @extractelt_nxv16f64_0(<vscale x 16 x double> %v) {
; CHECK-LABEL: extractelt_nxv16f64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x double> %v, i32 0
ret double %r
}
define double @extractelt_nxv16f64_imm(<vscale x 16 x double> %v) {
; CHECK-LABEL: extractelt_nxv16f64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x double> %v, i32 2
ret double %r
}
reamesUnsubmitted
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Can you add a test for vscale x 16 - 1 as the index? (Or anything else guaranteed to land in the second lmul8 register after splitting.)

reames: Can you add a test for vscale x 16 - 1 as the index? (Or anything else guaranteed to land in…
define double @extractelt_nxv16f64_idx(<vscale x 16 x double> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv16f64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: bltu a0, a2, .LBB53_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB53_2:
; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a2, sp, 64
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: fld fa0, 0(a0)
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x double> %v, i32 %idx
ret double %r
}

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <vscale x 64 x i8>, <vscale x 64 x i8>* %x %a = load <vscale x 64 x i8>, <vscale x 64 x i8>* %x
%b = icmp eq <vscale x 64 x i8> %a, zeroinitializer %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer
%c = extractelement <vscale x 64 x i1> %b, i64 %idx %c = extractelement <vscale x 64 x i1> %b, i64 %idx
ret i1 %c ret i1 %c
} }
define i1 @extractelt_nxv128i1(<vscale x 128 x i8>* %x, i64 %idx) nounwind {
; CHECK-LABEL: extractelt_nxv128i1:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: bltu a1, a3, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 4
; CHECK-NEXT: sub sp, sp, a3
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi a3, sp, 64
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a4, a0, a2
; CHECK-NEXT: vl8r.v v16, (a4)
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: add a0, a3, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmseq.vi v8, v16, 0
; CHECK-NEXT: vmseq.vi v0, v24, 0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: vs8r.v v24, (a3)
; CHECK-NEXT: add a1, a3, a2
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: lb a0, 0(a0)
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%a = load <vscale x 128 x i8>, <vscale x 128 x i8>* %x
%b = icmp eq <vscale x 128 x i8> %a, zeroinitializer
%c = extractelement <vscale x 128 x i1> %b, i64 %idx
ret i1 %c
}

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

Show First 20 Lines • Show All 853 Lines • ▼ Show 20 Lines
; RV32M-NEXT: add a0, a0, a1 ; RV32M-NEXT: add a0, a0, a1
; RV32M-NEXT: ret ; RV32M-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sdiv <vscale x 4 x i32> %x, %splat %bo = sdiv <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 0 %ext = extractelement <vscale x 4 x i32> %bo, i32 0
ret i32 %ext ret i32 %ext
} }
define i32 @extractelt_nxv32i32_0(<vscale x 32 x i32> %v) {
; CHECK-LABEL: extractelt_nxv32i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e32, m8, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i32> %v, i32 0
ret i32 %r
}
define i32 @extractelt_nxv32i32_imm(<vscale x 32 x i32> %v) {
; CHECK-LABEL: extractelt_nxv32i32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i32> %v, i32 2
ret i32 %r
}
define i32 @extractelt_nxv32i32_idx(<vscale x 32 x i32> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv32i32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 2
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: bltu a0, a2, .LBB73_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB73_2:
; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a2, sp, 64
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: lw a0, 0(a0)
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i32> %v, i32 %idx
ret i32 %r
}

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

Show First 20 Lines • Show All 784 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%bo = sdiv <vscale x 4 x i32> %x, %splat %bo = sdiv <vscale x 4 x i32> %x, %splat
%ext = extractelement <vscale x 4 x i32> %bo, i32 0 %ext = extractelement <vscale x 4 x i32> %bo, i32 0
ret i32 %ext ret i32 %ext
} }
define i64 @extractelt_nxv16i64_0(<vscale x 16 x i64> %v) {
; CHECK-LABEL: extractelt_nxv16i64_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i64> %v, i32 0
ret i64 %r
}
define i64 @extractelt_nxv16i64_imm(<vscale x 16 x i64> %v) {
; CHECK-LABEL: extractelt_nxv16i64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i64> %v, i32 2
ret i64 %r
}
define i64 @extractelt_nxv16i64_idx(<vscale x 16 x i64> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv16i64_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: bltu a0, a2, .LBB73_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB73_2:
; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a2, sp, 64
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: ld a0, 0(a0)
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i64> %v, i32 %idx
ret i64 %r
}