[LegalizeTypes][RISCV] Support f16 in ExpandIntRes_LLROUND_LLRINT.

[craig.topper]

Summary

Promote f16 to f32 and use the f32 libcall.

I deleted rv64zfh-half-intrinsics-strict.ll because it only existed due to this issue breaking rv32.

[reames]

LGTM. I'm basically trusting this is valid by the float semantics, and am only reviewing the code change.

[craig.topper]

@reames I assume you chose Needs Revision in error?

[reames]

In D134579#3815733, @craig.topper wrote:

@reames I assume you chose Needs Revision in error?

Yep.

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
                                                    SDValue &Hi) {
   SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
   SplitInteger(Res, Lo, Hi);
 }
 
 void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
                                                    SDValue &Hi) {
-  SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
+  SDLoc dl(N);
+  bool IsStrict = N->isStrictFPOpcode();
+  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
+  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
 
   assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&
          "Input type needs to be promoted!");
 
   EVT VT = Op.getValueType();
 
+  if (VT == MVT::f16) {
+    VT = MVT::f32;
+    // Extend to f32.
+    if (IsStrict) {
+      Op = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, { VT, MVT::Other }, {Chain, Op});
+      Chain = Op.getValue(1);
+    } else {
+      Op = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op);
+    }
+  }
+
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
   if (N->getOpcode() == ISD::LLROUND ||
       N->getOpcode() == ISD::STRICT_LLROUND) {
     if (VT == MVT::f32)
       LC = RTLIB::LLROUND_F32;
     else if (VT == MVT::f64)
       LC = RTLIB::LLROUND_F64;
     else if (VT == MVT::f80)
if (N->getOpcode() == ISD::LLROUND ||
     else if (VT == MVT::f128)
       LC = RTLIB::LLRINT_F128;
     else if (VT == MVT::ppcf128)
       LC = RTLIB::LLRINT_PPCF128;
     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
   } else
     llvm_unreachable("Unexpected opcode!");
 
-  SDLoc dl(N);
   EVT RetVT = N->getValueType(0);
-  SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
 
   TargetLowering::MakeLibCallOptions CallOptions;
   CallOptions.setSExt(true);
   std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
                                                     Op, CallOptions, dl,
                                                     Chain);
   SplitInteger(Tmp.first, Lo, Hi);
 

llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics-strict.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv64 -mattr=+zfh \
-; RUN:   -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \
-; RUN:   | FileCheck -check-prefix=RV64IZFH %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+d \
-; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi lp64d \
-; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64IDZFH %s
-
-; These intrinsics require half and i64 to be legal types.
-
-declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata)
-
-define i64 @llrint_f16(half %a) nounwind strictfp {
-; RV64IZFH-LABEL: llrint_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.l.h a0, fa0
-; RV64IZFH-NEXT:    ret
-;
-; RV64IDZFH-LABEL: llrint_f16:
-; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0
-; RV64IDZFH-NEXT:    ret
-  %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
-  ret i64 %1
-}
-
-declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata)
-
-define i64 @llround_f16(half %a) nounwind strictfp {
-; RV64IZFH-LABEL: llround_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
-; RV64IZFH-NEXT:    ret
-;
-; RV64IDZFH-LABEL: llround_f16:
-; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rmm
-; RV64IDZFH-NEXT:    ret
-  %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
-  ret i64 %1
-}

llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll

 ;
 ; RV64IZFH-LABEL: lround_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
   %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret iXLen %1
 }
+
+declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata)
+
+define i64 @llrint_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: llrint_f16:
+; RV32IZFH:       # %bb.0:
+; RV32IZFH-NEXT:    addi sp, sp, -16
+; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT:    call llrintf@plt
+; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    addi sp, sp, 16
+; RV32IZFH-NEXT:    ret
+;
+; RV64IZFH-LABEL: llrint_f16:
+; RV64IZFH:       # %bb.0:
+; RV64IZFH-NEXT:    fcvt.l.h a0, fa0
+; RV64IZFH-NEXT:    ret
+  %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
+  ret i64 %1
+}
+
+declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata)
+
+define i64 @llround_f16(half %a) nounwind strictfp {
+; RV32IZFH-LABEL: llround_f16:
+; RV32IZFH:       # %bb.0:
+; RV32IZFH-NEXT:    addi sp, sp, -16
+; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
+; RV32IZFH-NEXT:    call llroundf@plt
+; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    addi sp, sp, 16
+; RV32IZFH-NEXT:    ret
+;
+; RV64IZFH-LABEL: llround_f16:
+; RV64IZFH:       # %bb.0:
+; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
+; RV64IZFH-NEXT:    ret
+  %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
+  ret i64 %1
+}