[LLDB] Enable non-trivial types in EmulateInstruction::Context

[DavidSpickett]

Summary

In future I want to extend RegisterInfo and that will likely be non trivial
types like string and vector. RegisterInfo gets stored in Context, so Context
must be changed to a discriminated enum that properly calls destructors.

(which would be std::variant but although llvm is using -std=c++17 I don't
think we can expect c++17 library features just yet)

As so much existing code does this:
Context ctx;
// Lots of code that interacts with ctx...
ctx.Set<...>

I wasn't able to switch to factory functions for the Set<...> methods without a lot
more changes. Instead I've made the default constructor construct to the NoArgs type
and then Set<...> will change the type later.

Whenever you call a Set<...> it will destroy whatever is currently in the union
before setting the new data. Potentially non trivial types like RegisterInfos here are
placement newed because otherwise operator= would try to destroy the existing data
which is in fact uninitialised memory as far as we're concerned.

For the destructor we switch on the current info_type to know what to destruct.
(info_type that was made private in a previous change, so we know we have control of it)

Some places in lldb were using memset to initalise RegisterInfos. I tracked these
down with GCC's -Wclass-memaccess.
https://gcc.gnu.org/onlinedocs/gcc/C_002b_002b-Dialect-Options.html#index-Wclass-memaccess

To replace these I've added sensible default values for each member in RegisterInfo
and filled kinds with LLDB_INVALID_REGNUM in the default constructor.

Depends on D134039

[DavidSpickett]

Note that this does not add any non trivial types but of course I did test it by adding some to RegisterInfo.

This work is early parts of https://discourse.llvm.org/t/rfc-showing-register-fields-in-lldb/64676.

lldb/source/Target/DynamicRegisterInfo.cpp

239

This being an instance where there is a now a sensible default constructor that is used instead.

[tschuett]

If I read your summary correctly, then std::variant would simplify your code. LLVM still uses llvm::optional. As there is no LLVM variant, I would go for std::variant .

[DavidSpickett]

As there is no LLVM variant, I would go for std::variant

I was under the impression that we can use 17 language features but not library features, yet. Let me check that what the minimum toolchains have.

[DavidSpickett]

Variant is supported from:
libstdc++ 7.1
VS 2017 15.0
libcxx 4.0

So far so good relative to https://llvm.org/docs/GettingStarted.html#host-c-toolchain-both-compiler-and-standard-library.

https://en.cppreference.com/w/cpp/compiler_support/17#C.2B.2B17_library_features claims it is in apple clang 10.0.0 so unfortunately we're not quite there as the minimum is 9.3.

[tschuett]

Sorry. I hoped that variant would make your life easier.

[labath]

I think the main reason that the RegisterInfo struct is such as it is, is because it wants to be trivially constructible (or whatever the c++ term for that is). I'm pretty sure that adding a std::string member will make it stop being that, and I don't think we suddenly want to run global constructors for all of the global RegisterInfo instances we have (and we have a lot of them).

If you wanted to preserve the existing patterns, the right way to store a string/array member inside a static struct would be to copy what is being done in the value_regs/invalidate_regs field, i.e., store the value itself in another static object, and then store the pointer to that object into RegisterInfo. For dynamic RegisterInfos (like those received from the lldb-server), you'd use DynamicRegisterInfo and DynamicRegisterInfo::Register, which have logic to persist/create storage for these values (that logic would have to be extended to handle the new fields as well).

That said I would *love* is someone changed the RegisterInfo structs into something saner, but I think that will need to be more elaborate than simply stuffing a std::vector member into it. I can give you my idea of how this could work, if you're interested in trying this out.

lldb/include/lldb/Core/EmulateInstruction.h

196

I actually think that the simplest solution here would be to store the RegisterInfos as pointers. Copying them around doesn't make sense, particularly if their size is about to grow.

342–345

I am not a C++ expert, but I have a strong suspicion that this is not correct. You're destroyed the whole object, but then are only recreating its individual submembers. I get that these are the only members which have non-trivial constructors, but I don't think that's how c++ works. I can confirm this with some c++ experts if you want, but I am pretty sure that you need to recreate the ContextUnion object as a whole here to avoid straying into UB territory.

lldb/include/lldb/lldb-private-types.h

67–77

Is this class still trivially constructible (not requiring dynamic initialization)?

[clayborg]

Looks fine to me as this is all NFC with a look toward the future. Only one questions about if we want to switch the EmulateInstruction::GetRegisterInfo to return an optional as well?

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

785–787

Do we want to switch this over to returning a llvm::Optional<RegisterInfo> as well in the base class?

[clayborg]

I do share the concern that Pavel has where currently RegisterInfo does not require global constructors, and it would be good to keep it this way. Right now RegisterInfo is POD which means if there is a global array of RegisterInfo structs, it gets written into a data section and there is no code that runs.

So I might recommend adding a RegisterInfo member that is a "Fields *fields" that can be easily set to NULL in POD initializers, but then stored in the dynamic register info class in its own vector and then have the RegisterInfo struct point to another POD definition of the Fields.

[DavidSpickett]

Sorry. I hoped that variant would make your life easier.

Np, one can dream (until the next out of reach c++ feature comes along).

[DavidSpickett]

I think the main reason that the RegisterInfo struct is such as it is, is because it wants to be trivially constructible (or whatever the c++ term for that is). I'm pretty sure that adding a std::string member will make it stop being that, and I don't think we suddenly want to run global constructors for all of the global RegisterInfo instances we have (and we have a lot of them).

Agreed. I think I stumbled into a solution for this for different reasons.

I might have mentioned adding a std::string somewhere in this review but I only did that as a way to test this patch actually would work.

If you wanted to preserve the existing patterns, the right way to store a string/array member inside a static struct would be to copy what is being done in the value_regs/invalidate_regs field, i.e., store the value itself in another static object, and then store the pointer to that object into RegisterInfo. > For dynamic RegisterInfos (like those received from the lldb-server), you'd use DynamicRegisterInfo and DynamicRegisterInfo::Register, which have logic to persist/create storage for these values (that logic would have to be extended to handle the new fields as well).

Agreed.

That said I would *love* is someone changed the RegisterInfo structs into something saner, but I think that will need to be more elaborate than simply stuffing a std::vector member into it. I can give you my idea of how this could work, if you're interested in trying this out.

Sure I'd be interested in that. I've just been hacking on this small part of it so I don't have the full picture yet.

So I might recommend adding a RegisterInfo member that is a "Fields *fields" that can be easily set to NULL in POD initializers, but then stored in the dynamic register info class in its own vector and then have the RegisterInfo struct point to another POD definition of the Fields.

I though along the same lines but a different reason, I didn't want to store empty <register flags type> in every register info that didn't have flags and balloon the total size.

So I have:

struct RegisterInfo {
<...>
  /// If not nullptr, a custom type defined by XML descriptions.
  /// Using shared_ptr here means that the majority of registers that don't have
  /// custom types do not have to waste sizeof(RegisterFlags) bytes.
  std::shared_ptr<RegisterFlags> flags_type = nullptr;

But shared_ptr still has a destructor. It could be RegisterFlags*, I just have to work out when all that data needs to be dealocated. Probably when the target itself destructs but I need to figure that out, in general i don't know yet where the best place for these flags/fields to live is.

If it is a plain pointer then this patch is redundant but hey I learned how to use placement new :)

[DavidSpickett]

lldb/include/lldb/Core/EmulateInstruction.h

196

True, but sounds like we're going toward adding a pointer to the info. So that should keep the size constant.

342–345

I will check the rules here, it's not too hard to change anyway and it would mean I don't forget one of the members.

lldb/include/lldb/lldb-private-types.h

67–77

Current state, no. Due to the constructor setting kinds. Which is my attempt to remove the memset that was used elsewhere to do this, which sort of implies it was never trivially constructable really. Unless you knew you weren't going to read certain fields.

Given that:

#define LLDB_INVALID_REGNUM UINT32_MAX

And the memsets all used 0. At the very least it's opaque what the state of RegisterInfo is supposed to be.

That said I looked again at kNumRegisterKinds and it only goes up to 5. So I could just write this as:

uint32_t kinds[lldb::kNumRegisterKinds] = {LLDB_INVALID_REGNUM ... };

To avoid all this (I think I mixed it up with another enum with 100s of members).

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

785–787

I will try this as a separate change, unconnected to this. In general any time we can change bool+ref to optional, I'll take it.

[labath]

In D134041#3805034, @DavidSpickett wrote:

That said I would *love* is someone changed the RegisterInfo structs into something saner, but I think that will need to be more elaborate than simply stuffing a std::vector member into it. I can give you my idea of how this could work, if you're interested in trying this out.

Sure I'd be interested in that. I've just been hacking on this small part of it so I don't have the full picture yet.

I think that part of the problem is that nobody has a full picture of how RegisterInfos work anymore. :)

I don't claim to have this fully thought out, but the idea goes roughly like this. For the past few years, we've been moving towards a world where LLDB is able to fill in lots of details about the target registers. I think we're now at a state where it is sufficient for the remote stub to specify the register name and number, and lldb will be able to fill on most of the details about that register: EH/DWARF/"generic" numbers, subregisters, etc. However, this code is only invoked when communicating remote stub -- not for core files.
On one hand, this kind of makes sense -- for core files, we are the source of the register info, so why wouldn't we provide the complete info straight away? However, it means that the information that "ah is a one byte sub-register of rax at offset 1" is repeated multiple times (we currently have three core file plugins, times the number of architectures they support). If we made core file register infos go through this "augmentation" process, then we could unify our core file/live process flow more, and relieve the core file plugins of the burden of dealing with the subregisters -- all they'd need to know is how to read/write whole registers, and the generic code would take care of all the subregisters.
This would also mean that *all* register infos being handled by generic code would be DynamicRegisterInfos, which means we could drop the avoid this POD business, and just replace that class with something modern and easy to use. The only place where we would need to store static arrays would be in the bowels of individual plugins, but these would be simpler than the current RegisterInfo struct, as a lot of this info would be deduced (maybe including the register type information that you're trying to introduce), and we might even have each plugin store the info in whichever format it sees fit -- the only requirement would be that a DynamicRegisterInfo comes out at the end. Some plugins may choose not to store static info at all, as we're already running into the limits of what can be stored statically -- if an architecture has multiple optional registers sets (whose presence is only known at runtime), then its impossible to stuff those registers into a static array -- I believe all our AArch64 registers are currently dynamic for this reason.

I know this is somewhat vague, but that's why this is just an idea. Someone would have to try it out to find all the issues and figure them out. I can try to help if you want to take it on.

lldb/include/lldb/Core/EmulateInstruction.h

196

It should, but regardless of that, I'm surprised to see the structs being stored here, I'm not aware of any other place which stores RegisterInfos be value.

[jasonmolenda]

In D134041#3805941, @labath wrote:

In D134041#3805034, @DavidSpickett wrote:

That said I would *love* is someone changed the RegisterInfo structs into something saner, but I think that will need to be more elaborate than simply stuffing a std::vector member into it. I can give you my idea of how this could work, if you're interested in trying this out.

Sure I'd be interested in that. I've just been hacking on this small part of it so I don't have the full picture yet.

I think that part of the problem is that nobody has a full picture of how RegisterInfos work anymore. :)

I don't claim to have this fully thought out, but the idea goes roughly like this. For the past few years, we've been moving towards a world where LLDB is able to fill in lots of details about the target registers. I think we're now at a state where it is sufficient for the remote stub to specify the register name and number, and lldb will be able to fill on most of the details about that register: EH/DWARF/"generic" numbers, subregisters, etc. However, this code is only invoked when communicating remote stub -- not for core files.
On one hand, this kind of makes sense -- for core files, we are the source of the register info, so why wouldn't we provide the complete info straight away?

An aside, I'm working with a group inside apple that has a JTAG style debugger that can access not only the normal general purpose registers/floating point/vector registers, but control registers like AArch64's MDSCR_EL1 as one example. I haven't figured out the best format for them to express this information in a Mach-O corefile yet, but I am thinking towards a Mach-O LC_NOTE where they embed an XML register description for all the registers they can provide (and it will require that size and maybe offset are explicitly specified, at least), and a register context buffer of bytes for all of the registers. lldb would need to augment its list of available registers with this. My vague memory is that they may have different registers available on each core ("thread") so we would need to do this on per-"thread" basis.

This is all vague hand-wavy at this point, but they have the information and the debugger users want this information. At some point I'll want the corefile to be able to augment or replace lldb's register information (probably augment).

[labath]

In D134041#3806994, @jasonmolenda wrote:

In D134041#3805941, @labath wrote:

In D134041#3805034, @DavidSpickett wrote:

That said I would *love* is someone changed the RegisterInfo structs into something saner, but I think that will need to be more elaborate than simply stuffing a std::vector member into it. I can give you my idea of how this could work, if you're interested in trying this out.

Sure I'd be interested in that. I've just been hacking on this small part of it so I don't have the full picture yet.

I think that part of the problem is that nobody has a full picture of how RegisterInfos work anymore. :)

I don't claim to have this fully thought out, but the idea goes roughly like this. For the past few years, we've been moving towards a world where LLDB is able to fill in lots of details about the target registers. I think we're now at a state where it is sufficient for the remote stub to specify the register name and number, and lldb will be able to fill on most of the details about that register: EH/DWARF/"generic" numbers, subregisters, etc. However, this code is only invoked when communicating remote stub -- not for core files.
On one hand, this kind of makes sense -- for core files, we are the source of the register info, so why wouldn't we provide the complete info straight away?

An aside, I'm working with a group inside apple that has a JTAG style debugger that can access not only the normal general purpose registers/floating point/vector registers, but control registers like AArch64's MDSCR_EL1 as one example. I haven't figured out the best format for them to express this information in a Mach-O corefile yet, but I am thinking towards a Mach-O LC_NOTE where they embed an XML register description for all the registers they can provide (and it will require that size and maybe offset are explicitly specified, at least), and a register context buffer of bytes for all of the registers. lldb would need to augment its list of available registers with this.

Thanks for jumping in Jason. I forgot about the size field. I think that we need that as well. As for the offset, how do the Mach-O core files work? Are all registers placed into a single note segment? (so that an "offset" is well-defined). In elf, the registers are scattered in multiple notes (roughly according to register sets), and we need to (arbitrarily) concatenate them so that a single offset value is meaningful. But what this really confirms to me that the notion of "static" register info lists is just not sufficient any more.

My vague memory is that they may have different registers available on each core ("thread") so we would need to do this on per-"thread" basis.

That's interesting, but I think we should actually be in a fairly good shape for that now, since in the case of ARM SVE, we can have each thread configure the scalable registers with a different size.

This is all vague hand-wavy at this point, but they have the information and the debugger users want this information. At some point I'll want the corefile to be able to augment or replace lldb's register information (probably augment).

Seems reasonable to me.

[clayborg]

In D134041#3811289, @labath wrote:

In D134041#3806994, @jasonmolenda wrote:

In D134041#3805941, @labath wrote:

In D134041#3805034, @DavidSpickett wrote:

That said I would *love* is someone changed the RegisterInfo structs into something saner, but I think that will need to be more elaborate than simply stuffing a std::vector member into it. I can give you my idea of how this could work, if you're interested in trying this out.

Sure I'd be interested in that. I've just been hacking on this small part of it so I don't have the full picture yet.

I think that part of the problem is that nobody has a full picture of how RegisterInfos work anymore. :)

I don't claim to have this fully thought out, but the idea goes roughly like this. For the past few years, we've been moving towards a world where LLDB is able to fill in lots of details about the target registers. I think we're now at a state where it is sufficient for the remote stub to specify the register name and number, and lldb will be able to fill on most of the details about that register: EH/DWARF/"generic" numbers, subregisters, etc. However, this code is only invoked when communicating remote stub -- not for core files.
On one hand, this kind of makes sense -- for core files, we are the source of the register info, so why wouldn't we provide the complete info straight away?

An aside, I'm working with a group inside apple that has a JTAG style debugger that can access not only the normal general purpose registers/floating point/vector registers, but control registers like AArch64's MDSCR_EL1 as one example. I haven't figured out the best format for them to express this information in a Mach-O corefile yet, but I am thinking towards a Mach-O LC_NOTE where they embed an XML register description for all the registers they can provide (and it will require that size and maybe offset are explicitly specified, at least), and a register context buffer of bytes for all of the registers. lldb would need to augment its list of available registers with this.

Thanks for jumping in Jason. I forgot about the size field. I think that we need that as well. As for the offset, how do the Mach-O core files work? Are all registers placed into a single note segment? (so that an "offset" is well-defined). In elf, the registers are scattered in multiple notes (roughly according to register sets), and we need to (arbitrarily) concatenate them so that a single offset value is meaningful. But what this really confirms to me that the notion of "static" register info lists is just not sufficient any more.

Mach-o core files have registers in load commands (LC_THREAD) I believe. Within this, there is a register set flavor enum (GPR, FPU, EXC, DBG, etc), and then all of the registers are expected to be understood by whomever loads them and are given as here are N bytes for GPR. So something like:

LC_THREAD , CMDSIZE
FLAVOR, COUNT, BYTES
FLAVOR, COUNT, BYTES
ZERO

A Zero for flavor terminates the register data for a thread.

My vague memory is that they may have different registers available on each core ("thread") so we would need to do this on per-"thread" basis.

That's interesting, but I think we should actually be in a fairly good shape for that now, since in the case of ARM SVE, we can have each thread configure the scalable registers with a different size.

This is all vague hand-wavy at this point, but they have the information and the debugger users want this information. At some point I'll want the corefile to be able to augment or replace lldb's register information (probably augment).

Seems reasonable to me.

Typical core files seem to mostly have register data hard coded and the consumers are supposed to know exactly what is in register data (ELF core, mach-o core and minidump). Anything that gets us closer to our lldb-server workflow where we dynamically can figure out what the registers are is a good thing.

[DavidSpickett]

https://reviews.llvm.org/D135015 landed using std::variant and no one has complained so far, so this whole patch is now irrelevant. If it comes back, I'll just use variant.

I agree that there are reasons to keep things POD so I am working on that basis with the goal of being able to process information sent to us by remote stubs.

Core files and information provided by lldb itself, I'm thinking about in the background so thanks for the use cases there.

lldb/include/lldb/Core/EmulateInstruction.h

 //===-- EmulateInstruction.h ------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
enum InfoType {
     eInfoTypeISAAndImmediate,
     eInfoTypeISAAndImmediateSigned,
     eInfoTypeISA,
     eInfoTypeNoArgs
   };
 
   struct Context {
     ContextType type = eContextInvalid;
+    InfoType GetInfoType() const { return info.info_type; }
 
+    struct ContextUnion {
     private:
-    enum InfoType info_type = eInfoTypeNoArgs;
+      InfoType info_type;
 
     public:
-    enum InfoType GetInfoType() const { return info_type; }
-    union {
-      struct RegisterPlusOffset {
+      ContextUnion() : info_type(eInfoTypeNoArgs) {}
+
+      struct RegisterPlusOffsetStruct {
         RegisterInfo reg;      // base register
         int64_t signed_offset; // signed offset added to base register
-      } RegisterPlusOffset;
+      };
 
-      struct RegisterPlusIndirectOffset {
+      struct RegisterPlusIndirectOffsetStruct {
         RegisterInfo base_reg;   // base register number
         RegisterInfo offset_reg; // offset register kind
-      } RegisterPlusIndirectOffset;
+      };
 
-      struct RegisterToRegisterPlusOffset {
+      struct RegisterToRegisterPlusOffsetStruct {
         RegisterInfo data_reg; // source/target register for data
         RegisterInfo base_reg; // base register for address calculation
         int64_t offset;        // offset for address calculation
-      } RegisterToRegisterPlusOffset;
+      };
 
-      struct RegisterToRegisterPlusIndirectOffset {
+      struct RegisterToRegisterPlusIndirectOffsetStruct {
         RegisterInfo base_reg;   // base register for address calculation
         RegisterInfo offset_reg; // offset register for address calculation
         RegisterInfo data_reg;   // source/target register for data
-      } RegisterToRegisterPlusIndirectOffset;
+      };
 
-      struct RegisterRegisterOperands {
+      struct RegisterRegisterOperandsStruct {
         RegisterInfo
             operand1; // register containing first operand for binary op
         RegisterInfo
             operand2; // register containing second operand for binary op
-      } RegisterRegisterOperands;
+      };
+
+      struct ISAAndImmediateStruct {
+        uint32_t isa;
+        uint32_t unsigned_data32; // immediate data
+      };
+
+      struct ISAAndImmediateSignedStruct {
+        uint32_t isa;
+        int32_t signed_data32; // signed immediate data
+      };
+
+      ~ContextUnion() {
+        switch (info_type) {
+        case eInfoTypeRegisterPlusOffset:
+          RegisterPlusOffset.~RegisterPlusOffsetStruct();
+          break;
+        case eInfoTypeRegisterPlusIndirectOffset:
+          RegisterPlusIndirectOffset.~RegisterPlusIndirectOffsetStruct();
+          break;
+        case eInfoTypeRegisterToRegisterPlusOffset:
+          RegisterToRegisterPlusOffset.~RegisterToRegisterPlusOffsetStruct();
+          break;
+        case eInfoTypeRegisterToRegisterPlusIndirectOffset:
+          RegisterToRegisterPlusIndirectOffset
+              .~RegisterToRegisterPlusIndirectOffsetStruct();
+          break;
+        case eInfoTypeRegisterRegisterOperands:
+          RegisterRegisterOperands.~RegisterRegisterOperandsStruct();
+          break;
+        case eInfoTypeRegister:
+          reg.~RegisterInfo();
+          break;
+        case eInfoTypeISAAndImmediate:
+          ISAAndImmediate.~ISAAndImmediateStruct();
+          break;
+        case eInfoTypeISAAndImmediateSigned:
+          ISAAndImmediateSigned.~ISAAndImmediateSignedStruct();
+          break;
+        // The following are PODs.
+        case eInfoTypeAddress:
+        case eInfoTypeImmediate:
+        case eInfoTypeImmediateSigned:
+        case eInfoTypeOffset:
+        case eInfoTypeISA:
+        case eInfoTypeNoArgs:
+          break;
+        }
+      }
 
+      union {
+        RegisterPlusOffsetStruct RegisterPlusOffset;
+        RegisterPlusIndirectOffsetStruct RegisterPlusIndirectOffset;
+        RegisterToRegisterPlusOffsetStruct RegisterToRegisterPlusOffset;
+        RegisterToRegisterPlusIndirectOffsetStruct
+            RegisterToRegisterPlusIndirectOffset;
+        RegisterRegisterOperandsStruct RegisterRegisterOperands;
         int64_t signed_offset; // signed offset by which to adjust self (for
                                // registers only)
-
-      RegisterInfo reg; // plain register
-
+        RegisterInfo reg;      // plain register
         uint64_t unsigned_immediate; // unsigned immediate value
         int64_t signed_immediate;    // signed immediate value
-
-      lldb::addr_t address; // direct address
-
-      struct ISAAndImmediate {
-        uint32_t isa;
-        uint32_t unsigned_data32; // immediate data
-      } ISAAndImmediate;
-
-      struct ISAAndImmediateSigned {
+        lldb::addr_t address;        // direct address
+        ISAAndImmediateStruct ISAAndImmediate;
+        ISAAndImmediateSignedStruct ISAAndImmediateSigned;
         uint32_t isa;
-        int32_t signed_data32; // signed immediate data
-      } ISAAndImmediateSigned;
+      };
 
-      uint32_t isa;
+      // So that Context can access info_type.
+      friend Context;
     } info;
 
     Context() = default;
 
+    // In these Set<type> functions, anything that is non-trivial must use
+    // placement new. This is because operator= will interpret whatever
+    // uninitialised memory is in the union as the content of the object and try
+    // to destroy it.
+
     void SetRegisterPlusOffset(RegisterInfo base_reg, int64_t signed_offset) {
-      info_type = eInfoTypeRegisterPlusOffset;
-      info.RegisterPlusOffset.reg = base_reg;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeRegisterPlusOffset;
+      new (&info.RegisterPlusOffset.reg) RegisterInfo(base_reg);
       info.RegisterPlusOffset.signed_offset = signed_offset;
     }
 
     void SetRegisterPlusIndirectOffset(RegisterInfo base_reg,
                                        RegisterInfo offset_reg) {
-      info_type = eInfoTypeRegisterPlusIndirectOffset;
-      info.RegisterPlusIndirectOffset.base_reg = base_reg;
-      info.RegisterPlusIndirectOffset.offset_reg = offset_reg;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeRegisterPlusIndirectOffset;
+      new (&info.RegisterPlusIndirectOffset.base_reg) RegisterInfo(base_reg);
+      new (&info.RegisterPlusIndirectOffset.offset_reg)
+          RegisterInfo(offset_reg);
     }
 
     void SetRegisterToRegisterPlusOffset(RegisterInfo data_reg,
                                          RegisterInfo base_reg,
                                          int64_t offset) {
-      info_type = eInfoTypeRegisterToRegisterPlusOffset;
-      info.RegisterToRegisterPlusOffset.data_reg = data_reg;
-      info.RegisterToRegisterPlusOffset.base_reg = base_reg;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeRegisterToRegisterPlusOffset;
+      new (&info.RegisterToRegisterPlusOffset.data_reg) RegisterInfo(data_reg);
+      new (&info.RegisterToRegisterPlusOffset.base_reg) RegisterInfo(base_reg);
       info.RegisterToRegisterPlusOffset.offset = offset;
     }
 
     void SetRegisterToRegisterPlusIndirectOffset(RegisterInfo base_reg,
                                                  RegisterInfo offset_reg,
                                                  RegisterInfo data_reg) {
-      info_type = eInfoTypeRegisterToRegisterPlusIndirectOffset;
-      info.RegisterToRegisterPlusIndirectOffset.base_reg = base_reg;
-      info.RegisterToRegisterPlusIndirectOffset.offset_reg = offset_reg;
-      info.RegisterToRegisterPlusIndirectOffset.data_reg = data_reg;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeRegisterToRegisterPlusIndirectOffset;
+      new (&info.RegisterToRegisterPlusIndirectOffset.base_reg)
+          RegisterInfo(base_reg);
+      new (&info.RegisterToRegisterPlusIndirectOffset.offset_reg)
+          RegisterInfo(offset_reg);
+      new (&info.RegisterToRegisterPlusIndirectOffset.data_reg)
+          RegisterInfo(data_reg);
     }
 
     void SetRegisterRegisterOperands(RegisterInfo op1_reg,
                                      RegisterInfo op2_reg) {
-      info_type = eInfoTypeRegisterRegisterOperands;
-      info.RegisterRegisterOperands.operand1 = op1_reg;
-      info.RegisterRegisterOperands.operand2 = op2_reg;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeRegisterRegisterOperands;
+      new (&info.RegisterRegisterOperands.operand1) RegisterInfo(op1_reg);
+      new (&info.RegisterRegisterOperands.operand2) RegisterInfo(op2_reg);
     }
 
     void SetOffset(int64_t signed_offset) {
-      info_type = eInfoTypeOffset;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeOffset;
       info.signed_offset = signed_offset;
     }
 
     void SetRegister(RegisterInfo reg) {
-      info_type = eInfoTypeRegister;
-      info.reg = reg;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeRegister;
+      new (&info.reg) RegisterInfo(reg);
     }
 
     void SetImmediate(uint64_t immediate) {
-      info_type = eInfoTypeImmediate;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeImmediate;
       info.unsigned_immediate = immediate;
     }
 
     void SetImmediateSigned(int64_t signed_immediate) {
-      info_type = eInfoTypeImmediateSigned;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeImmediateSigned;
       info.signed_immediate = signed_immediate;
     }
 
     void SetAddress(lldb::addr_t address) {
-      info_type = eInfoTypeAddress;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeAddress;
       info.address = address;
     }
+
     void SetISAAndImmediate(uint32_t isa, uint32_t data) {
-      info_type = eInfoTypeISAAndImmediate;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeISAAndImmediate;
       info.ISAAndImmediate.isa = isa;
       info.ISAAndImmediate.unsigned_data32 = data;
     }
 
     void SetISAAndImmediateSigned(uint32_t isa, int32_t data) {
-      info_type = eInfoTypeISAAndImmediateSigned;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeISAAndImmediateSigned;
       info.ISAAndImmediateSigned.isa = isa;
       info.ISAAndImmediateSigned.signed_data32 = data;
     }
 
     void SetISA(uint32_t isa) {
-      info_type = eInfoTypeISA;
+      info.~ContextUnion();
+      info.info_type = eInfoTypeISA;
       info.isa = isa;
     }
 
-    void SetNoArgs() { info_type = eInfoTypeNoArgs; }
+    void SetNoArgs() {
+      info.~ContextUnion();
+      info.info_type = eInfoTypeNoArgs;
+    }
 
     void Dump(Stream &s, EmulateInstruction *instruction) const;
   };
 
   typedef size_t (*ReadMemoryCallback)(EmulateInstruction *instruction,
                                        void *baton, const Context &context,
                                        lldb::addr_t addr, void *dst,
                                        size_t length);

lldb/include/lldb/lldb-private-types.h

 //===-- lldb-private-types.h ------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLDB_LLDB_PRIVATE_TYPES_H
 #define LLDB_LLDB_PRIVATE_TYPES_H
 
 #if defined(__cplusplus)
 
+#include "lldb/lldb-defines.h"
 #include "lldb/lldb-private.h"
 
 #include "llvm/ADT/ArrayRef.h"
 
+#include <array>
+
 namespace llvm {
 namespace sys {
 class DynamicLibrary;
 }
 }
 
 namespace lldb_private {
 class Platform;
 class ExecutionContext;
 
 typedef llvm::sys::DynamicLibrary (*LoadPluginCallbackType)(
     const lldb::DebuggerSP &debugger_sp, const FileSpec &spec, Status &error);
 
 /// Every register is described in detail including its name, alternate name
 /// (optional), encoding, size in bytes and the default display format.
 struct RegisterInfo {
   /// Name of this register, can't be NULL.
-  const char *name;
+  const char *name = nullptr;
   /// Alternate name of this register, can be NULL.
-  const char *alt_name;
+  const char *alt_name = nullptr;
   /// Size in bytes of the register.
-  uint32_t byte_size;
+  uint32_t byte_size = 0;
   /// The byte offset in the register context data where this register's
   /// value is found.
   /// This is optional, and can be 0 if a particular RegisterContext does not
   /// need to address its registers by byte offset.
-  uint32_t byte_offset;
+  uint32_t byte_offset = 0;
   /// Encoding of the register bits.
-  lldb::Encoding encoding;
+  lldb::Encoding encoding = lldb::eEncodingInvalid;
   /// Default display format.
-  lldb::Format format;
+  lldb::Format format = lldb::eFormatInvalid;
   /// Holds all of the various register numbers for all register kinds.
-  uint32_t kinds[lldb::kNumRegisterKinds]; //
+  std::array<uint32_t, lldb::kNumRegisterKinds> kinds;
   /// List of registers (terminated with LLDB_INVALID_REGNUM). If this value is
   /// not null, all registers in this list will be read first, at which point
   /// the value for this register will be valid. For example, the value list
   /// for ah would be eax (x86) or rax (x64). Register numbers are
   /// of eRegisterKindLLDB. If multiple registers are listed, the final
   /// value will be the concatenation of them.
-  uint32_t *value_regs;
+  uint32_t *value_regs = nullptr;
   /// List of registers (terminated with LLDB_INVALID_REGNUM). If this value is
   /// not null, all registers in this list will be invalidated when the value of
   /// this register changes. For example, the invalidate list for eax would be
   /// rax ax, ah, and al.
-  uint32_t *invalidate_regs;
+  uint32_t *invalidate_regs = nullptr;
+
+  RegisterInfo() { kinds.fill(LLDB_INVALID_REGNUM); }
+
+  RegisterInfo(const char *name, const char *alt_name, uint32_t byte_size,
+               uint32_t byte_offset, lldb::Encoding encoding,
+               lldb::Format format,
+               std::array<uint32_t, lldb::kNumRegisterKinds> kinds,
+               uint32_t *value_regs, uint32_t *invalidate_regs)
+      : name(name), alt_name(alt_name), byte_size(byte_size),
+        byte_offset(byte_offset), encoding(encoding), format(format),
+        kinds(kinds), value_regs(value_regs), invalidate_regs(invalidate_regs) {
+  }
 
   llvm::ArrayRef<uint8_t> data(const uint8_t *context_base) const {
     return llvm::ArrayRef<uint8_t>(context_base + byte_offset, byte_size);
   }
 
   llvm::MutableArrayRef<uint8_t> mutable_data(uint8_t *context_base) const {
     return llvm::MutableArrayRef<uint8_t>(context_base + byte_offset,
                                           byte_size);

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

 //===-- EmulateInstructionARM.cpp -----------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 #include "lldb/Utility/ArchSpec.h"
 #include "lldb/Utility/ConstString.h"
 #include "lldb/Utility/Stream.h"
 
 #include "Plugins/Process/Utility/ARMDefines.h"
 #include "Plugins/Process/Utility/ARMUtils.h"
 #include "Utility/ARM_DWARF_Registers.h"
 
+#include "llvm/ADT/Optional.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/MathExtras.h"
 
 using namespace lldb;
 using namespace lldb_private;
 
 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionARM, InstructionARM)
 
 // Convenient macro definitions.
 #define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
 #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
 
 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
 
 //
 // ITSession implementation
 //
 
-static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo &reg_info) {
-  ::memset(&reg_info, 0, sizeof(RegisterInfo));
-  ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
+static llvm::Optional<RegisterInfo> GetARMDWARFRegisterInfo(unsigned reg_num) {
+  RegisterInfo reg_info;
 
   if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
     reg_info.byte_size = 16;
     reg_info.format = eFormatVectorOfUInt8;
     reg_info.encoding = eEncodingVector;
   }
 
   if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
static llvm::Optional<RegisterInfo> GetARMDWARFRegisterInfo(unsigned reg_num) {
   case dwarf_q14:
     reg_info.name = "q14";
     break;
   case dwarf_q15:
     reg_info.name = "q15";
     break;
 
   default:
-    return false;
+    return llvm::None;
   }
-  return true;
+  return reg_info;
 }
 
 // A8.6.50
 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
 static uint32_t CountITSize(uint32_t ITMask) {
   // First count the trailing zeros of the IT mask.
   uint32_t TZ = llvm::countTrailingZeros(ITMask);
   if (TZ > 3) {
if (!success)
     return false;
 
   if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, data))
     return false;
 
   return true;
 }
 
 bool EmulateInstructionARM::GetRegisterInfo(lldb::RegisterKind reg_kind,
                                             uint32_t reg_num,
                                             RegisterInfo &reg_info) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_pc;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindDWARF;
case LLDB_REGNUM_GENERIC_FLAGS:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_cpsr;
       break;
     default:
       return false;
     }
   }
 
-  if (reg_kind == eRegisterKindDWARF)
-    return GetARMDWARFRegisterInfo(reg_num, reg_info);
+  if (reg_kind == eRegisterKindDWARF) {
+    llvm::Optional<RegisterInfo> info = GetARMDWARFRegisterInfo(reg_num);
+    if (info)
+      reg_info = *info;
+    return info.has_value();
+  }
+
   return false;
 }
 
 uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber() const {
   if (m_arch.GetTriple().isAndroid())
     return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
   bool is_apple = false;
   if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)

 }
 
 // Dispatches to either BXWritePC or BranchWritePC based on architecture
 // versions.
 bool EmulateInstructionARM::LoadWritePC(Context &context, uint32_t addr) {
   if (ArchVersion() >= ARMv5T)
     return BXWritePC(context, addr);
   else
-    return BranchWritePC((const Context)context, addr);
+    return BranchWritePC(context, addr);
 }
 
 // Dispatches to either BXWritePC or BranchWritePC based on architecture
 // versions and current instruction set.
 bool EmulateInstructionARM::ALUWritePC(Context &context, uint32_t addr) {
   if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM)
     return BXWritePC(context, addr);
   else
-    return BranchWritePC((const Context)context, addr);
+    return BranchWritePC(context, addr);
 }
 
 EmulateInstructionARM::Mode EmulateInstructionARM::CurrentInstrSet() {
   return m_opcode_mode;
 }
 
 // Set the 'T' bit of our CPSR.  The m_opcode_mode gets updated when the next
 // ReadInstruction() is performed.  This function has a side effect of updating

lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h

 //===-- EmulateInstructionMIPS.h ------------------------------------*- C++
 //-*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//

 }
 
 namespace lldb_private {
   class OptionValueDictionary;
 }
 
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/Utility/Status.h"
+#include "llvm/ADT/Optional.h"
 
 class EmulateInstructionMIPS : public lldb_private::EmulateInstruction {
 public:
   static void Initialize();
 
   static void Terminate();
 
   static llvm::StringRef GetPluginNameStatic() { return "mips32"; }
protected:
   bool Emulate_JALx(llvm::MCInst &insn);
 
   bool Emulate_JALRS(llvm::MCInst &insn);
 
   bool nonvolatile_reg_p(uint32_t regnum);
 
   const char *GetRegisterName(unsigned reg_num, bool alternate_name);
 
+  llvm::Optional<lldb_private::RegisterInfo>
+  GetMIPSDWARFRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num);
+
 private:
   std::unique_ptr<llvm::MCDisassembler> m_disasm;
   std::unique_ptr<llvm::MCDisassembler> m_alt_disasm;
   std::unique_ptr<llvm::MCSubtargetInfo> m_subtype_info;
   std::unique_ptr<llvm::MCSubtargetInfo> m_alt_subtype_info;
   std::unique_ptr<llvm::MCRegisterInfo> m_reg_info;
   std::unique_ptr<llvm::MCAsmInfo> m_asm_info;
   std::unique_ptr<llvm::MCContext> m_context;
   std::unique_ptr<llvm::MCInstrInfo> m_insn_info;
   uint32_t m_next_inst_size;
   bool m_use_alt_disaasm;
 };
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_MIPS_EMULATEINSTRUCTIONMIPS_H

lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

 //===-- EmulateInstructionMIPS.cpp ----------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
const char *EmulateInstructionMIPS::GetRegisterName(unsigned reg_num,
   case dwarf_mir_mips:
     return "mir";
   case dwarf_config5_mips:
     return "config5";
   }
   return nullptr;
 }
 
-bool EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,
-                                             uint32_t reg_num,
-                                             RegisterInfo &reg_info) {
-  if (reg_kind == eRegisterKindGeneric) {
-    switch (reg_num) {
-    case LLDB_REGNUM_GENERIC_PC:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_pc_mips;
-      break;
-    case LLDB_REGNUM_GENERIC_SP:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_sp_mips;
-      break;
-    case LLDB_REGNUM_GENERIC_FP:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_r30_mips;
-      break;
-    case LLDB_REGNUM_GENERIC_RA:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_ra_mips;
-      break;
-    case LLDB_REGNUM_GENERIC_FLAGS:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_sr_mips;
-      break;
-    default:
-      return false;
-    }
-  }
-
-  if (reg_kind == eRegisterKindDWARF) {
-    ::memset(&reg_info, 0, sizeof(RegisterInfo));
-    ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
+llvm::Optional<lldb_private::RegisterInfo>
+EmulateInstructionMIPS::GetMIPSDWARFRegisterInfo(RegisterKind reg_kind,
+                                                 uint32_t reg_num) {
+  RegisterInfo reg_info;
 
-    if (reg_num == dwarf_sr_mips || reg_num == dwarf_fcsr_mips ||
-        reg_num == dwarf_fir_mips || reg_num == dwarf_mcsr_mips ||
-        reg_num == dwarf_mir_mips || reg_num == dwarf_config5_mips) {
-      reg_info.byte_size = 4;
-      reg_info.format = eFormatHex;
-      reg_info.encoding = eEncodingUint;
-    } else if ((int)reg_num >= dwarf_zero_mips &&
-               (int)reg_num <= dwarf_f31_mips) {
-      reg_info.byte_size = 4;
-      reg_info.format = eFormatHex;
-      reg_info.encoding = eEncodingUint;
-    } else if ((int)reg_num >= dwarf_w0_mips &&
-               (int)reg_num <= dwarf_w31_mips) {
-      reg_info.byte_size = 16;
-      reg_info.format = eFormatVectorOfUInt8;
-      reg_info.encoding = eEncodingVector;
-    } else {
-      return false;
-    }
+  } else if ((int)reg_num >= dwarf_w0_mips && (int)reg_num <= dwarf_w31_mips) {
+    return llvm::None;
 
-    reg_info.name = GetRegisterName(reg_num, false);
-    reg_info.alt_name = GetRegisterName(reg_num, true);
-    reg_info.kinds[eRegisterKindDWARF] = reg_num;
 
-    switch (reg_num) {
-    case dwarf_r30_mips:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
-      break;
-    case dwarf_ra_mips:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
-      break;
-    case dwarf_sp_mips:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
-      break;
-    case dwarf_pc_mips:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
-      break;
-    case dwarf_sr_mips:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
-      break;
-    default:
-      break;
-    }
-    return true;
+  return reg_info;
+}
+
+bool EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,
+                                             uint32_t reg_num,
+                                             RegisterInfo &reg_info) {
+  if (reg_kind == eRegisterKindGeneric) {
+    switch (reg_num) {
+    case LLDB_REGNUM_GENERIC_PC:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_pc_mips;
+      break;
+    case LLDB_REGNUM_GENERIC_SP:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_sp_mips;
+      break;
+    case LLDB_REGNUM_GENERIC_FP:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_r30_mips;
+      break;
+    case LLDB_REGNUM_GENERIC_RA:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_ra_mips;
+      break;
+    case LLDB_REGNUM_GENERIC_FLAGS:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_sr_mips;
+      break;
+    default:
+      return false;
+    }
+  }
+
+  if (reg_kind == eRegisterKindDWARF) {
+    llvm::Optional<RegisterInfo> info =
+        GetMIPSDWARFRegisterInfo(reg_kind, reg_num);
+    if (info)
+      reg_info = *info;
+    return info.has_value();
   }
   return false;
 }
 
 EmulateInstructionMIPS::MipsOpcode *
 EmulateInstructionMIPS::GetOpcodeForInstruction(llvm::StringRef name) {
   static EmulateInstructionMIPS::MipsOpcode g_opcodes[] = {
       // Prologue/Epilogue instructions

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

 //===-- EmulateInstructionMIPS64.h ------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_MIPS64_EMULATEINSTRUCTIONMIPS64_H
 #define LLDB_SOURCE_PLUGINS_INSTRUCTION_MIPS64_EMULATEINSTRUCTIONMIPS64_H
 
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/Interpreter/OptionValue.h"
 #include "lldb/Utility/Status.h"
+#include "llvm/ADT/Optional.h"
 
 namespace llvm {
 class MCDisassembler;
 class MCSubtargetInfo;
 class MCRegisterInfo;
 class MCAsmInfo;
 class MCContext;
 class MCInstrInfo;
protected:
   bool Emulate_BZV(llvm::MCInst &insn);
 
   bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz);
 
   bool nonvolatile_reg_p(uint64_t regnum);
 
   const char *GetRegisterName(unsigned reg_num, bool alternate_name);
 
+  llvm::Optional<lldb_private::RegisterInfo>
+  GetMIPS64DWARFRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num);
+
 private:
   std::unique_ptr<llvm::MCDisassembler> m_disasm;
   std::unique_ptr<llvm::MCSubtargetInfo> m_subtype_info;
   std::unique_ptr<llvm::MCRegisterInfo> m_reg_info;
   std::unique_ptr<llvm::MCAsmInfo> m_asm_info;
   std::unique_ptr<llvm::MCContext> m_context;
   std::unique_ptr<llvm::MCInstrInfo> m_insn_info;
 };
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_MIPS64_EMULATEINSTRUCTIONMIPS64_H

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

 //===-- EmulateInstructionMIPS64.cpp --------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
const char *EmulateInstructionMIPS64::GetRegisterName(unsigned reg_num,
   case dwarf_mir_mips64:
     return "mir";
   case dwarf_config5_mips64:
     return "config5";
   }
   return nullptr;
 }
 
-bool EmulateInstructionMIPS64::GetRegisterInfo(RegisterKind reg_kind,
-                                               uint32_t reg_num,
-                                               RegisterInfo &reg_info) {
-  if (reg_kind == eRegisterKindGeneric) {
-    switch (reg_num) {
-    case LLDB_REGNUM_GENERIC_PC:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_pc_mips64;
-      break;
-    case LLDB_REGNUM_GENERIC_SP:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_sp_mips64;
-      break;
-    case LLDB_REGNUM_GENERIC_FP:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_r30_mips64;
-      break;
-    case LLDB_REGNUM_GENERIC_RA:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_ra_mips64;
-      break;
-    case LLDB_REGNUM_GENERIC_FLAGS:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = dwarf_sr_mips64;
-      break;
-    default:
-      return false;
-    }
-  }
-
-  if (reg_kind == eRegisterKindDWARF) {
-    ::memset(&reg_info, 0, sizeof(RegisterInfo));
-    ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
+llvm::Optional<lldb_private::RegisterInfo>
+EmulateInstructionMIPS64::GetMIPS64DWARFRegisterInfo(RegisterKind reg_kind,
+                                                     uint32_t reg_num) {
+  RegisterInfo reg_info;
 
-    if (reg_num == dwarf_sr_mips64 || reg_num == dwarf_fcsr_mips64 ||
-        reg_num == dwarf_fir_mips64 || reg_num == dwarf_mcsr_mips64 ||
-        reg_num == dwarf_mir_mips64 || reg_num == dwarf_config5_mips64) {
-      reg_info.byte_size = 4;
-      reg_info.format = eFormatHex;
-      reg_info.encoding = eEncodingUint;
-    } else if ((int)reg_num >= dwarf_zero_mips64 &&
-               (int)reg_num <= dwarf_f31_mips64) {
-      reg_info.byte_size = 8;
-      reg_info.format = eFormatHex;
-      reg_info.encoding = eEncodingUint;
-    } else if ((int)reg_num >= dwarf_w0_mips64 &&
-               (int)reg_num <= dwarf_w31_mips64) {
-      reg_info.byte_size = 16;
-      reg_info.format = eFormatVectorOfUInt8;
-      reg_info.encoding = eEncodingVector;
-    } else {
-      return false;
-    }
+    return llvm::None;
 
-    reg_info.name = GetRegisterName(reg_num, false);
-    reg_info.alt_name = GetRegisterName(reg_num, true);
-    reg_info.kinds[eRegisterKindDWARF] = reg_num;
 
-    switch (reg_num) {
-    case dwarf_r30_mips64:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
-      break;
-    case dwarf_ra_mips64:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
-      break;
-    case dwarf_sp_mips64:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
-      break;
-    case dwarf_pc_mips64:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
-      break;
-    case dwarf_sr_mips64:
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
-      break;
-    default:
-      break;
-    }
-    return true;
+
+  return reg_info;
+}
+
+bool EmulateInstructionMIPS64::GetRegisterInfo(RegisterKind reg_kind,
+                                               uint32_t reg_num,
+                                               RegisterInfo &reg_info) {
+  if (reg_kind == eRegisterKindGeneric) {
+    switch (reg_num) {
+    case LLDB_REGNUM_GENERIC_PC:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_pc_mips64;
+      break;
+    case LLDB_REGNUM_GENERIC_SP:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_sp_mips64;
+      break;
+    case LLDB_REGNUM_GENERIC_FP:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_r30_mips64;
+      break;
+    case LLDB_REGNUM_GENERIC_RA:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_ra_mips64;
+      break;
+    case LLDB_REGNUM_GENERIC_FLAGS:
+      reg_kind = eRegisterKindDWARF;
+      reg_num = dwarf_sr_mips64;
+      break;
+    default:
+      return false;
+    }
+  }
+
+  if (reg_kind == eRegisterKindDWARF) {
+    llvm::Optional<RegisterInfo> info =
+        GetMIPS64DWARFRegisterInfo(reg_kind, reg_num);
+    if (info)
+      reg_info = *info;
+    return info.has_value();
   }
   return false;
 }
 
 EmulateInstructionMIPS64::MipsOpcode *
 EmulateInstructionMIPS64::GetOpcodeForInstruction(llvm::StringRef op_name) {
   static EmulateInstructionMIPS64::MipsOpcode g_opcodes[] = {
       // Prologue/Epilogue instructions

lldb/source/Target/DynamicRegisterInfo.cpp

 //===-- DynamicRegisterInfo.cpp -------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
for (uint32_t i = 0; i < num_regs; ++i) {
     }
 
     // { 'name':'rcx'       , 'bitsize' :  64, 'offset' :  16,
     // 'encoding':'uint' , 'format':'hex'         , 'set': 0, 'ehframe' : 2,
     // 'dwarf' : 2, 'generic':'arg4', 'alt-name':'arg4', },
     RegisterInfo reg_info;
     std::vector<uint32_t> value_regs;
     std::vector<uint32_t> invalidate_regs;
-    memset(&reg_info, 0, sizeof(reg_info));
 
     ConstString name_val;
     ConstString alt_name_val;
     if (!reg_info_dict->GetValueForKeyAsString("name", name_val, nullptr)) {
       Clear();
       printf("error: registers must have valid names and offsets\n");
       reg_info_dict->DumpToStdout();
       return 0;