[RISCV] Verify VL operand on instructions if present

[reames]

Summary

These should only be immediate values or GPR registers.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

break;
           ErrInfo = "Invalid immediate";
           return false;
         }
       }
     }
   }
 
   const uint64_t TSFlags = Desc.TSFlags;
+  if (RISCVII::hasVLOp(TSFlags)) {
+    const MachineOperand &Op = MI.getOperand(RISCVII::getVLOpNum(Desc));
+    if (!Op.isImm() && !Op.isReg())  {
+      ErrInfo = "Invalid operand type for VL operand";
+      return false;
+    }
+    if (Op.isReg() && Op.getReg() != RISCV::NoRegister) {
+      const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+      auto *RC = MRI.getRegClass(Op.getReg());
+      if (!RISCV::GPRRegClass.hasSubClassEq(RC)) {
+        ErrInfo = "Invalid register class for VL operand";
+        return false;
+      }
+    }
+  }
   if (RISCVII::hasSEWOp(TSFlags)) {
     unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
     uint64_t Log2SEW = MI.getOperand(OpIdx).getImm();
     if (Log2SEW > 31) {
       ErrInfo = "Unexpected SEW value";
       return false;
     }
     unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;