[RISCV] Fix a silent miscompile in copyPhysReg

[reames]

Summary

Found this when adding verifier rules. The case which arises is that we have a DefMBBI which has a VecPolicy operand. The code was not expecting this, and the unconditional copy of the last two operands resulted in the SEW and VecPolicy fields being added to the VMV_V_V as AVL and SEW respectively.

Oddly, this appears to be a silent in practice. There's no test change despite verifier changes proving that we definitely hit this in existing tests.

[craig.topper]

LGTM

I don't think anything looks at the VL or SEW after register allocation which is when copyPhysReg is called. Which is probably why this doesn't affect anything in practice.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if (MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
           // $v8m1 = PseudoVWREDSUM_VS_M1 $v26, $v27
           // $v26 = COPY killed renamable $v8
           // After widening, The valid value will be 1 x e16 elements. If we
           // convert the COPY to vmv.v.v, it will only copy 1 x e8 elements.
           uint64_t TSFlags = MBBI->getDesc().TSFlags;
           if (RISCVII::isRVVWideningReduction(TSFlags))
             return false;
 
-          // Found the definition.
-          FoundDef = true;
-          DefMBBI = MBBI;
           // If the producing instruction does not depend on vsetvli, do not
           // convert COPY to vmv.v.v. For example, VL1R_V or PseudoVRELOAD.
-          if (!RISCVII::hasSEWOp(TSFlags))
+          if (!RISCVII::hasSEWOp(TSFlags) || !RISCVII::hasVLOp(TSFlags))
             return false;
+
+          // Found the definition.
+          FoundDef = true;
+          DefMBBI = MBBI;
           break;
         }
       }
     }
   }
 
   return false;
 }
if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
     LMul = RISCVII::LMUL_1;
   } else {
     llvm_unreachable("Impossible reg-to-reg copy");
   }
 
   if (IsScalableVector) {
     bool UseVMV_V_V = false;
     MachineBasicBlock::const_iterator DefMBBI;
-    unsigned DefExplicitOpNum;
     unsigned VIOpc;
     if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
       UseVMV_V_V = true;
-      DefExplicitOpNum = DefMBBI->getNumExplicitOperands();
       // We only need to handle LMUL = 1/2/4/8 here because we only define
       // vector register classes for LMUL = 1/2/4/8.
       switch (LMul) {
       default:
         llvm_unreachable("Impossible LMUL for vector register copy.");
       case RISCVII::LMUL_1:
         Opc = RISCV::PseudoVMV_V_V_M1;
         VIOpc = RISCV::PseudoVMV_V_I_M1;
if (IsScalableVector) {
 
     if (NF == 1) {
       auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
       if (UseVMV_V_I)
         MIB = MIB.add(DefMBBI->getOperand(1));
       else
         MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
       if (UseVMV_V_V) {
-        // The last two arguments of vector instructions are
-        // AVL, SEW. We also need to append the implicit-use vl and vtype.
-        MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 2)); // AVL
-        MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 1)); // SEW
+        const MCInstrDesc &Desc = DefMBBI->getDesc();
+        MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
+        MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
         MIB.addReg(RISCV::VL, RegState::Implicit);
         MIB.addReg(RISCV::VTYPE, RegState::Implicit);
       }
     } else {
       const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
       int I = 0, End = NF, Incr = 1;
       unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
if (NF == 1) {
         auto MIB = BuildMI(MBB, MBBI, DL, get(Opc),
                            TRI->getSubReg(DstReg, SubRegIdx + I));
         if (UseVMV_V_I)
           MIB = MIB.add(DefMBBI->getOperand(1));
         else
           MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
                            getKillRegState(KillSrc));
         if (UseVMV_V_V) {
-          MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 2)); // AVL
-          MIB.add(DefMBBI->getOperand(DefExplicitOpNum - 1)); // SEW
+          const MCInstrDesc &Desc = DefMBBI->getDesc();
+          MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
+          MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
           MIB.addReg(RISCV::VL, RegState::Implicit);
           MIB.addReg(RISCV::VTYPE, RegState::Implicit);
         }
       }
     }
   } else {
     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
         .addReg(SrcReg, getKillRegState(KillSrc))