[LLDB][RISCV] Add RVM and RVA instruction support for EmulateInstructionRISCV

[Emmmer]

Summary

Add:

• RVM and RVA instructions sets.
• corresponding unittests.

Further work:

• implement RVC, RVF, RVD, and RVV extension.

[DavidSpickett]

General comment on all this, and forgive me if this sounds outlandish but are we going to end up with a complete riscv emulator here? Given that until hardware single step arrives we're going to have to emulate any possible instruction that we might breakpoint. Or am I mistaken here?

If it is the case that we're going to end up with almost every instruction here, I don't necessarily object on a technical level. Without spec updates there is no alternative. However, I do think that it would be worth getting someone who works on riscv daily to review for instruction correctness. I've written emulators before and getting one instruction slightly off can be a nightmare to find after the fact.

Ideally you could run a whole pile of programs single stepped and verify their results but obviously that is easier said than done. Something like csmith can give you programs, but not ones with specific results. Might find some crashes though if you got some memory operands wrong somewhere. Anyway, just some ideas because I am concerned about how sustainable this effort is (and how much time it'll cost you to get right).

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

304

Can you make these a bit more obvious? Like:

// RV32I & RV64I (integer instructions)

Probably obvious if you live in riscv land but with the amount of single letter extensions it's hard to tell sometimes.

Also if this is a section marker, as opposed to marking this one function, make it more obvious like:

<empty line>
// RV32I & RV64I //
<empty line>

I don't see an llvm style suggestion for that but you get the idea. Otherwise the reader thinks it's attached to that one function.

383

Why do we need a special case here? Looks like the same thing with more steps. If it isn't please add a comment explaining what corner case this is catching.

776

In general prefer smaller patches. E.g. Adding all these MUL could be its own patch and you'd have less reason to leave yourself these markers.

TODOs in committed code tend to stay there forever.

793

Is this effected by the target's current FP mode?

831

Don't do this for this change, but I've seen so many of this pattern I'm sure you could reduce the boilerplate a bit.

struct RS1RS2Values {
  RegisterValue rs1;
  RegisterValue rs2;
  bool valid;
};
RS1RS2Values getRS1RS2(EmulateInstructionRISCV &emulator, uint32_t inst) {
  // decode both and read, set valid false on failure of either.
}
...
auto regvals = getRS1RS2(emulator, inst);
if (!regvals.valid)
  return false;

838

This is the dividend, right? You could use dividend directly to make that clear.

973

Please document the return value of this function. Given that 0 is a valid memory address (ok, in 99% of circumstances it'll fault but there is a mapping there of some form).

From what I see, 0 means that the address in reg was not suitable for doing an atomic access. And perhaps the instruction itself makes the assumption that 0 will never be used as an address, but it would be good to document that.

(given that address 0 is aligned to any size you want, if you want to be pedantic about it)

974

Can align be negative, is unsigned fine here?

983

You could oneline this:

return addr % align == 0 ? addr : 0;

1090

For this and the prior 2 please document which fields these masks are looking for and what their expected values are.

For example you might say I'm looking for op=4 rd=5, foo=1, whatever names your spec uses.

1095

For another change, but this should really be llvm::Optional<lldb::addr_t> ReadPC();. Your use here is fine given the existing API though.

1101

I assume +4 is a safe assumption for these "atomic sequences" ? As in, no one's gonna put compressed code in here and if they did, it wouldn't be a valid sequence.

Can you write a comment with some example assembly to show that? E.g.

// An atomic sequence must be of the form
// instr1 a b c
// instr2 d e f
// ....

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

90

Try using llvm::Optional<T> for this, it will save having to remember to make success false before calling the function.

And if you're not going to do that, at least make success a bool& (even if you need to take its address to pass down to ReadMemoryUnsigned).

91

Stray newline.

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

65

Do you expect to hit this in working, normal testing? If not there should be an assert.

77

Also assert here if this is an unexpected case.

[DavidSpickett]

Do riscv extensions come with any kind of assembly self test suites? If such a thing existed you could single step those as a way to test this sort of thing.

[jasonmolenda]

In D133670#3786329, @DavidSpickett wrote:

General comment on all this, and forgive me if this sounds outlandish but are we going to end up with a complete riscv emulator here? Given that until hardware single step arrives we're going to have to emulate any possible instruction that we might breakpoint. Or am I mistaken here?

fwiw we had to do this for the earliest iphones, where there were no hardware breakpoints and no instruction single step. We had a tiny engine that could calculate the address of the next instruction on those armv6 chips. It was pretty limited in what it needed to be able to do, but I guess extending the instruction emulation engine to support this use case is reasonable. It really only needs to emulate instructions well enough to track where registers are spilled to stack, saved in other registers, etc, for unwinding.

After one or two revisions, we got hardware breakpoints and were able to set a "stop when pc != current address" which was effectively single step. Then in ARMv8 AArch32/AArch64 gave us genuine instruction step and that's what we use now.

[jasonmolenda]

In D133670#3787225, @jasonmolenda wrote:

We had a tiny engine that could calculate the address of the next instruction on those armv6 chips. It was pretty limited in what it needed to be able to do, but I guess extending the instruction emulation engine to support this use case is reasonable. It really only needs to emulate instructions well enough to track where registers are spilled to stack, saved in other registers, etc, for unwinding.

That was poorly worded. The emulation engine right now only needs to track side effects relevant to unwind. It doesn't track control flow side effects of instructions, short of branches within a function where we "forward" the unwind state to the target instruction. The instruction emulation engine (today) runs over a function statically, and generates an intermediate representation of the unwind state at every instruction point.

What you'd need for instruction single step is a similar intermediate representation that expressed branch behavior for every branchable instruction. Does this instruction depend on a condition flag? Does it branch to an address in a register? That kind of thing.

Or you can do the approach debugserver took so many years ago, where we are stopped at a specific instruction, and we decode it well enough to know where it will execute next, no intermediate representation of those details.

All of this assuming David is correct, that this is the problem being looked at.

[jasonmolenda]

In D133670#3787249, @jasonmolenda wrote:

Or you can do the approach debugserver took so many years ago, where we are stopped at a specific instruction, and we decode it well enough to know where it will execute next, no intermediate representation of those details.

And thinking about it further, the whole point of emulating all of the instructions in a function is that we need the full sequence to generate accurate unwind records. If we're only interested in what the next instruction address will be, we need the current register context and know how to decode one instruction. It's a bit of a different problem.

[Emmmer]

In D133670#3787225, @jasonmolenda wrote:

fwiw we had to do this for the earliest iphones, where there were no hardware breakpoints and no instruction single step. We had a tiny engine that could calculate the address of the next instruction on those armv6 chips. It was pretty limited in what it needed to be able to do, but I guess extending the instruction emulation engine to support this use case is reasonable. It really only needs to emulate instructions well enough to track where registers are spilled to stack, saved in other registers, etc, for unwinding.

Yes, riscv does not currently implement hardware breakpoints or instruction single step.

Almost every instruction in riscv is able to read and write to registers (rs1, rs2, and rd), so for those developers who wish to control every register, it is necessary to simulate every instruction completely.

For example, after an instruction that changes a register, the program may use the JALR to jump to the address stored in that register.

In D133670#3786329, @DavidSpickett wrote:

Ideally you could run a whole pile of programs single stepped and verify their results but obviously that is easier said than done. Something like csmith can give you programs, but not ones with specific results. Might find some crashes though if you got some memory operands wrong somewhere. Anyway, just some ideas because I am concerned about how sustainable this effort is (and how much time it'll cost you to get right).

For now we have few method to test a program, the best way is using unittest to cover this emulator.

In D133670#3786346, @DavidSpickett wrote:

Do riscv extensions come with any kind of assembly self test suites? If such a thing existed you could single step those as a way to test this sort of thing.

Yes, we can try to use this test suite https://github.com/riscv-software-src/riscv-tests

[DavidSpickett]

Almost every instruction in riscv is able to read and write to registers (rs1, rs2, and rd), so for those developers who wish to control every register, it is necessary to simulate every instruction completely.

For example, after an instruction that changes a register, the program may use the JALR to jump to the address stored in that register.

So can most instructions write to the PC as one of the registers? I see that if you were on the following instruction, you'd have to emulate it to know the place it jumps to:

add pc, #4

On AArch64 the PC is often not allowed so if we were to emulate there, it cuts down the work needed a lot.

With the jalr isn't it more like:

add r1, #4
jalr r1

So we could (or do) put a breakpoint on the jalr because we know that the add doesn't do a branch itself. Once we hit the jalr we can read registers to get r1 and know where to break next.

Meaning for cases like that you only need a "can this branch" rather than working out the whole thing. Of course if almost any instruction can write to the pc, "can branch" is almost always true.

Yes, we can try to use this test suite https://github.com/riscv-software-src/riscv-tests

Cool! Well, I'm not requiring you to do that but keep it in mind if you end up spending a lot of time bug fixing this code.
(random idea: make lldb's emulation dump its state like the Arm emulation tests do, in a format that matches some existing riscv emulator, diff the two).

On the review side, @asb can you reccomend anyone who would be able to review the riscv specifics? (just because I remember you have done a lot of work on riscv)

(again not blocking this change on that, but I think it would be more sustainable going forward if there was a riscv specific reviewer too)

[jrtc27]

PC isn't exposed as a GPR on RISC-V, only explicit branch/jump instructions can alter control flow

[DavidSpickett]

PC isn't exposed as a GPR on RISC-V, only explicit branch/jump instructions can alter control flow

Thanks. In which case does that mean we only need to emulate instructions that would alter control flow? Perhaps that is technically true but not a good experience in practice.

I will put some time into reading exactly how lldb implements software single step but in the meantime maybe @jasonmolenda will know from experience.

[Emmmer]

address review comments.

[Emmmer]

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

793

No. It does not affect.

[DavidSpickett]

Mostly grumbling about optional from me :) Once that is addressed I think that'll be it.

For future patches please keep the number of added instructions small (many patches is fine, just keep each review manageable) and again, if you can find a riscv expert to review the specifics of the instructions that would be a massive help.

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

247–248

My point with the optional is that Optional<T> is equivalent to T and bool. So you're almost there.

I should have given an example, this is what I meant:

template <typename T>
static std::enable_if_t<std::is_integral_v<T>, llvm::Optional<T>>
ReadMem(EmulateInstructionRISCV &emulator, uint64_t addr) {
  // local success for the underlying API
  bool success = false;
  T result = 0;
  // call that function which sets success and value
  if (!success)
    return {}; // aka return false
  return value;
}

Which means you can call it like this:

llvm::Optional<uint64_t> value = ReadMem<uint64_T>(emulator, addr);
if (!value)
  return false;
// otherwise use *value

Which prevents you from doing this by accident:

bool success = false;
some_function(&success)
if (!success)
  return false;
// Oops forgot to reset success, sure hope some_function initialises it for me
some_function(&success);
if (!success)
  return false;

See what I mean? Granted, our functions probably set success whether they fail or not, but this way you encode it into the types and we aren't returning things by ref which requires the reader to go look at how the function uses that ref/pointer.

381

I'm still wondering why we need a special case here, though adding a comment that this also covers the pseudo instruction is
a good idea regardless.

if (imm == 1) {
  if (rs.rs1().trunc<uint64_t>() == 0)
    return WriteRegister(emulator, DecodeRD(inst),
                         RegisterValue(uint64_t(1)));
  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(uint64_t(0)));
}

• Assume imm is 1
• If rs1 is 0 then set rd to 1
• If rs1 is not 0 then set rd to 0

uint64_t result = rs.rs1().trunc<uint64_t>() < uint64_t(imm);
return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));

Same thing with this code:

• Assume imm is 1
• result = rs1 < 1
• if rs1 is 0 then set rd to 1
• if rs1 is not 0 then set rd to 0

Am I missing something? Seems like the same logic works for both and we can just use the second implemntation.

1053

Two things:

1. I mistook RegisterContextUnwind::ReadPC for this one, which is why I thought it was an existing API.
2. The point was that these two are equivalent from a types point of view:

lldb::addr_t ReadPC(bool *success);
llvm::Optional<lldb::addr_t> ReadPC();

Except that the second is easier to handle (feel free to disagree, I am big optional enthusiast so I am biased here) and is more obvious when you read code that calls that function. In that you don't have to read the function, the type tells you everything you need to know.

Also, if you're gonna have a function that returns by pointer, but never checks that that pointer is null, just make it a ref. ReadPC(bool &success). If some underlying function N levels down insists on taking a pointer, keep it as a ref for as long as possible before converting it.

This is not a comment on your choice here by the way, lldb has a lot, a lot, of this pattern that I want to replace as new code gets added. So I appreciate you sticking with the local style but in this case there's reason to modernise.

1154

These comments are exactly what I wanted, thanks.

1201

sigle -> single and add a full stop on the end of the sentence.

[Emmmer]

address review comments.

[Emmmer]

In D133670#3791733, @DavidSpickett wrote:

For future patches please keep the number of added instructions small (many patches is fine, just keep each review manageable) and again, if you can find a riscv expert to review the specifics of the instructions that would be a massive help.

Sorry for the inconvenience, I will pay attention to the size of the patch next time.

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

381

Sorry, seems I mistook the example given by the spec as a special case because they use "NOTE".

1053

I just tried llvm::Optional, but it didn't reduce the number of null-checks, and we use Optional for that purpose (by chaining them with .map or .flatMap).

At the moment it seems to be missing some handy ADT functions like and_then : Optional<T> -> (T -> Optional<U>) -> Optional<U>, I can add them to llvm::Optional in the next patch together with some modernization.

BTW, The emulation API uses mostly bool &success to return the result, It is sure a huge refactoring.

[Emmmer]

change ReadPC(bool *success) -> ReadPC(bool &success)

[DavidSpickett]

One idea I had to help review future patches, if the authors of the llvm support for the extension are still active you could add them as reviewers. I'm happy to continue reviewing of course, just aware that I'm not doing the most in depth job here.

This change LGTM.

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

1053

The point is not that optional reduces checks for false, but it reduces the number of ways you can screw that up and encodes the intent in the types more accurately. You're not wrong that it isn't as nice as say rust's foo()?.bar() and the like, but it's better than returning a bool by ref and forgetting to reset it each time.

Yes refactoring the emulation API is a big job that will likely never happen, which is why writing new code in a better style is the way to go about it.

But hey, let's not let style get in the way of the point here which is to improve riscv support, and leave things as they are.

I'll get off my soapbox and maybe I'll implement what I'm talking about at some point in the future :)

[aprantl]

Hey @Emmmer the unit test is throwing a UBSAN failure, could you please take a look?

https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake-sanitized/lastFailedBuild/testReport/lldb-unit/Instruction___EmulatorTests_3/26/

Stacktrace
Script(shard):
--
GTEST_OUTPUT=json:/Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/lldb-build/tools/lldb/unittests/Instruction/./EmulatorTests-lldb-unit-48390-3-26.json GTEST_SHUFFLE=1 GTEST_TOTAL_SHARDS=26 GTEST_SHARD_INDEX=3 /Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/lldb-build/tools/lldb/unittests/Instruction/./EmulatorTests
--

Note: This is test shard 4 of 26.
Note: Randomizing tests' orders with a seed of 42603 .
[==========] Running 1 test from 1 test suite.
[----------] Global test environment set-up.
[----------] 1 test from RISCVEmulatorTester
[ RUN      ] RISCVEmulatorTester.TestAtomicSequence
/Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/llvm-project/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp:254:3: runtime error: store to misaligned address 0x61b000001034 for type 'uint64_t' (aka 'unsigned long long'), which requires 8 byte alignment
0x61b000001034: note: pointer points here
  af 27 04 10 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
              ^ 
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior /Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/llvm-project/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp:254:3 in 

--
exit: -6
--
shard JSON output does not exist: /Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/lldb-build/tools/lldb/unittests/Instruction/./EmulatorTests-lldb-unit-48390-3-26.json

[Emmmer]

In D133670#3804437, @aprantl wrote:

Hey @Emmmer the unit test is throwing a UBSAN failure, could you please take a look?

https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake-sanitized/lastFailedBuild/testReport/lldb-unit/Instruction___EmulatorTests_3/26/

Stacktrace
Script(shard):
--
GTEST_OUTPUT=json:/Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/lldb-build/tools/lldb/unittests/Instruction/./EmulatorTests-lldb-unit-48390-3-26.json GTEST_SHUFFLE=1 GTEST_TOTAL_SHARDS=26 GTEST_SHARD_INDEX=3 /Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/lldb-build/tools/lldb/unittests/Instruction/./EmulatorTests
--

Note: This is test shard 4 of 26.
Note: Randomizing tests' orders with a seed of 42603 .
[==========] Running 1 test from 1 test suite.
[----------] Global test environment set-up.
[----------] 1 test from RISCVEmulatorTester
[ RUN      ] RISCVEmulatorTester.TestAtomicSequence
/Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/llvm-project/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp:254:3: runtime error: store to misaligned address 0x61b000001034 for type 'uint64_t' (aka 'unsigned long long'), which requires 8 byte alignment
0x61b000001034: note: pointer points here
  af 27 04 10 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
              ^ 
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior /Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/llvm-project/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp:254:3 in 

--
exit: -6
--
shard JSON output does not exist: /Users/buildslave/jenkins/workspace/lldb-cmake-sanitized/lldb-build/tools/lldb/unittests/Instruction/./EmulatorTests-lldb-unit-48390-3-26.json

Thanks for your feedback! it was fixed in rG07d0ef306b74fbcede432ad3480d2f299c051a98

[aprantl]

Awesome, bot is green again!

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

 //===-- EmulateInstructionRISCV.h -----------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
 #define LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
 
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/Interpreter/OptionValue.h"
 #include "lldb/Utility/Log.h"
+#include "lldb/Utility/RegisterValue.h"
 #include "lldb/Utility/Status.h"
 
 namespace lldb_private {
 
 constexpr uint32_t DecodeRD(uint32_t inst) { return (inst & 0xF80) >> 7; }
 constexpr uint32_t DecodeRS1(uint32_t inst) { return (inst & 0xF8000) >> 15; }
 constexpr uint32_t DecodeRS2(uint32_t inst) { return (inst & 0x1F00000) >> 20; }
 
public:
   bool SetTargetTriple(const ArchSpec &arch) override;
   bool ReadInstruction() override;
   bool EvaluateInstruction(uint32_t options) override;
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
   bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
                        RegisterInfo &reg_info) override;
 
-  lldb::addr_t ReadPC(bool *success);
+  lldb::addr_t ReadPC(bool &success);
   bool WritePC(lldb::addr_t pc);
 
   const InstrPattern *Decode(uint32_t inst);
   bool DecodeAndExecute(uint32_t inst, bool ignore_cond);
+
+  template <typename T>
+  static std::enable_if_t<std::is_integral_v<T>, T>
+  ReadMem(EmulateInstructionRISCV &emulator, uint64_t addr, bool *success) {
+
+    EmulateInstructionRISCV::Context ctx;
+    ctx.type = EmulateInstruction::eContextRegisterLoad;
+    ctx.SetNoArgs();
+    return T(emulator.ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), success));
+  }
+
+  template <typename T>
+  static bool WriteMem(EmulateInstructionRISCV &emulator, uint64_t addr,
+                       RegisterValue value) {
+    EmulateInstructionRISCV::Context ctx;
+    ctx.type = EmulateInstruction::eContextRegisterStore;
+    ctx.SetNoArgs();
+    return emulator.WriteMemoryUnsigned(ctx, addr, value.GetAsUInt64(),
+                                        sizeof(T));
+  }
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

 
 #include "lldb/Core/Address.h"
 #include "lldb/Core/PluginManager.h"
 #include "lldb/Interpreter/OptionValueArray.h"
 #include "lldb/Interpreter/OptionValueDictionary.h"
 #include "lldb/Symbol/UnwindPlan.h"
 #include "lldb/Utility/ArchSpec.h"
 #include "lldb/Utility/LLDBLog.h"
-#include "lldb/Utility/RegisterValue.h"
 #include "lldb/Utility/Stream.h"
 
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/MathExtras.h"
 
 using namespace lldb;
 using namespace lldb_private;
 
static bool WriteRegister(EmulateInstructionRISCV &emulator,
   ctx.type = EmulateInstruction::eContextRegisterStore;
   ctx.SetNoArgs();
   return emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg, value);
 }
 
 static bool ExecJAL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   bool success = false;
   int64_t offset = SignExt(DecodeJImm(inst));
-  int64_t pc = emulator.ReadPC(&success);
+  int64_t pc = emulator.ReadPC(success);
   return success && emulator.WritePC(pc + offset) &&
          WriteRegister(emulator, DecodeRD(inst),
                        RegisterValue(uint64_t(pc + 4)));
 }
 
 static bool ExecJALR(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   int64_t offset = SignExt(DecodeIImm(inst));
   RegisterValue value;
   if (!ReadRegister(emulator, DecodeRS1(inst), value))
     return false;
   bool success = false;
-  int64_t pc = emulator.ReadPC(&success);
+  int64_t pc = emulator.ReadPC(success);
   int64_t rs1 = int64_t(value.GetAsUInt64());
   // JALR clears the bottom bit. According to riscv-spec:
   // "The JALR instruction now clears the lowest bit of the calculated target
   // address, to simplify hardware and to allow auxiliary information to be
   // stored in function pointers."
   return emulator.WritePC((rs1 + offset) & ~1) &&
          WriteRegister(emulator, DecodeRD(inst),
                        RegisterValue(uint64_t(pc + 4)));
case BLTU:
     return rs1 < rs2;
   case BGEU:
     return rs1 >= rs2;
   default:
     llvm_unreachable("unexpected funct3");
   }
 }
 
+struct Wrapped {
+  RegisterValue value;
+
+  template <typename T>
+  [[nodiscard]] std::enable_if_t<std::is_unsigned_v<T>, T> trunc() const {
+    return T(value.GetAsUInt64());
+  }
+
+  template <typename T> T sext() const = delete;
+};
+
+template <> int32_t Wrapped::sext<int32_t>() const {
+  return int32_t(trunc<uint32_t>());
+}
+
+template <> int64_t Wrapped::sext<int64_t>() const {
+  return int64_t(trunc<uint64_t>());
+}
+
+template <bool hasRS2> struct RSRegs {
+private:
+  Wrapped rs1_value;
+
+public:
+  bool valid;
+
+  Wrapped &rs1() { return rs1_value; }
+};
+
+template <> struct RSRegs<true> : RSRegs<false> {
+private:
+  Wrapped rs2_value;
+
+public:
+  Wrapped &rs2() { return rs2_value; }
+};
+
+RSRegs<true> readRS1RS2(EmulateInstructionRISCV &emulator, uint32_t inst) {
+  RSRegs<true> value{};
+  value.valid = ReadRegister(emulator, DecodeRS1(inst), value.rs1().value) &&
+                ReadRegister(emulator, DecodeRS2(inst), value.rs2().value);
+  return value;
+}
+
+RSRegs<false> readRS1(EmulateInstructionRISCV &emulator, uint32_t inst) {
+  RSRegs<false> value{};
+  value.valid = ReadRegister(emulator, DecodeRS1(inst), value.rs1().value);
+  return value;
+}
+
 static bool ExecB(EmulateInstructionRISCV &emulator, uint32_t inst,
                   bool ignore_cond) {
   bool success = false;
-  uint64_t pc = emulator.ReadPC(&success);
+  uint64_t pc = emulator.ReadPC(success);
   if (!success)
     return false;
 
   uint64_t offset = SignExt(DecodeBImm(inst));
   uint64_t target = pc + offset;
   if (ignore_cond)
     return emulator.WritePC(target);
 
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, DecodeRS1(inst), value1) ||
-      !ReadRegister(emulator, DecodeRS2(inst), value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
   uint32_t funct3 = DecodeFunct3(inst);
-  if (CompareB(value1.GetAsUInt64(), value2.GetAsUInt64(), funct3))
+  if (CompareB(rs.rs1().trunc<uint64_t>(), rs.rs2().trunc<uint64_t>(), funct3))
     return emulator.WritePC(target);
 
   return true;
 }
 
 static bool ExecLUI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   uint32_t imm = DecodeUImm(inst);
   RegisterValue value;
   value.SetUInt64(SignExt(imm));
   return WriteRegister(emulator, DecodeRD(inst), value);
 }
 
 static bool ExecAUIPC(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   uint32_t imm = DecodeUImm(inst);
   RegisterValue value;
   bool success = false;
-  value.SetUInt64(SignExt(imm) + emulator.ReadPC(&success));
+  value.SetUInt64(SignExt(imm) + emulator.ReadPC(success));
   return success && WriteRegister(emulator, DecodeRD(inst), value);
 }
 
 template <typename T>
-static std::enable_if_t<std::is_integral_v<T>, T>
-ReadMem(EmulateInstructionRISCV &emulator, uint64_t addr, bool *success) {
-
+static std::enable_if_t<std::is_integral_v<T>, llvm::Optional<T>>
+ReadMem(EmulateInstructionRISCV &emulator, uint64_t addr) {
   EmulateInstructionRISCV::Context ctx;
   ctx.type = EmulateInstruction::eContextRegisterLoad;
   ctx.SetNoArgs();
-  return T(emulator.ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), success));
+  bool success = false;
+  T result = emulator.ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), &success);
+  if (!success)
+    return {}; // aka return false
+  return result;
 }
 
 template <typename T>
 static bool WriteMem(EmulateInstructionRISCV &emulator, uint64_t addr,
                      RegisterValue value) {
   EmulateInstructionRISCV::Context ctx;
   ctx.type = EmulateInstruction::eContextRegisterStore;
   ctx.SetNoArgs();
   return emulator.WriteMemoryUnsigned(ctx, addr, value.GetAsUInt64(),
                                       sizeof(T));
 }
 
 static uint64_t LoadStoreAddr(EmulateInstructionRISCV &emulator,
                               uint32_t inst) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeSImm(inst));
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return LLDB_INVALID_ADDRESS;
-  uint64_t addr = value.GetAsUInt64() + uint64_t(imm);
+  uint64_t addr = rs.rs1().trunc<uint64_t>() + uint64_t(imm);
   return addr;
 }
 
 // Read T from memory, then load its sign-extended value E to register.
 template <typename T, typename E>
 static bool Load(EmulateInstructionRISCV &emulator, uint32_t inst,
                  uint64_t (*extend)(E)) {
   uint64_t addr = LoadStoreAddr(emulator, inst);
   if (addr == LLDB_INVALID_ADDRESS)
     return false;
-  bool success = false;
-  E value = E(ReadMem<T>(emulator, addr, &success));
-  if (!success)
+  E value = E(ReadMem<T>(emulator, addr).value());
+  if (!value)
     return false;
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(extend(value)));
 }
 
 template <typename T>
 static bool Store(EmulateInstructionRISCV &emulator, uint32_t inst) {
   uint64_t addr = LoadStoreAddr(emulator, inst);
   if (addr == LLDB_INVALID_ADDRESS)
     return false;
   RegisterValue value;
   if (!ReadRegister(emulator, DecodeRS2(inst), value))
     return false;
   return WriteMem<T>(emulator, addr, value);
 }
 
+// RV32I & RV64I (The base integer ISA) //
 static bool ExecLB(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   return Load<uint8_t, int8_t>(emulator, inst, SextW);
 }
 
 static bool ExecLH(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   return Load<uint16_t, int16_t>(emulator, inst, SextW);
 }
 
static bool ExecSW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   return Store<uint32_t>(emulator, inst);
 }
 
 static bool ExecSD(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   return Store<uint64_t>(emulator, inst);
 }
 
 static bool ExecADDI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = int64_t(value.GetAsUInt64()) + int64_t(imm);
+  uint64_t result = rs.rs1().sext<int64_t>() + int64_t(imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLTI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = int64_t(value.GetAsUInt64()) < int64_t(imm);
+  uint64_t result = rs.rs1().sext<int64_t>() < int64_t(imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLTIU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value.GetAsUInt64() < uint64_t(imm);
+  uint64_t result = rs.rs1().trunc<uint64_t>() < uint64_t(imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecXORI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value.GetAsUInt64() ^ uint64_t(imm);
+  uint64_t result = rs.rs1().trunc<uint64_t>() ^ uint64_t(imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecORI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value.GetAsUInt64() | uint64_t(imm);
+  uint64_t result = rs.rs1().trunc<uint64_t>() | uint64_t(imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecANDI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value.GetAsUInt64() & uint64_t(imm);
+  uint64_t result = rs.rs1().trunc<uint64_t>() & uint64_t(imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLLI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto shamt = DecodeSHAMT7(inst);
-
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value.GetAsUInt64() << shamt;
+  uint64_t result = rs.rs1().trunc<uint64_t>() << DecodeSHAMT7(inst);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRLI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto shamt = DecodeSHAMT7(inst);
-
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value.GetAsUInt64() >> shamt;
+  uint64_t result = rs.rs1().trunc<uint64_t>() >> DecodeSHAMT7(inst);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRAI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto shamt = DecodeSHAMT7(inst);
-
-  RegisterValue value;
-  if (!ReadRegister(emulator, rs1, value))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = int64_t(value.GetAsUInt64()) >> shamt;
+  uint64_t result = rs.rs1().sext<int64_t>() >> DecodeSHAMT7(inst);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecADD(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() + value2.GetAsUInt64();
+  uint64_t result = rs.rs1().trunc<uint64_t>() + rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSUB(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() - value2.GetAsUInt64();
+  uint64_t result = rs.rs1().trunc<uint64_t>() - rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() << (value2.GetAsUInt64() & 0b111111);
+  uint64_t result = rs.rs1().trunc<uint64_t>()
+                    << (rs.rs2().trunc<uint64_t>() & 0b111111);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLT(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = int64_t(value1.GetAsUInt64()) < int64_t(value2.GetAsUInt64());
+  uint64_t result = rs.rs1().sext<int64_t>() < rs.rs2().sext<int64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLTU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() < value2.GetAsUInt64();
+  uint64_t result = rs.rs1().trunc<uint64_t>() < rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecXOR(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() ^ value2.GetAsUInt64();
+  uint64_t result = rs.rs1().trunc<uint64_t>() ^ rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() >> (value2.GetAsUInt64() & 0b111111);
+  uint64_t result =
+      rs.rs1().trunc<uint64_t>() >> (rs.rs2().trunc<uint64_t>() & 0b111111);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRA(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
   uint64_t result =
-      int64_t(value1.GetAsUInt64()) >> (value2.GetAsUInt64() & 0b111111);
+      rs.rs1().sext<int64_t>() >> (rs.rs2().trunc<uint64_t>() & 0b111111);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecOR(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() | value2.GetAsUInt64();
+  uint64_t result = rs.rs1().trunc<uint64_t>() | rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecAND(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = value1.GetAsUInt64() & value2.GetAsUInt64();
+  uint64_t result = rs.rs1().trunc<uint64_t>() & rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecADDIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
   int32_t imm = SignExt(DecodeIImm(inst));
 
-  RegisterValue value1;
-  if (!ReadRegister(emulator, rs1, value1))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(int32_t(value1.GetAsUInt64()) + imm);
+  uint64_t result = SextW(rs.rs1().sext<int32_t>() + imm);
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLLIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto shamt = DecodeSHAMT5(inst);
-
-  RegisterValue value1;
-  if (!ReadRegister(emulator, rs1, value1))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(uint32_t(value1.GetAsUInt64()) << shamt);
+  uint64_t result = SextW(rs.rs1().trunc<uint32_t>() << DecodeSHAMT5(inst));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRLIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto shamt = DecodeSHAMT5(inst);
-
-  RegisterValue value1;
-  if (!ReadRegister(emulator, rs1, value1))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(uint32_t(value1.GetAsUInt64()) >> shamt);
+  uint64_t result = SextW(rs.rs1().trunc<uint32_t>() >> DecodeSHAMT5(inst));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRAIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto shamt = DecodeSHAMT5(inst);
-
-  RegisterValue value1;
-  if (!ReadRegister(emulator, rs1, value1))
+  auto rs = readRS1(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(int32_t(value1.GetAsUInt64()) >> shamt);
+  uint64_t result = SextW(rs.rs1().sext<int32_t>() >> DecodeSHAMT5(inst));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecADDW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(value1.GetAsUInt32() + value2.GetAsUInt32());
+  uint64_t result =
+      SextW(uint32_t(rs.rs1().trunc<uint64_t>() + rs.rs2().trunc<uint64_t>()));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSUBW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(value1.GetAsUInt32() - value2.GetAsUInt32());
+  uint64_t result =
+      SextW(uint32_t(rs.rs1().trunc<uint64_t>() - rs.rs2().trunc<uint64_t>()));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSLLW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(uint32_t(value1.GetAsUInt64())
-                          << (value2.GetAsUInt64() & 0b111111));
+  uint64_t result = SextW(rs.rs1().trunc<uint32_t>()
+                          << (rs.rs2().trunc<uint32_t>() & 0b11111));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRLW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
-
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result = SextW(uint32_t(value1.GetAsUInt64()) >>
-                          (value2.GetAsUInt64() & 0b111111));
+  uint64_t result = SextW(rs.rs1().trunc<uint32_t>() >>
+                          (rs.rs2().trunc<uint32_t>() & 0b11111));
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
 static bool ExecSRAW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = DecodeRS2(inst);
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
 
-  RegisterValue value1;
-  RegisterValue value2;
-  if (!ReadRegister(emulator, rs1, value1) ||
-      !ReadRegister(emulator, rs2, value2))
+  uint64_t result = SextW(rs.rs1().sext<int32_t>() >>
+                          (rs.rs2().trunc<uint64_t>() & 0b111111));
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+// RV32M & RV64M (The standard integer multiplication and division extension) //
+static bool ExecMUL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
     return false;
 
-  uint64_t result =
-      SextW(int32_t(value1.GetAsUInt64()) >> (value2.GetAsUInt64() & 0b111111));
+  uint64_t result = rs.rs1().trunc<uint64_t>() * rs.rs2().trunc<uint64_t>();
   return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
 }
 
+static bool ExecMULH(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  llvm::APInt mul = llvm::APInt(128, rs.rs1().trunc<uint64_t>(), true) *
+                    llvm::APInt(128, rs.rs2().trunc<uint64_t>(), true);
+
+  // signed * signed
+  auto result = mul.ashr(64).trunc(64).getZExtValue();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecMULHSU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  // signed * unsigned
+  llvm::APInt mul =
+      llvm::APInt(128, rs.rs1().trunc<uint64_t>(), true).zext(128) *
+      llvm::APInt(128, rs.rs2().trunc<uint64_t>(), false);
+
+  auto result = mul.lshr(64).trunc(64).getZExtValue();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecMULHU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  // unsigned * unsigned
+  llvm::APInt mul = llvm::APInt(128, rs.rs1().trunc<uint64_t>(), false) *
+                    llvm::APInt(128, rs.rs2().trunc<uint64_t>(), false);
+  auto result = mul.lshr(64).trunc(64).getZExtValue();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecDIV(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  int64_t dividend = rs.rs1().sext<int64_t>();
+  int64_t divisor = rs.rs2().sext<int64_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(UINT64_MAX));
+
+  if (dividend == INT64_MIN && divisor == -1)
+    return WriteRegister(emulator, DecodeRD(inst),
+                         RegisterValue(uint64_t(dividend)));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(uint64_t(dividend / divisor)));
+}
+
+static bool ExecDIVU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  uint64_t dividend = rs.rs1().trunc<uint64_t>();
+  uint64_t divisor = rs.rs2().trunc<uint64_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(UINT64_MAX));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(dividend / divisor));
+}
+
+static bool ExecREM(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  int64_t dividend = rs.rs1().sext<int64_t>();
+  int64_t divisor = rs.rs2().sext<int64_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst),
+                         RegisterValue(uint64_t(dividend)));
+
+  if (dividend == INT64_MIN && divisor == -1)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(uint64_t(0)));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(uint64_t(dividend % divisor)));
+}
+
+static bool ExecREMU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  uint64_t dividend = rs.rs1().trunc<uint64_t>();
+  uint64_t divisor = rs.rs2().trunc<uint64_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(dividend));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(dividend % divisor));
+}
+
+static bool ExecMULW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  uint64_t result = SextW(rs.rs1().sext<int32_t>() * rs.rs2().sext<int32_t>());
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecDIVW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  int32_t dividend = rs.rs1().sext<int32_t>();
+  int32_t divisor = rs.rs2().sext<int32_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(UINT64_MAX));
+
+  if (dividend == INT32_MIN && divisor == -1)
+    return WriteRegister(emulator, DecodeRD(inst),
+                         RegisterValue(SextW(dividend)));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(SextW(dividend / divisor)));
+}
+
+static bool ExecDIVUW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  uint32_t dividend = rs.rs1().trunc<uint32_t>();
+  uint32_t divisor = rs.rs2().trunc<uint32_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(UINT64_MAX));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(SextW(dividend / divisor)));
+}
+
+static bool ExecREMW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  int32_t dividend = rs.rs1().sext<int32_t>();
+  int32_t divisor = rs.rs2().sext<int32_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst),
+                         RegisterValue(SextW(dividend)));
+
+  if (dividend == INT32_MIN && divisor == -1)
+    return WriteRegister(emulator, DecodeRD(inst), RegisterValue(uint64_t(0)));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(SextW(dividend % divisor)));
+}
+
+static bool ExecREMUW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs = readRS1RS2(emulator, inst);
+  if (!rs.valid)
+    return false;
+
+  uint32_t dividend = rs.rs1().trunc<uint32_t>();
+  uint32_t divisor = rs.rs2().trunc<uint32_t>();
+
+  if (divisor == 0)
+    return WriteRegister(emulator, DecodeRD(inst),
+                         RegisterValue(SextW(dividend)));
+
+  return WriteRegister(emulator, DecodeRD(inst),
+                       RegisterValue(SextW(dividend % divisor)));
+}
+
+// RV32A & RV64A (The standard atomic instruction extension) //
+static uint64_t AtomicAddr(EmulateInstructionRISCV &emulator, uint32_t reg,
+                           unsigned int align) {
+  RegisterValue value;
+  if (!ReadRegister(emulator, reg, value))
+    return LLDB_INVALID_ADDRESS;
+
+  uint64_t addr = value.GetAsUInt64();
+  return addr % align == 0 ? addr : LLDB_INVALID_ADDRESS;
+}
+
+template <typename T>
+static bool AtomicSwap(EmulateInstructionRISCV &emulator, uint32_t inst,
+                       int align, uint64_t (*extend)(T)) {
+  RegisterValue rs2;
+  if (!ReadRegister(emulator, DecodeRS2(inst), rs2))
+    return false;
+
+  uint64_t addr = AtomicAddr(emulator, DecodeRS1(inst), align);
+  if (addr == LLDB_INVALID_ADDRESS)
+    return false;
+
+  T tmp = ReadMem<T>(emulator, addr).value();
+  if (!tmp)
+    return false;
+
+  bool success =
+      WriteMem<T>(emulator, addr, RegisterValue(T(rs2.GetAsUInt64())));
+  if (!success)
+    return false;
+
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(extend(tmp)));
+}
+
+template <typename T>
+static bool AtomicADD(EmulateInstructionRISCV &emulator, uint32_t inst,
+                      int align, uint64_t (*extend)(T)) {
+  RegisterValue rs2;
+  if (!ReadRegister(emulator, DecodeRS2(inst), rs2))
+    return false;
+
+  uint64_t addr = AtomicAddr(emulator, DecodeRS1(inst), align);
+  if (addr == LLDB_INVALID_ADDRESS)
+    return false;
+
+  T value = ReadMem<T>(emulator, addr).value();
+  if (!value)
+    return false;
+
+  bool success =
+      WriteMem<T>(emulator, addr, RegisterValue(value + T(rs2.GetAsUInt64())));
+  if (!success)
+    return false;
+
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(extend(value)));
+}
+
+template <typename T>
+static bool AtomicBitOperate(EmulateInstructionRISCV &emulator, uint32_t inst,
+                             int align, uint64_t (*extend)(T),
+                             T (*operate)(T, T)) {
+  RegisterValue rs2;
+  if (!ReadRegister(emulator, DecodeRS2(inst), rs2))
+    return false;
+
+  uint64_t addr = AtomicAddr(emulator, DecodeRS1(inst), align);
+  if (addr == LLDB_INVALID_ADDRESS)
+    return false;
+
+  T value = ReadMem<T>(emulator, addr).value();
+  if (!value)
+    return false;
+
+  bool success = WriteMem<T>(
+      emulator, addr, RegisterValue(operate(value, T(rs2.GetAsUInt64()))));
+  if (!success)
+    return false;
+
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(extend(value)));
+}
+
+template <typename T>
+static bool AtomicCmp(EmulateInstructionRISCV &emulator, uint32_t inst,
+                      int align, uint64_t (*extend)(T), T (*cmp)(T, T)) {
+  RegisterValue rs2;
+  if (!ReadRegister(emulator, DecodeRS2(inst), rs2))
+    return false;
+
+  uint64_t addr = AtomicAddr(emulator, DecodeRS1(inst), align);
+  if (addr == LLDB_INVALID_ADDRESS)
+    return false;
+
+  T value = ReadMem<T>(emulator, addr).value();
+  if (!value)
+    return false;
+
+  bool success = WriteMem<T>(emulator, addr,
+                             RegisterValue(cmp(value, T(rs2.GetAsUInt64()))));
+  if (!success)
+    return false;
+
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(extend(value)));
+}
+
+// 00010 aq[1] rl[1] 00000 rs1[5] 010 rd[5] 0101111 LR.D
+// 00010 aq[1] rl[1] 00000 rs1[5] 011 rd[5] 0101111 LR.W
+static bool IsLR(uint32_t inst) {
+  return (inst & 0xF9F0707F) == 0x1000202F || (inst & 0xF9F0707F) == 0x1000302F;
+}
+
+// 00011 aq[1] rl[1] rs2[5] rs1[5] 010 rd[5] 0101111 SC.W
+// 00011 aq[1] rl[1] rs2[5] rs1[5] 011 rd[5] 0101111 SC.D
+static bool IsSC(uint32_t inst) {
+  return (inst & 0xF800707F) == 0x1800202F || (inst & 0xF800707F) == 0x1800302F;
+}
+
+// imm[7] rs2[5] rs1[5] 001 imm[5] 1100011 BNE
+static bool IsBNE(uint32_t inst) { return (inst & 0x707F) == 0x1063; }
+
+static bool ExecAtomicSequence(EmulateInstructionRISCV &emulator, uint32_t inst,
+                               bool) {
+  // The atomic sequence is always 4 instructions long:
+  // example:
+  //   110cc: 100427af            lr.w  a5,(s0)
+  //   110d0: 00079663            bnez  a5,110dc
+  //   110d4: 1ce426af            sc.w.aq a3,a4,(s0)
+  //   110d8: fe069ae3            bnez  a3,110cc
+  //   110dc:   ........            <next instruction>
+  bool success = false;
+  llvm::Optional<lldb::addr_t> pc = emulator.ReadPC(success);
+  if (!success || !pc)
+    return false;
+  lldb::addr_t current_pc = pc.value();
+  lldb::addr_t start_pc = current_pc;
+  llvm::Optional<uint32_t> value = inst;
+
+  // inst must be LR
+  if (!value || !IsLR(value.value()))
+    return false;
+  value = ReadMem<uint32_t>(emulator, current_pc += 4).value();
+
+  // inst must be BNE to exit
+  if (!value || !IsBNE(value.value()))
+    return false;
+  auto exit_pc = current_pc + SextW(DecodeBImm(value.value()));
+  value = ReadMem<uint32_t>(emulator, current_pc += 4).value();
+
+  // inst must be SC
+  if (!value || !IsSC(value.value()))
+    return false;
+  value = ReadMem<uint32_t>(emulator, current_pc += 4).value();
+
+  // inst must be BNE to restart
+  if (!value || !IsBNE(value.value()))
+    return false;
+  if (current_pc + SextW(DecodeBImm(value.value())) != start_pc)
+    return false;
+  current_pc += 4;
+
+  if (exit_pc != current_pc)
+    return false;
+
+  return emulator.WritePC(current_pc);
+}
+
+static bool ExecLR_W(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return ExecAtomicSequence(emulator, inst, false);
+}
+
+static bool ExecAMOSWAP_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                          bool) {
+  return AtomicSwap<uint32_t>(emulator, inst, 4, SextW);
+}
+
+static bool ExecAMOADD_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicADD<uint32_t>(emulator, inst, 4, SextW);
+}
+
+static bool ExecAMOXOR_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicBitOperate<uint32_t>(
+      emulator, inst, 4, SextW, [](uint32_t a, uint32_t b) { return a ^ b; });
+}
+
+static bool ExecAMOAND_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicBitOperate<uint32_t>(
+      emulator, inst, 4, SextW, [](uint32_t a, uint32_t b) { return a & b; });
+}
+
+static bool ExecAMOOR_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                        bool) {
+  return AtomicBitOperate<uint32_t>(
+      emulator, inst, 4, SextW, [](uint32_t a, uint32_t b) { return a | b; });
+}
+
+static bool ExecAMOMIN_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicCmp<uint32_t>(
+      emulator, inst, 4, SextW, [](uint32_t a, uint32_t b) {
+        return uint32_t(std::min(int32_t(a), int32_t(b)));
+      });
+}
+
+static bool ExecAMOMAX_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicCmp<uint32_t>(
+      emulator, inst, 4, SextW, [](uint32_t a, uint32_t b) {
+        return uint32_t(std::max(int32_t(a), int32_t(b)));
+      });
+}
+
+static bool ExecAMOMINU_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                          bool) {
+  return AtomicCmp<uint32_t>(
+      emulator, inst, 4, SextW,
+      [](uint32_t a, uint32_t b) { return std::min(a, b); });
+}
+
+static bool ExecAMOMAXU_W(EmulateInstructionRISCV &emulator, uint32_t inst,
+                          bool) {
+  return AtomicCmp<uint32_t>(
+      emulator, inst, 4, SextW,
+      [](uint32_t a, uint32_t b) { return std::max(a, b); });
+}
+
+static bool ExecLR_D(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return ExecAtomicSequence(emulator, inst, false);
+}
+
+static bool ExecAMOSWAP_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                          bool) {
+  return AtomicSwap<uint64_t>(emulator, inst, 8, ZextD);
+}
+
+static bool ExecAMOADD_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicADD<uint64_t>(emulator, inst, 8, ZextD);
+}
+
+static bool ExecAMOXOR_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicBitOperate<uint64_t>(
+      emulator, inst, 8, ZextD, [](uint64_t a, uint64_t b) { return a ^ b; });
+}
+
+static bool ExecAMOAND_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicBitOperate<uint64_t>(
+      emulator, inst, 8, ZextD, [](uint64_t a, uint64_t b) { return a & b; });
+}
+
+static bool ExecAMOOR_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                        bool) {
+  return AtomicBitOperate<uint64_t>(
+      emulator, inst, 8, ZextD, [](uint64_t a, uint64_t b) { return a | b; });
+}
+
+static bool ExecAMOMIN_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicCmp<uint64_t>(
+      emulator, inst, 8, ZextD, [](uint64_t a, uint64_t b) {
+        return uint64_t(std::min(int64_t(a), int64_t(b)));
+      });
+}
+
+static bool ExecAMOMAX_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                         bool) {
+  return AtomicCmp<uint64_t>(
+      emulator, inst, 8, ZextD, [](uint64_t a, uint64_t b) {
+        return uint64_t(std::max(int64_t(a), int64_t(b)));
+      });
+}
+
+static bool ExecAMOMINU_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                          bool) {
+  return AtomicCmp<uint64_t>(
+      emulator, inst, 8, ZextD,
+      [](uint64_t a, uint64_t b) { return std::min(a, b); });
+}
+
+static bool ExecAMOMAXU_D(EmulateInstructionRISCV &emulator, uint32_t inst,
+                          bool) {
+  return AtomicCmp<uint64_t>(
+      emulator, inst, 8, ZextD,
+      [](uint64_t a, uint64_t b) { return std::max(a, b); });
+}
+
 static const InstrPattern PATTERNS[] = {
+    // RV32I & RV64I (The base integer ISA) //
     {"LUI", 0x7F, 0x37, ExecLUI},
     {"AUIPC", 0x7F, 0x17, ExecAUIPC},
     {"JAL", 0x7F, 0x6F, ExecJAL},
     {"JALR", 0x707F, 0x67, ExecJALR},
     {"B<CMP>", 0x7F, 0x63, ExecB},
     {"LB", 0x707F, 0x3, ExecLB},
     {"LH", 0x707F, 0x1003, ExecLH},
     {"LW", 0x707F, 0x2003, ExecLW},
static const InstrPattern PATTERNS[] = {
     {"SLLIW", 0xFE00707F, 0x101B, ExecSLLIW},
     {"SRLIW", 0xFE00707F, 0x501B, ExecSRLIW},
     {"SRAIW", 0xFE00707F, 0x4000501B, ExecSRAIW},
     {"ADDW", 0xFE00707F, 0x3B, ExecADDW},
     {"SUBW", 0xFE00707F, 0x4000003B, ExecSUBW},
     {"SLLW", 0xFE00707F, 0x103B, ExecSLLW},
     {"SRLW", 0xFE00707F, 0x503B, ExecSRLW},
     {"SRAW", 0xFE00707F, 0x4000503B, ExecSRAW},
+
+    // RV32M & RV64M (The integer multiplication and division extension) //
+    {"MUL", 0xFE00707F, 0x2000033, ExecMUL},
+    {"MULH", 0xFE00707F, 0x2001033, ExecMULH},
+    {"MULHSU", 0xFE00707F, 0x2002033, ExecMULHSU},
+    {"MULHU", 0xFE00707F, 0x2003033, ExecMULHU},
+    {"DIV", 0xFE00707F, 0x2004033, ExecDIV},
+    {"DIVU", 0xFE00707F, 0x2005033, ExecDIVU},
+    {"REM", 0xFE00707F, 0x2006033, ExecREM},
+    {"REMU", 0xFE00707F, 0x2007033, ExecREMU},
+    {"MULW", 0xFE00707F, 0x200003B, ExecMULW},
+    {"DIVW", 0xFE00707F, 0x200403B, ExecDIVW},
+    {"DIVUW", 0xFE00707F, 0x200503B, ExecDIVUW},
+    {"REMW", 0xFE00707F, 0x200603B, ExecREMW},
+    {"REMUW", 0xFE00707F, 0x200703B, ExecREMUW},
+
+    // RV32A & RV64A (The standard atomic instruction extension) //
+    {"LR_W", 0xF9F0707F, 0x1000202F, ExecLR_W},
+    {"AMOSWAP_W", 0xF800707F, 0x800202F, ExecAMOSWAP_W},
+    {"AMOADD_W", 0xF800707F, 0x202F, ExecAMOADD_W},
+    {"AMOXOR_W", 0xF800707F, 0x2000202F, ExecAMOXOR_W},
+    {"AMOAND_W", 0xF800707F, 0x6000202F, ExecAMOAND_W},
+    {"AMOOR_W", 0xF800707F, 0x4000202F, ExecAMOOR_W},
+    {"AMOMIN_W", 0xF800707F, 0x8000202F, ExecAMOMIN_W},
+    {"AMOMAX_W", 0xF800707F, 0xA000202F, ExecAMOMAX_W},
+    {"AMOMINU_W", 0xF800707F, 0xC000202F, ExecAMOMINU_W},
+    {"AMOMAXU_W", 0xF800707F, 0xE000202F, ExecAMOMAXU_W},
+    {"LR_D", 0xF9F0707F, 0x1000302F, ExecLR_D},
+    {"AMOSWAP_D", 0xF800707F, 0x800302F, ExecAMOSWAP_D},
+    {"AMOADD_D", 0xF800707F, 0x302F, ExecAMOADD_D},
+    {"AMOXOR_D", 0xF800707F, 0x2000302F, ExecAMOXOR_D},
+    {"AMOAND_D", 0xF800707F, 0x6000302F, ExecAMOAND_D},
+    {"AMOOR_D", 0xF800707F, 0x4000302F, ExecAMOOR_D},
+    {"AMOMIN_D", 0xF800707F, 0x8000302F, ExecAMOMIN_D},
+    {"AMOMAX_D", 0xF800707F, 0xA000302F, ExecAMOMAX_D},
+    {"AMOMINU_D", 0xF800707F, 0xC000302F, ExecAMOMINU_D},
+    {"AMOMAXU_D", 0xF800707F, 0xE000302F, ExecAMOMAXU_D},
 };
 
 const InstrPattern *EmulateInstructionRISCV::Decode(uint32_t inst) {
   for (const InstrPattern &pat : PATTERNS) {
-    if ((inst & pat.type_mask) == pat.eigen) {
+    if ((inst & pat.type_mask) == pat.eigen)
       return &pat;
-    }
-  }
   return nullptr;
 }
 
 /// This function only determines the next instruction address for software
-/// sigle stepping by emulating instructions
+/// single stepping by emulating instructions
 bool EmulateInstructionRISCV::DecodeAndExecute(uint32_t inst,
                                                bool ignore_cond) {
   Log *log = GetLog(LLDBLog::Unwind);
   const InstrPattern *pattern = this->Decode(inst);
   if (pattern) {
     LLDB_LOGF(log, "EmulateInstructionRISCV::%s: inst(%x) was decoded to %s",
               __FUNCTION__, inst, pattern->name);
     return pattern->exec(*this, inst, ignore_cond);
   }
 
-  LLDB_LOGF(log,
-            "EmulateInstructionRISCV::%s: inst(0x%x) does not branch: "
-            "no need to calculate the next pc address which is trivial.",
+  LLDB_LOGF(log, "EmulateInstructionRISCV::%s: inst(0x%x) was unsupported",
             __FUNCTION__, inst);
-  return true;
+  return false;
 }
 
 bool EmulateInstructionRISCV::EvaluateInstruction(uint32_t options) {
   uint32_t inst_size = m_opcode.GetByteSize();
   uint32_t inst = m_opcode.GetOpcode32();
   bool increase_pc = options & eEmulateInstructionOptionAutoAdvancePC;
   bool ignore_cond = options & eEmulateInstructionOptionIgnoreConditions;
   bool success = false;
 
   lldb::addr_t old_pc = LLDB_INVALID_ADDRESS;
   if (increase_pc) {
-    old_pc = ReadPC(&success);
+    old_pc = ReadPC(success);
     if (!success)
       return false;
   }
 
   if (inst_size == 2) {
     // TODO: execute RVC
     return false;
   }
 
   success = DecodeAndExecute(inst, ignore_cond);
   if (!success)
     return false;
 
   if (increase_pc) {
-    lldb::addr_t new_pc = ReadPC(&success);
+    lldb::addr_t new_pc = ReadPC(success);
     if (!success)
       return false;
 
     if (new_pc == old_pc) {
       if (!WritePC(old_pc + inst_size))
         return false;
     }
   }
   return true;
 }
 
 bool EmulateInstructionRISCV::ReadInstruction() {
   bool success = false;
-  m_addr = ReadPC(&success);
+  m_addr = ReadPC(success);
   if (!success) {
     m_addr = LLDB_INVALID_ADDRESS;
     return false;
   }
 
   Context ctx;
   ctx.type = eContextReadOpcode;
   ctx.SetNoArgs();
   uint32_t inst = uint32_t(ReadMemoryUnsigned(ctx, m_addr, 4, 0, &success));
   uint16_t try_rvc = uint16_t(inst & 0x0000ffff);
   // check whether the compressed encode could be valid
   uint16_t mask = try_rvc & 0b11;
   if (try_rvc != 0 && mask != 3)
     m_opcode.SetOpcode16(try_rvc, GetByteOrder());
   else
     m_opcode.SetOpcode32(inst, GetByteOrder());
 
   return true;
 }
 
-lldb::addr_t EmulateInstructionRISCV::ReadPC(bool *success) {
+lldb::addr_t EmulateInstructionRISCV::ReadPC(bool &success) {
   return ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
-                              LLDB_INVALID_ADDRESS, success);
+                              LLDB_INVALID_ADDRESS, &success);
 }
 
 bool EmulateInstructionRISCV::WritePC(lldb::addr_t pc) {
   EmulateInstruction::Context ctx;
   ctx.type = eContextAdvancePC;
   ctx.SetNoArgs();
   return WriteRegisterUnsigned(ctx, eRegisterKindGeneric,
                                LLDB_REGNUM_GENERIC_PC, pc);

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

 #include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
 #include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
 
 using namespace lldb;
 using namespace lldb_private;
 
 struct RISCVEmulatorTester : public EmulateInstructionRISCV, testing::Test {
   RegisterInfoPOSIX_riscv64::GPR gpr;
+  uint8_t memory[1024] = {0};
 
   RISCVEmulatorTester()
       : EmulateInstructionRISCV(ArchSpec("riscv64-unknown-linux-gnu")) {
     EmulateInstruction::SetReadRegCallback(ReadRegisterCallback);
     EmulateInstruction::SetWriteRegCallback(WriteRegisterCallback);
+    EmulateInstruction::SetReadMemCallback(ReadMemoryCallback);
+    EmulateInstruction::SetWriteMemCallback(WriteMemoryCallback);
   }
 
   static bool ReadRegisterCallback(EmulateInstruction *instruction, void *baton,
                                    const RegisterInfo *reg_info,
                                    RegisterValue &reg_value) {
     RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
     uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
     if (reg == gpr_x0_riscv)
       reg_value.SetUInt(0, reg_info->byte_size);
     else
       reg_value.SetUInt(tester->gpr.gpr[reg], reg_info->byte_size);
     return true;
   }
 
   static bool WriteRegisterCallback(EmulateInstruction *instruction,
                                     void *baton, const Context &context,
                                     const RegisterInfo *reg_info,
                                     const RegisterValue &reg_value) {
     RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
     uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
     if (reg != gpr_x0_riscv)
       tester->gpr.gpr[reg] = reg_value.GetAsUInt64();
     return true;
   }
+
+  static size_t ReadMemoryCallback(EmulateInstruction *instruction, void *baton,
+                                   const Context &context, lldb::addr_t addr,
+                                   void *dst, size_t length) {
+    RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
+    assert(addr + length < sizeof(tester->memory));
+    memcpy(dst, tester->memory + addr, length);
+    return length;
+  };
+
+  static size_t WriteMemoryCallback(EmulateInstruction *instruction,
+                                    void *baton, const Context &context,
+                                    lldb::addr_t addr, const void *dst,
+                                    size_t length) {
+    RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
+    assert(addr + length < sizeof(tester->memory));
+    memcpy(tester->memory + addr, dst, length);
+    return length;
+  };
 };
 
 TEST_F(RISCVEmulatorTester, testJAL) {
   lldb::addr_t old_pc = 0x114514;
   WritePC(old_pc);
   // jal x1, -6*4
   uint32_t inst = 0b11111110100111111111000011101111;
   ASSERT_TRUE(DecodeAndExecute(inst, false));
   auto x1 = gpr.gpr[1];
 
   bool success = false;
-  auto pc = ReadPC(&success);
+  auto pc = ReadPC(success);
 
   ASSERT_TRUE(success);
   ASSERT_EQ(x1, old_pc + 4);
   ASSERT_EQ(pc, old_pc + (-6 * 4));
 }
 
 constexpr uint32_t EncodeIType(uint32_t opcode, uint32_t funct3, uint32_t rd,
                                uint32_t rs1, uint32_t imm) {
TEST_F(RISCVEmulatorTester, testJALR) {
   WritePC(old_pc);
   gpr.gpr[2] = old_x2;
   // jalr x1, x2(-255)
   uint32_t inst = JALR(1, 2, -255);
   ASSERT_TRUE(DecodeAndExecute(inst, false));
   auto x1 = gpr.gpr[1];
 
   bool success = false;
-  auto pc = ReadPC(&success);
+  auto pc = ReadPC(success);
 
   ASSERT_TRUE(success);
   ASSERT_EQ(x1, old_pc + 4);
   // JALR always zeros the bottom bit of the target address.
   ASSERT_EQ(pc, (old_x2 + (-255)) & (~1));
 }
 
 constexpr uint32_t EncodeBType(uint32_t opcode, uint32_t funct3, uint32_t rs1,
void testBranch(RISCVEmulatorTester *tester, EncoderB encoder, bool branched,
   lldb::addr_t old_pc = 0x114514;
   tester->WritePC(old_pc);
   tester->gpr.gpr[1] = rs1;
   tester->gpr.gpr[2] = rs2;
   // b<cmp> x1, x2, (-256)
   uint32_t inst = encoder(1, 2, -256);
   ASSERT_TRUE(tester->DecodeAndExecute(inst, false));
   bool success = false;
-  auto pc = tester->ReadPC(&success);
+  auto pc = tester->ReadPC(success);
   ASSERT_TRUE(success);
   ASSERT_EQ(pc, old_pc + (branched ? (-256) : 0));
 }
 
 #define GEN_BRANCH_TEST(name, rs1, rs2_branched, rs2_continued)                \
   TEST_F(RISCVEmulatorTester, test##name##Branched) {                          \
     testBranch(this, name, true, rs1, rs2_branched);                           \
   }                                                                            \
   TEST_F(RISCVEmulatorTester, test##name##Continued) {                         \
     testBranch(this, name, false, rs1, rs2_continued);                         \
   }
 
 void CheckRD(RISCVEmulatorTester *tester, uint64_t rd, uint64_t value) {
   ASSERT_EQ(tester->gpr.gpr[rd], value);
 }
 
+template <typename T>
+void CheckMem(RISCVEmulatorTester *tester, uint64_t addr, uint64_t value) {
+  bool success = false;
+  ASSERT_EQ(tester->ReadMem<T>(*tester, addr, &success), value);
+  ASSERT_TRUE(success);
+}
+
 using RS1 = uint64_t;
 using RS2 = uint64_t;
 using PC = uint64_t;
 using RDComputer = std::function<uint64_t(RS1, RS2, PC)>;
 
 void TestInst(RISCVEmulatorTester *tester, uint64_t inst, bool has_rs2,
               RDComputer rd_val) {
 
   lldb::addr_t old_pc = 0x114514;
   tester->WritePC(old_pc);
-  auto rd = DecodeRD(inst);
-  auto rs1 = DecodeRS1(inst);
-  auto rs2 = 0;
+  uint32_t rd = DecodeRD(inst);
+  uint32_t rs1 = DecodeRS1(inst);
+  uint32_t rs2 = 0;
+
+  uint64_t rs1_val = 0x19;
+  uint64_t rs2_val = 0x81;
+
   if (rs1)
-    tester->gpr.gpr[rs1] = 0x1919;
+    tester->gpr.gpr[rs1] = rs1_val;
 
   if (has_rs2) {
     rs2 = DecodeRS2(inst);
-    if (rs2)
-      tester->gpr.gpr[rs2] = 0x8181;
-  }
+    if (rs2) {
+      if (rs1 == rs2)
+        rs2_val = rs1_val;
+      tester->gpr.gpr[rs2] = rs2_val;
+    }
+  }
+
+  ASSERT_TRUE(tester->DecodeAndExecute(inst, false));
+  CheckRD(tester, rd, rd_val(rs1_val, rs2 ? rs2_val : 0, old_pc));
 
+template <typename T>
+void TestAtomic(RISCVEmulatorTester *tester, uint64_t inst, T rs1_val,
+                T rs2_val, T rd_expected, T mem_expected) {
+  // Atomic inst must have rs1 and rs2
+
+  uint32_t rd = DecodeRD(inst);
+  uint32_t rs1 = DecodeRS1(inst);
+  uint32_t rs2 = DecodeRS2(inst);
+
+  // addr was stored in rs1
+  uint64_t atomic_addr = 0x100;
+
+  tester->gpr.gpr[rs1] = atomic_addr;
+  tester->gpr.gpr[rs2] = rs2_val;
+
+  // Write and check rs1_val in atomic_addr
+  ASSERT_TRUE(
+      tester->WriteMem<T>(*tester, atomic_addr, RegisterValue(rs1_val)));
+  CheckMem<T>(tester, atomic_addr, rs1_val);
+
   ASSERT_TRUE(tester->DecodeAndExecute(inst, false));
-  CheckRD(tester, rd,
-          rd_val(tester->gpr.gpr[rs1], rs2 ? tester->gpr.gpr[rs2] : 0, old_pc));
+  CheckRD(tester, rd, rd_expected);
+  CheckMem<T>(tester, atomic_addr, mem_expected);
+}
+
+TEST_F(RISCVEmulatorTester, TestAtomicSequence) {
+  this->WritePC(0x0);
+  *(uint64_t *)this->memory = 0x100427af;        // lr.w  a5,(s0)
+  *(uint64_t *)(this->memory + 4) = 0x00079663;  // bnez  a5,12
+  *(uint64_t *)(this->memory + 8) = 0x1ce426af;  // sc.w.aq  a3,a4,(s0)
+  *(uint64_t *)(this->memory + 12) = 0xfe069ae3; // bnez  a3,-12
+  ASSERT_TRUE(this->DecodeAndExecute(*(uint32_t *)this->memory, false));
+  ASSERT_EQ(this->gpr.gpr[0], uint64_t(16));
 }
 
 // GEN_BRANCH_TEST(opcode, imm1, imm2, imm3):
 // It should branch for instruction `opcode imm1, imm2`
 // It should do nothing for instruction `opcode imm1, imm3`
 GEN_BRANCH_TEST(BEQ, 1, 1, 0)
 GEN_BRANCH_TEST(BNE, 1, 0, 1)
 GEN_BRANCH_TEST(BLT, -2, 1, -3)
 GEN_BRANCH_TEST(BGE, -2, -3, 1)
 GEN_BRANCH_TEST(BLTU, -2, -1, 1)
 GEN_BRANCH_TEST(BGEU, -2, 1, -1)
 
 struct TestData {
   uint32_t inst;
   std::string name;
   bool has_rs2;
   RDComputer rd_val;
 };
 
 TEST_F(RISCVEmulatorTester, TestDecodeAndExcute) {
 
   std::vector<TestData> tests = {
+      // RV32I & RV64I Tests
       {0x00010113, "ADDI", false, [](RS1 rs1, RS2, PC) { return rs1 + 0; }},
       {0x00023517, "AUIPC", false, [](RS1, RS2, PC pc) { return pc + 143360; }},
       {0x0006079b, "ADDIW", false, [](RS1 rs1, RS2, PC) { return rs1 + 0; }},
       {0x00110837, "LUI", false, [](RS1, RS2, PC pc) { return 1114112; }},
       {0x00147513, "ANDI", false, [](RS1 rs1, RS2, PC) { return rs1 & 1; }},
-      {0x00153513, "SLTIU", false, [](RS1 rs1, RS2, PC) { return rs1 != 0; }},
-      {0x00256513, "ORI", false, [](RS1 rs1, RS2, PC) { return rs1 | 1; }},
+      {0x00153513, "SLTIU", false, [](RS1 rs1, RS2, PC) { return 0; }},
+      {0x00256513, "ORI", false, [](RS1 rs1, RS2, PC) { return rs1 | 2; }},
       {0x00451a13, "SLLI", false, [](RS1 rs1, RS2, PC) { return rs1 << 4; }},
       {0x00455693, "SRLI", false, [](RS1 rs1, RS2, PC) { return rs1 >> 4; }},
       {0x00a035b3, "SLTU", true, [](RS1 rs1, RS2 rs2, PC) { return rs2 != 0; }},
       {0x00b50633, "ADD", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 + rs2; }},
       {0x40d507b3, "SUB", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 - rs2; }},
+
+      // RV32M & RV64M Tests
+      {0x02f787b3, "MUL", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 * rs2; }},
+      {0x2F797B3, "MULH", true, [](RS1 rs1, RS2 rs2, PC) { return 0; }},
+      {0x2F7A7B3, "MULHSU", true,
+       [](RS1 rs1, RS2 rs2, PC) { return 0; }},
+      {0x2F7B7B3, "MULHU", true,
+       [](RS1 rs1, RS2 rs2, PC) { return 0; }},
+      {0x02f747b3, "DIV", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 / rs2; }},
+      {0x02f757b3, "DIVU", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 / rs2; }},
+      {0x02f767b3, "REM", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 % rs2; }},
+      {0x02f777b3, "REMU", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 % rs2; }},
+      {0x02f787bb, "MULW", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 * rs2; }},
+      {0x02f747bb, "DIVW", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 / rs2; }},
+      {0x02f757bb, "DIVUW", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 / rs2; }},
+      {0x02f767bb, "REMW", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 % rs2; }},
+      {0x02f777bb, "REMUW", true,
+       [](RS1 rs1, RS2 rs2, PC) { return rs1 % rs2; }},
   };
   for (auto i : tests) {
     const InstrPattern *pattern = this->Decode(i.inst);
     ASSERT_TRUE(pattern != nullptr);
     std::string name = pattern->name;
     ASSERT_EQ(name, i.name);
     TestInst(this, i.inst, i.has_rs2, i.rd_val);
   }
 }
+
+TEST_F(RISCVEmulatorTester, TestAMOSWAP) {
+  TestAtomic<uint32_t>(this, 0x8F7282F, 0x1, 0x2, 0x1, 0x2);
+  TestAtomic<uint64_t>(this, 0x8F7382F, 0x1, 0x2, 0x1, 0x2);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOADD) {
+  TestAtomic<uint32_t>(this, 0xF7282F, 0x1, 0x2, 0x1, 0x3);
+  TestAtomic<uint64_t>(this, 0xF7382F, 0x1, 0x2, 0x1, 0x3);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOXOR) {
+  TestAtomic<uint32_t>(this, 0x20F7282F, 0x1, 0x2, 0x1, 0x3);
+  TestAtomic<uint32_t>(this, 0x20F7382F, 0x1, 0x2, 0x1, 0x3);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOAND) {
+  TestAtomic<uint32_t>(this, 0x60F7282F, 0x1, 0x2, 0x1, 0x0);
+  TestAtomic<uint64_t>(this, 0x60F7382F, 0x1, 0x2, 0x1, 0x0);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOOR) {
+  TestAtomic<uint32_t>(this, 0x40F7282F, 0x1, 0x2, 0x1, 0x3);
+  TestAtomic<uint32_t>(this, 0x40F7382F, 0x1, 0x2, 0x1, 0x3);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOMIN) {
+  TestAtomic<uint32_t>(this, 0x80F7282F, 0x1, 0x2, 0x1, 0x1);
+  TestAtomic<uint64_t>(this, 0x80F7382F, 0x1, 0x2, 0x1, 0x1);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOMAX) {
+  TestAtomic<uint32_t>(this, 0xA0F7282F, 0x1, 0x2, 0x1, 0x2);
+  TestAtomic<uint64_t>(this, 0xA0F7382F, 0x1, 0x2, 0x1, 0x2);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOMINU) {
+  TestAtomic<uint32_t>(this, 0xC0F7282F, 0x1, 0x2, 0x1, 0x1);
+  TestAtomic<uint64_t>(this, 0xC0F7382F, 0x1, 0x2, 0x1, 0x1);
+}
+
+TEST_F(RISCVEmulatorTester, TestAMOMAXU) {
+  TestAtomic<uint32_t>(this, 0xE0F7282F, 0x1, 0x2, 0x1, 0x2);
+  TestAtomic<uint64_t>(this, 0xE0F7382F, 0x1, 0x2, 0x1, 0x2);
+}