This is an archive of the discontinued LLVM Phabricator instance.

Differential D132637

[RISCV][NFC] Use common prefix to simplify test.
ClosedPublic

Authored by jacquesguan on Aug 25 2022, 1:45 AM.

Details

Reviewers
wangpc
craig.topper
asb
luismarques
frasercrmck
benshi001
Commits
rGb28b54f8fcec: [RISCV][NFC] Use common prefix to simplify test.

Diff Detail

Event Timeline

jacquesguan created this revision.Aug 25 2022, 1:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 25 2022, 1:45 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 26 others. · View Herald Transcript
jacquesguan requested review of this revision.Aug 25 2022, 1:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 25 2022, 1:45 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
frasercrmck accepted this revision.Aug 25 2022, 2:34 AM

LGTM

This revision is now accepted and ready to land.Aug 25 2022, 2:34 AM
Harbormaster completed remote builds in B183315: Diff 455505.Aug 25 2022, 2:51 AM
This revision was landed with ongoing or failed builds.Aug 25 2022, 8:03 PM
Closed by commit rGb28b54f8fcec: [RISCV][NFC] Use common prefix to simplify test. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rGb28b54f8fcec: [RISCV][NFC] Use common prefix to simplify test..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
472 lines

Diff 455778

llvm/test/CodeGen/RISCV/div-pow2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefixes=RV32,RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZBT ; RUN: | FileCheck %s -check-prefixes=RV32,RV32ZBT
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefixes=RV64,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBT ; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBT
define i32 @sdiv32_pow2_2(i32 %a) { define i32 @sdiv32_pow2_2(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_2: ; RV32-LABEL: sdiv32_pow2_2:
; RV32I: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32I-NEXT: srli a1, a0, 31 ; RV32-NEXT: srli a1, a0, 31
; RV32I-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 1 ; RV32-NEXT: srai a0, a0, 1
; RV32I-NEXT: ret ; RV32-NEXT: ret
; ;
; RV32ZBT-LABEL: sdiv32_pow2_2: ; RV64-LABEL: sdiv32_pow2_2:
; RV32ZBT: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV32ZBT-NEXT: srli a1, a0, 31 ; RV64-NEXT: srliw a1, a0, 31
; RV32ZBT-NEXT: add a0, a0, a1 ; RV64-NEXT: addw a0, a0, a1
; RV32ZBT-NEXT: srai a0, a0, 1 ; RV64-NEXT: sraiw a0, a0, 1
; RV32ZBT-NEXT: ret ; RV64-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srliw a1, a0, 31
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: sdiv32_pow2_2:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srliw a1, a0, 31
; RV64ZBT-NEXT: addw a0, a0, a1
; RV64ZBT-NEXT: sraiw a0, a0, 1
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, 2 %div = sdiv i32 %a, 2
ret i32 %div ret i32 %div
} }
define i32 @sdiv32_pow2_negative_2(i32 %a) { define i32 @sdiv32_pow2_negative_2(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_2: ; RV32-LABEL: sdiv32_pow2_negative_2:
; RV32I: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32I-NEXT: srli a1, a0, 31 ; RV32-NEXT: srli a1, a0, 31
; RV32I-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 1 ; RV32-NEXT: srai a0, a0, 1
; RV32I-NEXT: neg a0, a0 ; RV32-NEXT: neg a0, a0
; RV32I-NEXT: ret ; RV32-NEXT: ret
; ;
; RV32ZBT-LABEL: sdiv32_pow2_negative_2: ; RV64-LABEL: sdiv32_pow2_negative_2:
; RV32ZBT: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV32ZBT-NEXT: srli a1, a0, 31 ; RV64-NEXT: srliw a1, a0, 31
; RV32ZBT-NEXT: add a0, a0, a1 ; RV64-NEXT: addw a0, a0, a1
; RV32ZBT-NEXT: srai a0, a0, 1 ; RV64-NEXT: sraiw a0, a0, 1
; RV32ZBT-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV32ZBT-NEXT: ret ; RV64-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srliw a1, a0, 31
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: sdiv32_pow2_negative_2:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srliw a1, a0, 31
; RV64ZBT-NEXT: addw a0, a0, a1
; RV64ZBT-NEXT: sraiw a0, a0, 1
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, -2 %div = sdiv i32 %a, -2
ret i32 %div ret i32 %div
} }
define i32 @sdiv32_pow2_2048(i32 %a) { define i32 @sdiv32_pow2_2048(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_2048: ; RV32I-LABEL: sdiv32_pow2_2048:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; RV64ZBT-NEXT: neg a0, a0 ; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret ; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, -2048 %div = sdiv i32 %a, -2048
ret i32 %div ret i32 %div
} }
define i32 @sdiv32_pow2_4096(i32 %a) { define i32 @sdiv32_pow2_4096(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_4096: ; RV32-LABEL: sdiv32_pow2_4096:
; RV32I: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31 ; RV32-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 20 ; RV32-NEXT: srli a1, a1, 20
; RV32I-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 12 ; RV32-NEXT: srai a0, a0, 12
; RV32I-NEXT: ret ; RV32-NEXT: ret
; ;
; RV32ZBT-LABEL: sdiv32_pow2_4096: ; RV64-LABEL: sdiv32_pow2_4096:
; RV32ZBT: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV32ZBT-NEXT: srai a1, a0, 31 ; RV64-NEXT: sraiw a1, a0, 31
; RV32ZBT-NEXT: srli a1, a1, 20 ; RV64-NEXT: srliw a1, a1, 20
; RV32ZBT-NEXT: add a0, a0, a1 ; RV64-NEXT: addw a0, a0, a1
; RV32ZBT-NEXT: srai a0, a0, 12 ; RV64-NEXT: sraiw a0, a0, 12
; RV32ZBT-NEXT: ret ; RV64-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_4096:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 20
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 12
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: sdiv32_pow2_4096:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: sraiw a1, a0, 31
; RV64ZBT-NEXT: srliw a1, a1, 20
; RV64ZBT-NEXT: addw a0, a0, a1
; RV64ZBT-NEXT: sraiw a0, a0, 12
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, 4096 %div = sdiv i32 %a, 4096
ret i32 %div ret i32 %div
} }
define i32 @sdiv32_pow2_negative_4096(i32 %a) { define i32 @sdiv32_pow2_negative_4096(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_4096: ; RV32-LABEL: sdiv32_pow2_negative_4096:
; RV32I: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31 ; RV32-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 20 ; RV32-NEXT: srli a1, a1, 20
; RV32I-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 12 ; RV32-NEXT: srai a0, a0, 12
; RV32I-NEXT: neg a0, a0 ; RV32-NEXT: neg a0, a0
; RV32I-NEXT: ret ; RV32-NEXT: ret
; ;
; RV32ZBT-LABEL: sdiv32_pow2_negative_4096: ; RV64-LABEL: sdiv32_pow2_negative_4096:
; RV32ZBT: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV32ZBT-NEXT: srai a1, a0, 31 ; RV64-NEXT: sraiw a1, a0, 31
; RV32ZBT-NEXT: srli a1, a1, 20 ; RV64-NEXT: srliw a1, a1, 20
; RV32ZBT-NEXT: add a0, a0, a1 ; RV64-NEXT: addw a0, a0, a1
; RV32ZBT-NEXT: srai a0, a0, 12 ; RV64-NEXT: sraiw a0, a0, 12
; RV32ZBT-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV32ZBT-NEXT: ret ; RV64-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_4096:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 20
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 12
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: sdiv32_pow2_negative_4096:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: sraiw a1, a0, 31
; RV64ZBT-NEXT: srliw a1, a1, 20
; RV64ZBT-NEXT: addw a0, a0, a1
; RV64ZBT-NEXT: sraiw a0, a0, 12
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, -4096 %div = sdiv i32 %a, -4096
ret i32 %div ret i32 %div
} }
define i32 @sdiv32_pow2_65536(i32 %a) { define i32 @sdiv32_pow2_65536(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_65536: ; RV32-LABEL: sdiv32_pow2_65536:
; RV32I: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31 ; RV32-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 16 ; RV32-NEXT: srli a1, a1, 16
; RV32I-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 16 ; RV32-NEXT: srai a0, a0, 16
; RV32I-NEXT: ret ; RV32-NEXT: ret
; ;
; RV32ZBT-LABEL: sdiv32_pow2_65536: ; RV64-LABEL: sdiv32_pow2_65536:
; RV32ZBT: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV32ZBT-NEXT: srai a1, a0, 31 ; RV64-NEXT: sraiw a1, a0, 31
; RV32ZBT-NEXT: srli a1, a1, 16 ; RV64-NEXT: srliw a1, a1, 16
; RV32ZBT-NEXT: add a0, a0, a1 ; RV64-NEXT: addw a0, a0, a1
; RV32ZBT-NEXT: srai a0, a0, 16 ; RV64-NEXT: sraiw a0, a0, 16
; RV32ZBT-NEXT: ret ; RV64-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_65536:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 16
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: sdiv32_pow2_65536:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: sraiw a1, a0, 31
; RV64ZBT-NEXT: srliw a1, a1, 16
; RV64ZBT-NEXT: addw a0, a0, a1
; RV64ZBT-NEXT: sraiw a0, a0, 16
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, 65536 %div = sdiv i32 %a, 65536
ret i32 %div ret i32 %div
} }
define i32 @sdiv32_pow2_negative_65536(i32 %a) { define i32 @sdiv32_pow2_negative_65536(i32 %a) {
; RV32I-LABEL: sdiv32_pow2_negative_65536: ; RV32-LABEL: sdiv32_pow2_negative_65536:
; RV32I: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32I-NEXT: srai a1, a0, 31 ; RV32-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 16 ; RV32-NEXT: srli a1, a1, 16
; RV32I-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32I-NEXT: srai a0, a0, 16 ; RV32-NEXT: srai a0, a0, 16
; RV32I-NEXT: neg a0, a0 ; RV32-NEXT: neg a0, a0
; RV32I-NEXT: ret ; RV32-NEXT: ret
; ;
; RV32ZBT-LABEL: sdiv32_pow2_negative_65536: ; RV64-LABEL: sdiv32_pow2_negative_65536:
; RV32ZBT: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV32ZBT-NEXT: srai a1, a0, 31 ; RV64-NEXT: sraiw a1, a0, 31
; RV32ZBT-NEXT: srli a1, a1, 16 ; RV64-NEXT: srliw a1, a1, 16
; RV32ZBT-NEXT: add a0, a0, a1 ; RV64-NEXT: addw a0, a0, a1
; RV32ZBT-NEXT: srai a0, a0, 16 ; RV64-NEXT: sraiw a0, a0, 16
; RV32ZBT-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV32ZBT-NEXT: ret ; RV64-NEXT: ret
;
; RV64I-LABEL: sdiv32_pow2_negative_65536:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: sraiw a0, a0, 16
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: sdiv32_pow2_negative_65536:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: sraiw a1, a0, 31
; RV64ZBT-NEXT: srliw a1, a1, 16
; RV64ZBT-NEXT: addw a0, a0, a1
; RV64ZBT-NEXT: sraiw a0, a0, 16
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i32 %a, -65536 %div = sdiv i32 %a, -65536
ret i32 %div ret i32 %div
} }
define i64 @sdiv64_pow2_2(i64 %a) { define i64 @sdiv64_pow2_2(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_2: ; RV32I-LABEL: sdiv64_pow2_2:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 12 Lines
; RV32ZBT-NEXT: srli a2, a1, 31 ; RV32ZBT-NEXT: srli a2, a1, 31
; RV32ZBT-NEXT: add a2, a0, a2 ; RV32ZBT-NEXT: add a2, a0, a2
; RV32ZBT-NEXT: sltu a0, a2, a0 ; RV32ZBT-NEXT: sltu a0, a2, a0
; RV32ZBT-NEXT: add a1, a1, a0 ; RV32ZBT-NEXT: add a1, a1, a0
; RV32ZBT-NEXT: fsri a0, a2, a1, 1 ; RV32ZBT-NEXT: fsri a0, a2, a1, 1
; RV32ZBT-NEXT: srai a1, a1, 1 ; RV32ZBT-NEXT: srai a1, a1, 1
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_2: ; RV64-LABEL: sdiv64_pow2_2:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srli a1, a0, 63 ; RV64-NEXT: srli a1, a0, 63
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 1 ; RV64-NEXT: srai a0, a0, 1
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_2:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srli a1, a0, 63
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 1
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, 2 %div = sdiv i64 %a, 2
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_negative_2(i64 %a) { define i64 @sdiv64_pow2_negative_2(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_2: ; RV32I-LABEL: sdiv64_pow2_negative_2:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 20 Lines
; RV32ZBT-NEXT: fsri a2, a2, a1, 1 ; RV32ZBT-NEXT: fsri a2, a2, a1, 1
; RV32ZBT-NEXT: neg a0, a2 ; RV32ZBT-NEXT: neg a0, a2
; RV32ZBT-NEXT: snez a2, a2 ; RV32ZBT-NEXT: snez a2, a2
; RV32ZBT-NEXT: srai a1, a1, 1 ; RV32ZBT-NEXT: srai a1, a1, 1
; RV32ZBT-NEXT: add a1, a1, a2 ; RV32ZBT-NEXT: add a1, a1, a2
; RV32ZBT-NEXT: neg a1, a1 ; RV32ZBT-NEXT: neg a1, a1
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_negative_2: ; RV64-LABEL: sdiv64_pow2_negative_2:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srli a1, a0, 63 ; RV64-NEXT: srli a1, a0, 63
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 1 ; RV64-NEXT: srai a0, a0, 1
; RV64I-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_negative_2:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srli a1, a0, 63
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 1
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, -2 %div = sdiv i64 %a, -2
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_2048(i64 %a) { define i64 @sdiv64_pow2_2048(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_2048: ; RV32I-LABEL: sdiv64_pow2_2048:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; RV32ZBT-NEXT: srli a2, a2, 20 ; RV32ZBT-NEXT: srli a2, a2, 20
; RV32ZBT-NEXT: add a2, a0, a2 ; RV32ZBT-NEXT: add a2, a0, a2
; RV32ZBT-NEXT: sltu a0, a2, a0 ; RV32ZBT-NEXT: sltu a0, a2, a0
; RV32ZBT-NEXT: add a1, a1, a0 ; RV32ZBT-NEXT: add a1, a1, a0
; RV32ZBT-NEXT: fsri a0, a2, a1, 12 ; RV32ZBT-NEXT: fsri a0, a2, a1, 12
; RV32ZBT-NEXT: srai a1, a1, 12 ; RV32ZBT-NEXT: srai a1, a1, 12
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_4096: ; RV64-LABEL: sdiv64_pow2_4096:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63 ; RV64-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 52 ; RV64-NEXT: srli a1, a1, 52
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 12 ; RV64-NEXT: srai a0, a0, 12
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_4096:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srai a1, a0, 63
; RV64ZBT-NEXT: srli a1, a1, 52
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 12
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, 4096 %div = sdiv i64 %a, 4096
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_negative_4096(i64 %a) { define i64 @sdiv64_pow2_negative_4096(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_4096: ; RV32I-LABEL: sdiv64_pow2_negative_4096:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 22 Lines
; RV32ZBT-NEXT: fsri a2, a2, a1, 12 ; RV32ZBT-NEXT: fsri a2, a2, a1, 12
; RV32ZBT-NEXT: neg a0, a2 ; RV32ZBT-NEXT: neg a0, a2
; RV32ZBT-NEXT: snez a2, a2 ; RV32ZBT-NEXT: snez a2, a2
; RV32ZBT-NEXT: srai a1, a1, 12 ; RV32ZBT-NEXT: srai a1, a1, 12
; RV32ZBT-NEXT: add a1, a1, a2 ; RV32ZBT-NEXT: add a1, a1, a2
; RV32ZBT-NEXT: neg a1, a1 ; RV32ZBT-NEXT: neg a1, a1
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_negative_4096: ; RV64-LABEL: sdiv64_pow2_negative_4096:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63 ; RV64-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 52 ; RV64-NEXT: srli a1, a1, 52
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 12 ; RV64-NEXT: srai a0, a0, 12
; RV64I-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_negative_4096:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srai a1, a0, 63
; RV64ZBT-NEXT: srli a1, a1, 52
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 12
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, -4096 %div = sdiv i64 %a, -4096
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_65536(i64 %a) { define i64 @sdiv64_pow2_65536(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_65536: ; RV32I-LABEL: sdiv64_pow2_65536:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 14 Lines
; RV32ZBT-NEXT: srli a2, a2, 16 ; RV32ZBT-NEXT: srli a2, a2, 16
; RV32ZBT-NEXT: add a2, a0, a2 ; RV32ZBT-NEXT: add a2, a0, a2
; RV32ZBT-NEXT: sltu a0, a2, a0 ; RV32ZBT-NEXT: sltu a0, a2, a0
; RV32ZBT-NEXT: add a1, a1, a0 ; RV32ZBT-NEXT: add a1, a1, a0
; RV32ZBT-NEXT: fsri a0, a2, a1, 16 ; RV32ZBT-NEXT: fsri a0, a2, a1, 16
; RV32ZBT-NEXT: srai a1, a1, 16 ; RV32ZBT-NEXT: srai a1, a1, 16
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_65536: ; RV64-LABEL: sdiv64_pow2_65536:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63 ; RV64-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 48 ; RV64-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 16 ; RV64-NEXT: srai a0, a0, 16
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_65536:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srai a1, a0, 63
; RV64ZBT-NEXT: srli a1, a1, 48
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 16
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, 65536 %div = sdiv i64 %a, 65536
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_negative_65536(i64 %a) { define i64 @sdiv64_pow2_negative_65536(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_65536: ; RV32I-LABEL: sdiv64_pow2_negative_65536:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 22 Lines
; RV32ZBT-NEXT: fsri a2, a2, a1, 16 ; RV32ZBT-NEXT: fsri a2, a2, a1, 16
; RV32ZBT-NEXT: neg a0, a2 ; RV32ZBT-NEXT: neg a0, a2
; RV32ZBT-NEXT: snez a2, a2 ; RV32ZBT-NEXT: snez a2, a2
; RV32ZBT-NEXT: srai a1, a1, 16 ; RV32ZBT-NEXT: srai a1, a1, 16
; RV32ZBT-NEXT: add a1, a1, a2 ; RV32ZBT-NEXT: add a1, a1, a2
; RV32ZBT-NEXT: neg a1, a1 ; RV32ZBT-NEXT: neg a1, a1
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_negative_65536: ; RV64-LABEL: sdiv64_pow2_negative_65536:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63 ; RV64-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 48 ; RV64-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 16 ; RV64-NEXT: srai a0, a0, 16
; RV64I-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_negative_65536:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srai a1, a0, 63
; RV64ZBT-NEXT: srli a1, a1, 48
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 16
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, -65536 %div = sdiv i64 %a, -65536
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_8589934592(i64 %a) { define i64 @sdiv64_pow2_8589934592(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_8589934592: ; RV32I-LABEL: sdiv64_pow2_8589934592:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 15 Lines
; RV32ZBT-NEXT: fsri a1, a1, a1, 31 ; RV32ZBT-NEXT: fsri a1, a1, a1, 31
; RV32ZBT-NEXT: add a1, a0, a1 ; RV32ZBT-NEXT: add a1, a0, a1
; RV32ZBT-NEXT: sltu a0, a1, a0 ; RV32ZBT-NEXT: sltu a0, a1, a0
; RV32ZBT-NEXT: add a1, a2, a0 ; RV32ZBT-NEXT: add a1, a2, a0
; RV32ZBT-NEXT: srai a0, a1, 1 ; RV32ZBT-NEXT: srai a0, a1, 1
; RV32ZBT-NEXT: srai a1, a1, 31 ; RV32ZBT-NEXT: srai a1, a1, 31
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_8589934592: ; RV64-LABEL: sdiv64_pow2_8589934592:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63 ; RV64-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 31 ; RV64-NEXT: srli a1, a1, 31
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 33 ; RV64-NEXT: srai a0, a0, 33
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_8589934592:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srai a1, a0, 63
; RV64ZBT-NEXT: srli a1, a1, 31
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 33
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, 8589934592 ; 2^33 %div = sdiv i64 %a, 8589934592 ; 2^33
ret i64 %div ret i64 %div
} }
define i64 @sdiv64_pow2_negative_8589934592(i64 %a) { define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {
; RV32I-LABEL: sdiv64_pow2_negative_8589934592: ; RV32I-LABEL: sdiv64_pow2_negative_8589934592:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 23 Lines
; RV32ZBT-NEXT: srai a1, a0, 31 ; RV32ZBT-NEXT: srai a1, a0, 31
; RV32ZBT-NEXT: srai a0, a0, 1 ; RV32ZBT-NEXT: srai a0, a0, 1
; RV32ZBT-NEXT: snez a2, a0 ; RV32ZBT-NEXT: snez a2, a0
; RV32ZBT-NEXT: add a1, a1, a2 ; RV32ZBT-NEXT: add a1, a1, a2
; RV32ZBT-NEXT: neg a1, a1 ; RV32ZBT-NEXT: neg a1, a1
; RV32ZBT-NEXT: neg a0, a0 ; RV32ZBT-NEXT: neg a0, a0
; RV32ZBT-NEXT: ret ; RV32ZBT-NEXT: ret
; ;
; RV64I-LABEL: sdiv64_pow2_negative_8589934592: ; RV64-LABEL: sdiv64_pow2_negative_8589934592:
; RV64I: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64I-NEXT: srai a1, a0, 63 ; RV64-NEXT: srai a1, a0, 63
; RV64I-NEXT: srli a1, a1, 31 ; RV64-NEXT: srli a1, a1, 31
; RV64I-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64I-NEXT: srai a0, a0, 33 ; RV64-NEXT: srai a0, a0, 33
; RV64I-NEXT: neg a0, a0 ; RV64-NEXT: neg a0, a0
; RV64I-NEXT: ret ; RV64-NEXT: ret
;
; RV64ZBT-LABEL: sdiv64_pow2_negative_8589934592:
; RV64ZBT: # %bb.0: # %entry
; RV64ZBT-NEXT: srai a1, a0, 63
; RV64ZBT-NEXT: srli a1, a1, 31
; RV64ZBT-NEXT: add a0, a0, a1
; RV64ZBT-NEXT: srai a0, a0, 33
; RV64ZBT-NEXT: neg a0, a0
; RV64ZBT-NEXT: ret
entry: entry:
%div = sdiv i64 %a, -8589934592 ; -2^33 %div = sdiv i64 %a, -8589934592 ; -2^33
ret i64 %div ret i64 %div
} }