[AArch64] Reserve more physical registers

[Carrot]

Summary

Reserved physical registers can't be assigned to virtual registers, but they can still be used as ABI required. So we can reserve X8, X16, X17 and X19.

Similarly argument registers can be reserved even if they are used by function call.

With this change we can reserve most of the physical registers, it is much easier to test and debug register allocator.

[kristof.beyls]

My understanding is that X8, X16, X17 and X19 cannot be reserved because the code generator in places will make use of them.
For example, using X19 as a base register in some cases. X16 and X17 are defined by the ABI to potentially be clobbered on function calls & when a veneer needs to be inserted by a linker, it does get clobbered. IIRC, some of the security mitigations implemented in LLVM also clobber these 2 registers on function calls.
I'm not fully sure why X8 cannot be reserved.

In short, I don't think it's a good idea to enable users to reserve these registers as the compiler/toolchain/ABI will not respect their request to reserve these registers.

It seems your motivation for being able to reserve more registers is to be able to more easily write regression test for register allocation.
Are there other ways to achieve that?

[Carrot]

A reserved physical register doesn't mean it can't be used by compiler/linker, it just means it can't be used by register allocator, see the comments in TargetRegisterInfo::getReservedRegs(). The most common example is the stack pointer. So when we reserve X8, X16, X17 and X19, it means we can't allocate them to virtual registers, compiler/linker can still use X8 to pass return address, and use X16 and X17 in a veneer.

[kristof.beyls]

See https://reviews.llvm.org/D56305 and https://reviews.llvm.org/D48580 for previous related discussions.
I think it would be helpful to understand the use case for being able to reserve x8, x16, x17 and x19 better.

[Carrot]

I want to reserve most of the physical registers, so only a small number of registers can be used by register allocator. Then I can write small test cases to simulate high register pressure situation, it will be much easier to test and debug register allocation changes.

[efriedma]

A reserved physical register doesn't mean it can't be used by compiler/linker, it just means it can't be used by register allocator, see the comments in TargetRegisterInfo::getReservedRegs().

The target feature to "reserve" a register is meant to be "don't use this register for anything". For some registers, making sure the register isn't used by the register allocator is sufficient because the compiler/linker won't use them in any other way... but if the compiler uses a register outside register allocation, that doesn't work.

If you want a target feature to simulate high register pressure without any expectation that the resulting code actually works, please add a separate "regalloc-test-reserve-all-regs" feature or something like that.

[Carrot]

Thanks for the clarification, I will propose another patch for my purpose.

clang/lib/Driver/ToolChains/Arch/AArch64.cpp

if (Args.hasArg(options::OPT_ffixed_x5))
     Features.push_back("+reserve-x5");
 
   if (Args.hasArg(options::OPT_ffixed_x6))
     Features.push_back("+reserve-x6");
 
   if (Args.hasArg(options::OPT_ffixed_x7))
     Features.push_back("+reserve-x7");
 
+  if (Args.hasArg(options::OPT_ffixed_x8))
+    Features.push_back("+reserve-x8");
+
   if (Args.hasArg(options::OPT_ffixed_x9))
     Features.push_back("+reserve-x9");
 
   if (Args.hasArg(options::OPT_ffixed_x10))
     Features.push_back("+reserve-x10");
 
   if (Args.hasArg(options::OPT_ffixed_x11))
     Features.push_back("+reserve-x11");
 
   if (Args.hasArg(options::OPT_ffixed_x12))
     Features.push_back("+reserve-x12");
 
   if (Args.hasArg(options::OPT_ffixed_x13))
     Features.push_back("+reserve-x13");
 
   if (Args.hasArg(options::OPT_ffixed_x14))
     Features.push_back("+reserve-x14");
 
   if (Args.hasArg(options::OPT_ffixed_x15))
     Features.push_back("+reserve-x15");
 
+  if (Args.hasArg(options::OPT_ffixed_x16))
+    Features.push_back("+reserve-x16");
+
+  if (Args.hasArg(options::OPT_ffixed_x17))
+    Features.push_back("+reserve-x17");
+
   if (Args.hasArg(options::OPT_ffixed_x18))
     Features.push_back("+reserve-x18");
 
+  if (Args.hasArg(options::OPT_ffixed_x19))
+    Features.push_back("+reserve-x19");
+
   if (Args.hasArg(options::OPT_ffixed_x20))
     Features.push_back("+reserve-x20");
 
   if (Args.hasArg(options::OPT_ffixed_x21))
     Features.push_back("+reserve-x21");
 
   if (Args.hasArg(options::OPT_ffixed_x22))
     Features.push_back("+reserve-x22");

llvm/lib/Target/AArch64/AArch64.td

def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
     "HasZeroCycleZeroingFPWorkaround", "true",
     "The zero-cycle floating-point zeroing instruction has a bug">;
 
 def FeatureStrictAlign : SubtargetFeature<"strict-align",
                                           "RequiresStrictAlign", "true",
                                           "Disallow all unaligned memory "
                                           "access">;
 
-foreach i = {1-7,9-15,18,20-28,30} in
+foreach i = {1-28,30} in
     def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
                                              "Reserve X"#i#", making it unavailable "
                                              "as a GPR">;
 
 foreach i = {8-15,18} in
     def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
          "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
 

llvm/lib/Target/AArch64/AArch64FastISel.cpp

if (Subtarget->isTargetWindows() && Addr.getGlobalValue() &&
       Addr.getGlobalValue()->hasExternalWeakLinkage())
     return false;
 
   // Handle the arguments now that we've gotten them.
   unsigned NumBytes;
   if (!processCallArgs(CLI, OutVTs, NumBytes))
     return false;
 
-  const AArch64RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
-  if (RegInfo->isAnyArgRegReserved(*MF))
-    RegInfo->emitReservedArgRegCallError(*MF);
-
   // Issue the call.
   MachineInstrBuilder MIB;
   if (Subtarget->useSmallAddressing()) {
     const MCInstrDesc &II =
         TII.get(Addr.getReg() ? getBLRCallOpcode(*MF) : (unsigned)AArch64::BL);
     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
     if (Symbol)
       MIB.addSym(Symbol, 0);

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (!Mask) {
       Mask = TRI->getCallPreservedMask(MF, CallConv);
     }
   } else
     Mask = TRI->getCallPreservedMask(MF, CallConv);
 
   if (Subtarget->hasCustomCallingConv())
     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
 
-  if (TRI->isAnyArgRegReserved(MF))
-    TRI->emitReservedArgRegCallError(MF);
-
   assert(Mask && "Missing call preserved mask for calling convention");
   Ops.push_back(DAG.getRegisterMask(Mask));
 
   if (InFlag.getNode())
     Ops.push_back(InFlag);
 
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
 

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

public:
   AArch64RegisterInfo(const Triple &TT);
 
   // FIXME: This should be tablegen'd like getDwarfRegNum is
   int getSEHRegNum(unsigned i) const {
     return getEncodingValue(i);
   }
 
   bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
-  bool isAnyArgRegReserved(const MachineFunction &MF) const;
-  void emitReservedArgRegCallError(const MachineFunction &MF) const;
 
   void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
   void UpdateCustomCallPreservedMask(MachineFunction &MF,
                                      const uint32_t **Mask) const;
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const MCPhysReg *getDarwinCalleeSavedRegs(const MachineFunction *MF) const;

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   return Reserved;
 }
 
 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
                                         MCRegister Reg) const {
   return getReservedRegs(MF)[Reg];
 }
 
-bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
-  return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
-    return isReservedReg(MF, r);
-  });
-}
-
-void AArch64RegisterInfo::emitReservedArgRegCallError(
-    const MachineFunction &MF) const {
-  const Function &F = MF.getFunction();
-  F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
-    " function calls if any of the argument registers is reserved.")});
-}
-
 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                           MCRegister PhysReg) const {
   return !isReservedReg(MF, PhysReg);
 }
 
 bool AArch64RegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
   return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
 }

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

bool AArch64CallLowering::lowerTailCall(
   // Tell the call which registers are clobbered.
   const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   auto TRI = Subtarget.getRegisterInfo();
   const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
   if (Subtarget.hasCustomCallingConv())
     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
   MIB.addRegMask(Mask);
 
-  if (TRI->isAnyArgRegReserved(MF))
-    TRI->emitReservedArgRegCallError(MF);
-
   // FPDiff is the byte offset of the call's argument area from the callee's.
   // Stores to callee stack arguments will be placed in FixedStackSlots offset
   // by this amount for a tail call. In a sibling call it must be 0 because the
   // caller will deallocate the entire stack and the callee still expects its
   // arguments to begin at SP+0.
   int FPDiff = 0;
 
   // This will be 0 for sibcalls, potentially nonzero for tail calls produced
if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
     return false;
 
   Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
 
   if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
   MIB.addRegMask(Mask);
 
-  if (TRI->isAnyArgRegReserved(MF))
-    TRI->emitReservedArgRegCallError(MF);
-
   // Now we can add the actual call instruction to the correct basic block.
   MIRBuilder.insertInstr(MIB);
 
   // If Callee is a reg, since it is used by a target specific
   // instruction, it must have a register class matching the
   // constraint of that instruction.
   if (MIB->getOperand(CalleeOpNo).isReg())
     constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),

llvm/test/CodeGen/AArch64/arm64-platform-reg.ll

 ; RUN: llc -mtriple=arm64-apple-ios -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18
 ; RUN: llc -mtriple=arm64-freebsd-gnu -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18
 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-android -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18
 ; RUN: llc -mtriple=aarch64-fuchsia -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18
 ; RUN: llc -mtriple=aarch64-windows -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18
 
 ; Test reserve-x# options individually.
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x1 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X1
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x2 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X2
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x3 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X3
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x4 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X4
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x5 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X5
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x6 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X6
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x7 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X7
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x8 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X8
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x9 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X9
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x10 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X10
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x11 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X11
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x12 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X12
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x13 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X13
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x14 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X14
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x15 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X15
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x16 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X16
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x17 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X17
+; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x19 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X19
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x20 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X20
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x21 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X21
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x22 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X22
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x23 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X23
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x24 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X24
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x25 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X25
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x26 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X26
 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x27 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X27

 ; RUN: llc -mtriple=arm64-linux-gnu \
 ; RUN: -mattr=+reserve-x1 \
 ; RUN: -mattr=+reserve-x2 \
 ; RUN: -mattr=+reserve-x3 \
 ; RUN: -mattr=+reserve-x4 \
 ; RUN: -mattr=+reserve-x5 \
 ; RUN: -mattr=+reserve-x6 \
 ; RUN: -mattr=+reserve-x7 \
+; RUN: -mattr=+reserve-x8 \
 ; RUN: -mattr=+reserve-x9 \
 ; RUN: -mattr=+reserve-x10 \
 ; RUN: -mattr=+reserve-x11 \
 ; RUN: -mattr=+reserve-x12 \
 ; RUN: -mattr=+reserve-x13 \
 ; RUN: -mattr=+reserve-x14 \
 ; RUN: -mattr=+reserve-x15 \
+; RUN: -mattr=+reserve-x16 \
+; RUN: -mattr=+reserve-x17 \
 ; RUN: -mattr=+reserve-x18 \
+; RUN: -mattr=+reserve-x19 \
 ; RUN: -mattr=+reserve-x20 \
 ; RUN: -mattr=+reserve-x21 \
 ; RUN: -mattr=+reserve-x22 \
 ; RUN: -mattr=+reserve-x23 \
 ; RUN: -mattr=+reserve-x24 \
 ; RUN: -mattr=+reserve-x25 \
 ; RUN: -mattr=+reserve-x26 \
 ; RUN: -mattr=+reserve-x27 \
 ; RUN: -mattr=+reserve-x28 \
 ; RUN: -mattr=+reserve-x30 \
 ; RUN: -o - %s | FileCheck %s \
 ; RUN: --check-prefix=CHECK-RESERVE \
 ; RUN: --check-prefix=CHECK-RESERVE-X1 \
 ; RUN: --check-prefix=CHECK-RESERVE-X2 \
 ; RUN: --check-prefix=CHECK-RESERVE-X3 \
 ; RUN: --check-prefix=CHECK-RESERVE-X4 \
 ; RUN: --check-prefix=CHECK-RESERVE-X5 \
 ; RUN: --check-prefix=CHECK-RESERVE-X6 \
 ; RUN: --check-prefix=CHECK-RESERVE-X7 \
+; RUN: --check-prefix=CHECK-RESERVE-X8 \
 ; RUN: --check-prefix=CHECK-RESERVE-X9 \
 ; RUN: --check-prefix=CHECK-RESERVE-X10 \
 ; RUN: --check-prefix=CHECK-RESERVE-X11 \
 ; RUN: --check-prefix=CHECK-RESERVE-X12 \
 ; RUN: --check-prefix=CHECK-RESERVE-X13 \
 ; RUN: --check-prefix=CHECK-RESERVE-X14 \
 ; RUN: --check-prefix=CHECK-RESERVE-X15 \
+; RUN: --check-prefix=CHECK-RESERVE-X16 \
+; RUN: --check-prefix=CHECK-RESERVE-X17 \
 ; RUN: --check-prefix=CHECK-RESERVE-X18 \
+; RUN: --check-prefix=CHECK-RESERVE-X19 \
 ; RUN: --check-prefix=CHECK-RESERVE-X20 \
 ; RUN: --check-prefix=CHECK-RESERVE-X21 \
 ; RUN: --check-prefix=CHECK-RESERVE-X22 \
 ; RUN: --check-prefix=CHECK-RESERVE-X23 \
 ; RUN: --check-prefix=CHECK-RESERVE-X24 \
 ; RUN: --check-prefix=CHECK-RESERVE-X25 \
 ; RUN: --check-prefix=CHECK-RESERVE-X26 \
 ; RUN: --check-prefix=CHECK-RESERVE-X27 \

 define void @keep_live() {
   %val = load volatile [30 x i64], [30 x i64]* @var
   store volatile [30 x i64] %val, [30 x i64]* @var
 
 ; CHECK: ldr x18
 ; CHECK: str x18
 
 ; CHECK-RESERVE-NOT: ldr fp
+; CHECK-RESERVE-X8-NOT: adrp x8
+; CHECK-RESERVE-X8-NOT: ldr x8
 ; CHECK-RESERVE-X1-NOT: ldr x1,
 ; CHECK-RESERVE-X2-NOT: ldr x2,
 ; CHECK-RESERVE-X3-NOT: ldr x3,
 ; CHECK-RESERVE-X4-NOT: ldr x4,
 ; CHECK-RESERVE-X5-NOT: ldr x5,
 ; CHECK-RESERVE-X6-NOT: ldr x6,
 ; CHECK-RESERVE-X7-NOT: ldr x7,
 ; CHECK-RESERVE-X9-NOT: ldr x9,
 ; CHECK-RESERVE-X10-NOT: ldr x10,
 ; CHECK-RESERVE-X11-NOT: ldr x11,
 ; CHECK-RESERVE-X12-NOT: ldr x12,
 ; CHECK-RESERVE-X13-NOT: ldr x13,
 ; CHECK-RESERVE-X14-NOT: ldr x14,
 ; CHECK-RESERVE-X15-NOT: ldr x15,
+; CHECK-RESERVE-X16-NOT: ldr x16
+; CHECK-RESERVE-X17-NOT: ldr x17
 ; CHECK-RESERVE-X18-NOT: ldr x18
+; CHECK-RESERVE-X19-NOT: ldr x19
 ; CHECK-RESERVE-X20-NOT: ldr x20
 ; CHECK-RESERVE-X21-NOT: ldr x21
 ; CHECK-RESERVE-X22-NOT: ldr x22
 ; CHECK-RESERVE-X23-NOT: ldr x23
 ; CHECK-RESERVE-X24-NOT: ldr x24
 ; CHECK-RESERVE-X25-NOT: ldr x25
 ; CHECK-RESERVE-X26-NOT: ldr x26
 ; CHECK-RESERVE-X27-NOT: ldr x27

 ; CHECK-RESERVE-X7-NOT: ldr x7,
 ; CHECK-RESERVE-X9-NOT: ldr x9,
 ; CHECK-RESERVE-X10-NOT: ldr x10,
 ; CHECK-RESERVE-X11-NOT: ldr x11,
 ; CHECK-RESERVE-X12-NOT: ldr x12,
 ; CHECK-RESERVE-X13-NOT: ldr x13,
 ; CHECK-RESERVE-X14-NOT: ldr x14,
 ; CHECK-RESERVE-X15-NOT: ldr x15,
+; CHECK-RESERVE-X16-NOT: ldr x16
+; CHECK-RESERVE-X17-NOT: ldr x17
 ; CHECK-RESERVE-X18-NOT: ldr x18
+; CHECK-RESERVE-X19-NOT: ldr x19
 ; CHECK-RESERVE-X20-NOT: ldr x20
 ; CHECK-RESERVE-X21-NOT: ldr x21
 ; CHECK-RESERVE-X22-NOT: ldr x22
 ; CHECK-RESERVE-X23-NOT: ldr x23
 ; CHECK-RESERVE-X24-NOT: ldr x24
 ; CHECK-RESERVE-X25-NOT: ldr x25
 ; CHECK-RESERVE-X26-NOT: ldr x26
 ; CHECK-RESERVE-X27-NOT: ldr x27
 ; CHECK-RESERVE-X28-NOT: ldr x28
 ; CHECK-RESERVE-X30-NOT: ldr x30
 ; CHECK-RESERVE: ret
   ret void
 }

llvm/test/CodeGen/AArch64/arm64-reserved-arg-reg-call-error.ll

-; RUN: not llc < %s -mtriple=arm64-linux-gnu -mattr=+reserve-x1 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnu -mattr=+reserve-x1 -fast-isel 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnu -mattr=+reserve-x1 -global-isel 2>&1 | FileCheck %s
-
-; CHECK: error:
-; CHECK-SAME: AArch64 doesn't support function calls if any of the argument registers is reserved.
-define void @call_function() {
-  call void @foo()
-  ret void
-}
-declare void @foo()
-
-; CHECK: error:
-; CHECK-SAME: AArch64 doesn't support function calls if any of the argument registers is reserved.
-define void @call_memcpy(i8* %out, i8* %in) {
-  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 800, i1 false)
-  ret void
-}
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)