Use ISA versions instead of attributes to determine intrinsic legality.

[Leonc]

Summary

Subtarget attributes are not guaranteed to match those of the actual hardware. This can cause the compiler to crash in some circumstances.
Modify intrinsic lowering to be conditional on ISA version numbers instead of subtarget attributes.

[bcahoon]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

7826

Why can't the compiler continue to use the attribute?

[Leonc]

Abandoning in favour of updating device-libs.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsR600.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/KnownBits.h"
+#include "llvm/Support/TargetParser.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "si-lower"
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 
 static cl::opt<bool> DisableLoopAlignment(
case Intrinsic::amdgcn_flat_atomic_fmax: {
     MemSDNode *M = cast<MemSDNode>(Op);
     SDValue Ops[] = {
       M->getOperand(0), // Chain
       M->getOperand(2), // Ptr
       M->getOperand(3)  // Value
     };
     unsigned Opcode = 0;
     switch (IntrID) {
-    case Intrinsic::amdgcn_global_atomic_fadd:
-      if (!Subtarget->hasAtomicFaddNoRtnInsts())
+    case Intrinsic::amdgcn_global_atomic_fadd: {
+      auto IV = AMDGPU::getIsaVersion(Subtarget->getCPU());
+      auto IVTupl = std::make_tuple(IV.Major, IV.Minor, IV.Stepping);
+      using TuplTy = decltype(IVTupl);
+      // Emit `v_illegal` if ISA version is between gfx908 and gfx940
+      // (inclusive), or if ISA version is gfx11 or above.
+      if ((IVTupl < TuplTy(9u, 0u, 8u)) ||
+          (IVTupl > TuplTy(9u, 4u, 0u) && IVTupl < TuplTy(11u, 0u, 0u)))
         return makeV_ILLEGAL(Op, DAG);
       [[fallthrough]];
+    }
     case Intrinsic::amdgcn_flat_atomic_fadd: {
       EVT VT = Op.getOperand(3).getValueType();
       return DAG.getAtomic(ISD::ATOMIC_LOAD_FADD, DL, VT,
                            DAG.getVTList(VT, MVT::Other), Ops,
                            M->getMemOperand());
     }
     case Intrinsic::amdgcn_global_atomic_fmin:
     case Intrinsic::amdgcn_flat_atomic_fmin: {

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll

main_body:
   %p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 -1
   %ret = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
   ret void
 }
 
 ; Make sure this artificially selects with an incorrect subtarget, but
 ; the feature set.
 ; GCN-LABEL: {{^}}global_atomic_fadd_f32_wrong_subtarget:
-; GCN: global_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
+; GCN-NOT: global_atomic_add_f32
+; GCN: v_illegal
 define amdgpu_kernel void @global_atomic_fadd_f32_wrong_subtarget(float addrspace(1)* %ptr, float %data) #0 {
   %ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %ptr, float %data)
   ret void
 }
 
 attributes #0 = { "target-cpu"="gfx803" "target-features"="+atomic-fadd-no-rtn-insts"}