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Differential D131950

[RISCV][test] Add pre-commit test for D131551.
ClosedPublic

Authored by jacquesguan on Aug 16 2022, 1:58 AM.

Details

Reviewers
reames
craig.topper
asb
luismarques
frasercrmck
benshi001
Commits
rG6392cf331a9b: [RISCV][test] Add pre-commit test for D131551.

Diff Detail

Unit TestsFailed

TimeTest
60,070 msx64 debian > BOLT.runtime/X86::exceptions-pic.test

Event Timeline

jacquesguan created this revision.Aug 16 2022, 1:58 AM
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Herald added subscribers: sunshaoce, VincentWu, luke957 and 26 others. · View Herald Transcript
jacquesguan requested review of this revision.Aug 16 2022, 1:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 16 2022, 1:58 AM
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jacquesguan added a child revision: D131551: [RISCV] Fold vector binary operatrion into select with identity constant..Aug 16 2022, 2:28 AM
Harbormaster completed remote builds in B181462: Diff 452922.Aug 16 2022, 2:47 AM
jacquesguan mentioned this in D131551: [RISCV] Fold vector binary operatrion into select with identity constant..Aug 16 2022, 6:55 PM
jacquesguan updated this revision to Diff 469481.Oct 21 2022, 12:03 AM

Add fp test.

Harbormaster completed remote builds in B193431: Diff 469481.Oct 21 2022, 12:40 AM
craig.topper accepted this revision.Dec 5 2022, 4:00 PM

LGTM

This revision is now accepted and ready to land.Dec 5 2022, 4:00 PM
This revision was landed with ongoing or failed builds.Dec 5 2022, 6:38 PM
Closed by commit rG6392cf331a9b: [RISCV][test] Add pre-commit test for D131551. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rG6392cf331a9b: [RISCV][test] Add pre-commit test for D131551..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
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49 lines
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32 lines
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Diff 469481

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll

Show First 20 Lines • Show All 884 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = add <vscale x 8 x i64> %splat1, %splat2 %v = add <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = add <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = add <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = add <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vadd_vv_mask_negative0_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vv_mask_negative0_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 1
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
%vc = add <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vadd_vv_mask_negative1_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vv_mask_negative1_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = add <vscale x 8 x i32> %va, %vs
%vd = add <vscale x 8 x i32> %vc, %vs
ret <vscale x 8 x i32> %vd
}

llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

Show First 20 Lines • Show All 1,375 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = and <vscale x 8 x i64> %splat1, %splat2 %v = and <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vand_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%allones = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %allones
%vc = and <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vand_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
%vc = and <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vand_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
%vc = and <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll

Show First 20 Lines • Show All 1,178 Lines • ▼ Show 20 Lines
; RV64-V-NEXT: vsra.vi v8, v8, 1 ; RV64-V-NEXT: vsra.vi v8, v8, 1
; RV64-V-NEXT: vadd.vv v8, v8, v16 ; RV64-V-NEXT: vadd.vv v8, v8, v16
; RV64-V-NEXT: ret ; RV64-V-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = sdiv <vscale x 8 x i64> %va, %splat %vc = sdiv <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i32> @vdiv_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vdiv_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 1
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
%vc = sdiv <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vdiv_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vdiv_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 1
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
%vc = sdiv <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vdiv_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vdiv_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 1
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
%vc = sdiv <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll

Show First 20 Lines • Show All 1,191 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsrl.vv v8, v8, v16 ; CHECK-NEXT: vsrl.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i64> %splat, %vb %vc = shl <vscale x 8 x i64> %splat, %vb
%vd = udiv <vscale x 8 x i64> %va, %vc %vd = udiv <vscale x 8 x i64> %va, %vc
ret <vscale x 8 x i64> %vd ret <vscale x 8 x i64> %vd
} }
define <vscale x 8 x i32> @vdivu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vdivu_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 1
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
%vc = udiv <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vdivu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vdivu_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 1
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
%vc = udiv <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vdivu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vdivu_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 1
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
%vc = udiv <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x double> %splat, %va %vc = fadd <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc ret <vscale x 8 x double> %vc
} }
define <vscale x 8 x float> @vfadd_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfadd_vv_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
%vc = fadd fast <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfadd_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfadd_vf_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
%vc = fadd fast <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x double> %splat, %va %vc = fdiv <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc ret <vscale x 8 x double> %vc
} }
define <vscale x 8 x float> @vfdiv_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfdiv_vv_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
%vc = fdiv <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfdiv_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfdiv_vf_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
%vc = fdiv <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x double> %splat, %va %vc = fmul <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc ret <vscale x 8 x double> %vc
} }
define <vscale x 8 x float> @vfmul_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfmul_vv_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
%vc = fmul <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfmul_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfmul_vf_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
%vc = fmul <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: vfrsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x double> %splat, %va %vc = fsub <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc ret <vscale x 8 x double> %vc
} }
define <vscale x 8 x float> @vfsub_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfsub_vv_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
%vc = fsub fast <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfsub_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfsub_vf_mask_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
%vc = fsub fast <vscale x 8 x float> %va, %vs
ret <vscale x 8 x float> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll

Show First 20 Lines • Show All 884 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i64> %va, %splat %cmp = icmp ugt <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i32> @vmax_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmax_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vmaxu.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %vs
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmax_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vmaxu.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %vs
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmax_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmax_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, -3, v0
; CHECK-NEXT: vmaxu.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ugt <vscale x 8 x i32> %va, %vs
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll

Show First 20 Lines • Show All 884 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%cmp = icmp ult <vscale x 8 x i64> %va, %splat %cmp = icmp ult <vscale x 8 x i64> %va, %splat
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i32> @vmin_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmin_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, -1
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vminu.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%max = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %max
%cmp = icmp ult <vscale x 8 x i32> %va, %vs
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmin_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vminu.vv v8, v8, v12
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head1 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
%cmp = icmp ult <vscale x 8 x i32> %va, %vs
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmin_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmin_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, -1
; CHECK-NEXT: vmerge.vim v12, v12, -3, v0
; CHECK-NEXT: vminu.vv v8, v8, v12
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head1 = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
%splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
%cmp = icmp ult <vscale x 8 x i32> %va, %vs
%vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

Show First 20 Lines • Show All 953 Lines • ▼ Show 20 Lines
; RV64M-NEXT: ret ; RV64M-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = mul <vscale x 8 x i64> %splat1, %splat2 %v = mul <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmul_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 1
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
%vc = mul <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmul_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 1
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
%vc = mul <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmul_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 1
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
%vc = mul <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

Show First 20 Lines • Show All 1,168 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = or <vscale x 8 x i64> %splat1, %splat2 %v = or <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vor_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vor_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vor_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll

Show First 20 Lines • Show All 623 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i64> %va, %splat %vc = shl <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vshl_vv_mask_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vsll.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vshl_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsll.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vshl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vshl_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: li a0, 31
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsll.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll

Show First 20 Lines • Show All 796 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i64> %va, %splat %vc = ashr <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsra_vv_mask_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vsra.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsra_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsra.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsra_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: li a0, 31
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsra.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll

Show First 20 Lines • Show All 576 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i64> %va, %splat %vc = lshr <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
} }
define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsrl_vv_mask_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsrl_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vsrl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsrl_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: li a0, 31
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

Show First 20 Lines • Show All 862 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = sub <vscale x 8 x i64> %splat1, %splat2 %v = sub <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsub_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = sub <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsub_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = sub <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsub_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vsub.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = sub <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

Show First 20 Lines • Show All 1,375 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = xor <vscale x 8 x i64> %splat1, %splat2 %v = xor <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i32> @vxor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vxor_vv_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
; CHECK-NEXT: vxor.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = xor <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vxor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vxor_vx_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
; CHECK-NEXT: vxor.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = xor <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}
define <vscale x 8 x i32> @vxor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vxor_vi_mask_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
; CHECK-NEXT: vxor.vv v8, v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
%vc = xor <vscale x 8 x i32> %va, %vs
ret <vscale x 8 x i32> %vc
}