[RISCV] : Add support for immediate operands.

[MarkGoncharovAl]

Summary

Launching on RISCV machine llvm-exegesis to measure latency, I faced with troubles like: 'Operand is not set: ... <MCOperand INVALID>>; ... OpInfo.OperandType: 0'
(explanation: OperandType 0 means Unknown type).

Find out that this problem occurs with instructions:
C_ADDI
C_ADDIW
C_ADDI_HINT_IMM_ZERO
C_ANDI
C_FLD
C_FLW
C_LD
C_LW
C_SLLI
C_SRAI
C_SRLI
SHFLI
UNSHFLI
VADC_VIM
VADD_VI
VAND_VI
VMADC_VI
VMADC_VIM
VMERGE_VIM
VMSEQ_VI
VMSGTU_VI
VMSGT_VI
VMSLEU_VI
VMSLE_VI
VMSNE_VI
VOR_VI
VRSUB_VI
VSADDU_VI
VSADD_VI
VSETVLI
VXOR_VI

llvm-exegesis uses operand type information provided in tablegen files to initialize immediate arguments of the instruction. Some of them (listed above) simply don't have such information. Thus we should set into relevant immediate operands their specific type. Also create verification methods for them.

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

219

Stray blank line?

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

31

VI -> VTYPEI

42

This is never used in a pattern, why does it need ImmLeaf?

102

I don't think there are any instruction that uses this as an operand. Why do we need this change?

[MarkGoncharovAl]

Unuseful stray blank line was removed.

Operand VI was renamed to VTYPEI.

Operand type for SIMM5_NONZERO and unuseful ImmLeaf were removed.

Run testsuite - success.

[MarkGoncharovAl]

Diff to check new update relative to main branch.

[MarkGoncharovAl]

Please, take a look to review changes.

[craig.topper]

LGTM

[MarkGoncharovAl]

I do not have commit access.
Someone who has it, please, push this commit to upstream.

[steven.zhang]

In D131771#3738758, @MarkGoncharovAl wrote:

I do not have commit access.
Someone who has it, please, push this commit to upstream.

I will commit it for you.

[MarkGoncharovAl]

In D131771#3745095, @steven.zhang wrote:

In D131771#3738758, @MarkGoncharovAl wrote:

I do not have commit access.
Someone who has it, please, push this commit to upstream.

I will commit it for you.

Thank you

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM7,
+  OPERAND_UIMM7_LSB00,
+  OPERAND_UIMM8_LSB00,
+  OPERAND_UIMM8_LSB000,
   OPERAND_UIMM12,
+  OPERAND_ZERO,
+  OPERAND_SIMM5,
+  OPERAND_SIMM5_PLUS1,
+  OPERAND_SIMM6,
+  OPERAND_SIMM6_NONZERO,
   OPERAND_SIMM12,
   OPERAND_SIMM12_LSB00000,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
+  OPERAND_UIMMLOG2XLEN_NONZERO,
+  OPERAND_UIMM_SHFL,
+  OPERAND_VTYPEI10,
+  OPERAND_VTYPEI11,
   OPERAND_RVKRNUM,
   OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli
   // or vsetivli.
   OPERAND_AVL,
 };
 } // namespace RISCVOp

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

#define CASE_OPERAND_UIMM(NUM)                                                 \
   case RISCVOp::OPERAND_UIMM##NUM:                                             \
     Ok = isUInt<NUM>(Imm);                                                     \
     break;
         CASE_OPERAND_UIMM(2)
         CASE_OPERAND_UIMM(3)
         CASE_OPERAND_UIMM(4)
         CASE_OPERAND_UIMM(5)
         CASE_OPERAND_UIMM(7)
+        case RISCVOp::OPERAND_UIMM7_LSB00:
+          Ok = isShiftedUInt<5, 2>(Imm);
+          break;
+        case RISCVOp::OPERAND_UIMM8_LSB00:
+          Ok = isShiftedUInt<6, 2>(Imm);
+          break;
+        case RISCVOp::OPERAND_UIMM8_LSB000:
+          Ok = isShiftedUInt<5, 3>(Imm);
+          break;
         CASE_OPERAND_UIMM(12)
         CASE_OPERAND_UIMM(20)
           // clang-format on
+        case RISCVOp::OPERAND_ZERO:
+          Ok = Imm == 0;
+          break;
+        case RISCVOp::OPERAND_SIMM5:
+          Ok = isInt<5>(Imm);
+          break;
+        case RISCVOp::OPERAND_SIMM5_PLUS1:
+          Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
+          break;
+        case RISCVOp::OPERAND_SIMM6:
+          Ok = isInt<6>(Imm);
+          break;
+        case RISCVOp::OPERAND_SIMM6_NONZERO:
+          Ok = Imm != 0 && isInt<6>(Imm);
+          break;
+        case RISCVOp::OPERAND_VTYPEI10:
+          Ok = isUInt<10>(Imm);
+          break;
+        case RISCVOp::OPERAND_VTYPEI11:
+          Ok = isUInt<11>(Imm);
+          break;
         case RISCVOp::OPERAND_SIMM12:
           Ok = isInt<12>(Imm);
           break;
         case RISCVOp::OPERAND_SIMM12_LSB00000:
           Ok = isShiftedInt<7, 5>(Imm);
           break;
         case RISCVOp::OPERAND_UIMMLOG2XLEN:
-          if (STI.getTargetTriple().isArch64Bit())
-            Ok = isUInt<6>(Imm);
-          else
-            Ok = isUInt<5>(Imm);
+          Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
+                                                   : isUInt<5>(Imm);
+          break;
+        case RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO:
+          Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
+                                                   : isUInt<5>(Imm);
+          Ok = Ok && Imm != 0;
+          break;
+        case RISCVOp::OPERAND_UIMM_SHFL:
+          Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<5>(Imm)
+                                                   : isUInt<4>(Imm);
           break;
         case RISCVOp::OPERAND_RVKRNUM:
           Ok = Imm >= 0 && Imm <= 10;
           break;
         }
         if (!Ok) {
           ErrInfo = "Invalid immediate";
           return false;

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

 def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return isUInt<6>(Imm) && (Imm != 0);
   return isUInt<5>(Imm) && (Imm != 0);
 }]> {
   let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
   // TODO: should ensure invalid shamt is rejected when decoding.
   let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_UIMMLOG2XLEN_NONZERO";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     if (STI.getTargetTriple().isArch64Bit())
       return  isUInt<6>(Imm) && (Imm != 0);
     return isUInt<5>(Imm) && (Imm != 0);
   }];
 }
 
 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<6>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<6>";
+  let OperandType = "OPERAND_SIMM6";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<6>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
 def simm6nonzero : Operand<XLenVT>,
                    ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<6>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<6, "NonZero">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<6>";
+  let OperandType = "OPERAND_SIMM6_NONZERO";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return (Imm != 0) && isInt<6>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
 def immzero : Operand<XLenVT>,
               ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
   let ParserMatchClass = ImmZeroAsmOperand;
+  let OperandType = "OPERAND_ZERO";
+  let OperandNamespace = "RISCVOp";
 }
 
 def CLUIImmAsmOperand : AsmOperandClass {
   let Name = "CLUIImm";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = !strconcat("Invalid", Name);
 }
 

 }
 
 // A 7-bit unsigned immediate where the least significant two bits are zero.
 def uimm7_lsb00 : Operand<XLenVT>,
                   ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<7>";
+  let OperandType = "OPERAND_UIMM7_LSB00";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     return isShiftedUInt<5, 2>(Imm);
   }];
 }
 
 // A 8-bit unsigned immediate where the least significant two bits are zero.
 def uimm8_lsb00 : Operand<XLenVT>,
                   ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<8>";
+  let OperandType = "OPERAND_UIMM8_LSB00";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     return isShiftedUInt<6, 2>(Imm);
   }];
 }
 
 // A 8-bit unsigned immediate where the least significant three bits are zero.
 def uimm8_lsb000 : Operand<XLenVT>,
                    ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<8>";
+  let OperandType = "OPERAND_UIMM8_LSB000";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     return isShiftedUInt<5, 3>(Imm);
   }];
 }
 

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

class VTypeIAsmOperand<int VTypeINum> : AsmOperandClass {
   let DiagnosticType = "InvalidVTypeI";
   let RenderMethod = "addVTypeIOperands";
 }
 
 class VTypeIOp<int VTypeINum> : Operand<XLenVT> {
   let ParserMatchClass = VTypeIAsmOperand<VTypeINum>;
   let PrintMethod = "printVTypeI";
   let DecoderMethod = "decodeUImmOperand<"#VTypeINum#">";
+  let OperandType = "OPERAND_VTYPEI" # VTypeINum;
+  let OperandNamespace = "RISCVOp";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (MCOp.evaluateAsConstantImm(Imm))
+      return isUInt<VTypeINum>(Imm);
+    return MCOp.isBareSymbolRef();
+  }];
 }
 
 def VTypeIOp10 : VTypeIOp<10>;
 def VTypeIOp11 : VTypeIOp<11>;
 
 def VMaskAsmOperand : AsmOperandClass {
   let Name = "RVVMaskRegOpOperand";
   let RenderMethod = "addRegOperands";
   let PredicateMethod = "isV0Reg";
   let ParserMethod = "parseMaskReg";
   let IsOptional = 1;
   let DefaultMethod = "defaultMaskRegOp";
   let DiagnosticType = "InvalidVMaskRegister";
 }
 
 def VMaskOp : RegisterOperand<VMV0> {
   let ParserMatchClass = VMaskAsmOperand;
   let PrintMethod = "printVMaskReg";
   let EncoderMethod = "getVMaskReg";
   let DecoderMethod = "decodeVMaskReg";
 }
 
 def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<5>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<5>";
+  let OperandType = "OPERAND_SIMM5";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<5>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
 def SImm5Plus1AsmOperand : AsmOperandClass {
   let Name = "SImm5Plus1";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidSImm5Plus1";
 }
 
 def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
   [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
   let ParserMatchClass = SImm5Plus1AsmOperand;
+  let OperandType = "OPERAND_SIMM5_PLUS1";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
     return MCOp.isBareSymbolRef();
   }];
 }
 
 def simm5_plus1_nonzero : ImmLeaf<XLenVT,
   [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
 
 //===----------------------------------------------------------------------===//
 // Scheduling definitions.
 //===----------------------------------------------------------------------===//
 
 class VMVRSched<int n>: Sched <[!cast<SchedReadWrite>("WriteVMov" # n # "V"),
                                 !cast<SchedReadWrite>("ReadVMov" # n # "V")]>;
 
 class VLESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDE" # n),
                                 ReadVLDX, ReadVMask]>;
 
 class VSESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTE" # n),
                                 !cast<SchedReadWrite>("ReadVSTE" # n # "V"),
                                 ReadVSTX, ReadVMask]>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 
 def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return isUInt<5>(Imm);
   return isUInt<4>(Imm);
 }]> {
   let ParserMatchClass = UImmLog2XLenHalfAsmOperand;
   let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_UIMM_SHFL";
+  let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     if (STI.getTargetTriple().isArch64Bit())
       return  isUInt<5>(Imm);
     return isUInt<4>(Imm);
   }];